R600InstrInfo.h revision 0eca5fd919b0a31ea926b5f5072e5e56f7a55269 
1//===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Interface definition for R600InstrInfo
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef R600INSTRUCTIONINFO_H_
15#define R600INSTRUCTIONINFO_H_
16
17#include "AMDIL.h"
18#include "AMDGPUInstrInfo.h"
19#include "R600RegisterInfo.h"
20
21#include <map>
22
23namespace llvm {
24
25  class AMDGPUTargetMachine;
26  class DFAPacketizer;
27  class ScheduleDAG;
28  class MachineFunction;
29  class MachineInstr;
30  class MachineInstrBuilder;
31
32  class R600InstrInfo : public AMDGPUInstrInfo {
33  private:
34  const R600RegisterInfo RI;
35  AMDGPUTargetMachine &TM;
36
37  int getBranchInstr(const MachineOperand &op) const;
38
39  public:
40  explicit R600InstrInfo(AMDGPUTargetMachine &tm);
41
42  const R600RegisterInfo &getRegisterInfo() const;
43  virtual void copyPhysReg(MachineBasicBlock &MBB,
44                           MachineBasicBlock::iterator MI, DebugLoc DL,
45                           unsigned DestReg, unsigned SrcReg,
46                           bool KillSrc) const;
47
48  bool isTrig(const MachineInstr &MI) const;
49  bool isPlaceHolderOpcode(unsigned opcode) const;
50  bool isTexOp(unsigned opcode) const;
51  bool isReductionOp(unsigned opcode) const;
52  bool isCubeOp(unsigned opcode) const;
53  bool isFCOp(unsigned opcode) const;
54
55  /// isVector - Vector instructions are instructions that must fill all
56  /// instruction slots within an instruction group.
57  bool isVector(const MachineInstr &MI) const;
58
59  virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
60                                        int64_t Imm) const;
61
62  virtual unsigned getIEQOpcode() const;
63  virtual bool isMov(unsigned Opcode) const;
64
65  DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
66                                           const ScheduleDAG *DAG) const;
67  bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
68                     SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
69
70  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
71
72  unsigned RemoveBranch(MachineBasicBlock &MBB) const;
73
74  bool isPredicated(const MachineInstr *MI) const;
75
76  bool isPredicable(MachineInstr *MI) const;
77};
78
79} // End llvm namespace
80
81namespace R600_InstFlag {
82	enum TIF {
83		TRANS_ONLY = (1 << 0),
84		TEX = (1 << 1),
85		REDUCTION = (1 << 2),
86		FC = (1 << 3),
87		TRIG = (1 << 4),
88		OP3 = (1 << 5),
89		VECTOR = (1 << 6)
90	};
91}
92
93#endif // R600INSTRINFO_H_
94