R600InstrInfo.h revision a614979286f8d329af318c1e9fb067e17cab4315 
1//===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Interface definition for R600InstrInfo
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef R600INSTRUCTIONINFO_H_
15#define R600INSTRUCTIONINFO_H_
16
17#include "AMDIL.h"
18#include "AMDGPUInstrInfo.h"
19#include "R600RegisterInfo.h"
20
21#include <map>
22
23namespace llvm {
24
25  class AMDGPUTargetMachine;
26  class DFAPacketizer;
27  class ScheduleDAG;
28  class MachineFunction;
29  class MachineInstr;
30  class MachineInstrBuilder;
31
32  class R600InstrInfo : public AMDGPUInstrInfo {
33  private:
34  const R600RegisterInfo RI;
35  AMDGPUTargetMachine &TM;
36
37  int getBranchInstr(const MachineOperand &op) const;
38
39  public:
40  explicit R600InstrInfo(AMDGPUTargetMachine &tm);
41
42  const R600RegisterInfo &getRegisterInfo() const;
43  virtual void copyPhysReg(MachineBasicBlock &MBB,
44                           MachineBasicBlock::iterator MI, DebugLoc DL,
45                           unsigned DestReg, unsigned SrcReg,
46                           bool KillSrc) const;
47
48  bool isTrig(const MachineInstr &MI) const;
49  bool isPlaceHolderOpcode(unsigned opcode) const;
50  bool isTexOp(unsigned opcode) const;
51  bool isReductionOp(unsigned opcode) const;
52  bool isCubeOp(unsigned opcode) const;
53  bool isFCOp(unsigned opcode) const;
54
55  /// isVector - Vector instructions are instructions that must fill all
56  /// instruction slots within an instruction group.
57  bool isVector(const MachineInstr &MI) const;
58
59  virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
60                                        int64_t Imm) const;
61
62  virtual unsigned getIEQOpcode() const;
63  virtual bool isMov(unsigned Opcode) const;
64
65  DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
66                                           const ScheduleDAG *DAG) const;
67
68  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
69
70  bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
71                     SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
72
73  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
74
75  unsigned RemoveBranch(MachineBasicBlock &MBB) const;
76
77  bool isPredicated(const MachineInstr *MI) const;
78
79  bool isPredicable(MachineInstr *MI) const;
80
81  bool
82   isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
83                             const BranchProbability &Probability) const;
84
85  bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
86                           unsigned ExtraPredCycles,
87                           const BranchProbability &Probability) const ;
88
89  bool
90   isProfitableToIfCvt(MachineBasicBlock &TMBB,
91                       unsigned NumTCycles, unsigned ExtraTCycles,
92                       MachineBasicBlock &FMBB,
93                       unsigned NumFCycles, unsigned ExtraFCycles,
94                       const BranchProbability &Probability) const;
95
96  bool DefinesPredicate(MachineInstr *MI,
97                                  std::vector<MachineOperand> &Pred) const;
98
99  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
100                         const SmallVectorImpl<MachineOperand> &Pred2) const;
101
102  bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
103                                          MachineBasicBlock &FMBB) const;
104
105  bool PredicateInstruction(MachineInstr *MI,
106                        const SmallVectorImpl<MachineOperand> &Pred) const;
107
108  int getInstrLatency(const InstrItineraryData *ItinData,
109                              const MachineInstr *MI,
110                              unsigned *PredCost = 0) const;
111
112  virtual int getInstrLatency(const InstrItineraryData *ItinData,
113                              SDNode *Node) const { return 1;}
114};
115
116} // End llvm namespace
117
118namespace R600_InstFlag {
119	enum TIF {
120		TRANS_ONLY = (1 << 0),
121		TEX = (1 << 1),
122		REDUCTION = (1 << 2),
123		FC = (1 << 3),
124		TRIG = (1 << 4),
125		OP3 = (1 << 5),
126		VECTOR = (1 << 6)
127	};
128}
129
130#endif // R600INSTRINFO_H_
131