R600Instructions.td revision 1cb07bd3b8abd5e52e9dbd80bb1666058545387e
1//===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// R600 Tablegen instruction definitions 11// 12//===----------------------------------------------------------------------===// 13 14include "R600Intrinsics.td" 15 16class InstR600 <bits<32> inst, dag outs, dag ins, string asm, list<dag> pattern, 17 InstrItinClass itin> 18 : AMDGPUInst <outs, ins, asm, pattern> { 19 20 field bits<32> Inst; 21 bit Trig = 0; 22 bit Op3 = 0; 23 bit isVector = 0; 24 25 let Inst = inst; 26 let Namespace = "AMDGPU"; 27 let OutOperandList = outs; 28 let InOperandList = ins; 29 let AsmString = asm; 30 let Pattern = pattern; 31 let Itinerary = itin; 32 33 let TSFlags{4} = Trig; 34 let TSFlags{5} = Op3; 35 36 // Vector instructions are instructions that must fill all slots in an 37 // instruction group 38 let TSFlags{6} = isVector; 39} 40 41class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> : 42 AMDGPUInst <outs, ins, asm, pattern> 43{ 44 field bits<64> Inst; 45 46 let Namespace = "AMDGPU"; 47} 48 49def MEMxi : Operand<iPTR> { 50 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index); 51} 52 53def MEMrr : Operand<iPTR> { 54 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index); 55} 56 57def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>; 58def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>; 59def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>; 60 61class R600_ALU { 62 63 bits<7> DST_GPR = 0; 64 bits<9> SRC0_SEL = 0; 65 bits<1> SRC0_NEG = 0; 66 bits<9> SRC1_SEL = 0; 67 bits<1> SRC1_NEG = 0; 68 bits<1> CLAMP = 0; 69 70} 71 72def R600_Pred : PredicateOperand<i32, (ops R600_Predicate), 73 (ops PRED_SEL_OFF)>; 74 75 76class R600_1OP <bits<32> inst, string opName, list<dag> pattern, 77 InstrItinClass itin = AnyALU> : 78 InstR600 <inst, 79 (outs R600_Reg32:$dst), 80 (ins R600_Reg32:$src, R600_Pred:$p, variable_ops), 81 !strconcat(opName, " $dst, $src ($p)"), 82 pattern, 83 itin 84 >; 85 86class R600_2OP <bits<32> inst, string opName, list<dag> pattern, 87 InstrItinClass itin = AnyALU> : 88 InstR600 <inst, 89 (outs R600_Reg32:$dst), 90 (ins R600_Reg32:$src0, R600_Reg32:$src1,R600_Pred:$p, variable_ops), 91 !strconcat(opName, " $dst, $src0, $src1"), 92 pattern, 93 itin 94 >; 95 96class R600_3OP <bits<32> inst, string opName, list<dag> pattern, 97 InstrItinClass itin = AnyALU> : 98 InstR600 <inst, 99 (outs R600_Reg32:$dst), 100 (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2,R600_Pred:$p, variable_ops), 101 !strconcat(opName, " $dst, $src0, $src1, $src2"), 102 pattern, 103 itin>{ 104 105 let Op3 = 1; 106 } 107 108 109 110def PRED_X : AMDGPUInst <(outs R600_Predicate_Bit:$dst), 111 (ins R600_Reg32:$src0, i32imm:$src1), 112 "PRED $dst, $src0, $src1", 113 []> 114{ 115 let DisableEncoding = "$src0"; 116 field bits<32> Inst; 117 bits<32> src1; 118 119 let Inst = src1; 120} 121 122 123 124let isTerminator = 1, isBranch = 1 in { 125def JUMP : InstR600 <0x10, 126 (outs), 127 (ins brtarget:$target, R600_Pred:$p), 128 "JUMP $target ($p)", 129 [], AnyALU 130 >; 131} 132 133class R600_REDUCTION <bits<32> inst, dag ins, string asm, list<dag> pattern, 134 InstrItinClass itin = VecALU> : 135 InstR600 <inst, 136 (outs R600_Reg32:$dst), 137 ins, 138 asm, 139 pattern, 140 itin 141 142 >; 143 144class R600_TEX <bits<32> inst, string opName, list<dag> pattern, 145 InstrItinClass itin = AnyALU> : 146 InstR600 <inst, 147 (outs R600_Reg128:$dst), 148 (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2), 149 !strconcat(opName, "$dst, $src0, $src1, $src2"), 150 pattern, 151 itin 152 >; 153 154def TEX_SHADOW : PatLeaf< 155 (imm), 156 [{uint32_t TType = (uint32_t)N->getZExtValue(); 157 return (TType >= 6 && TType <= 8) || TType == 11 || TType == 12; 158 }] 159>; 160 161class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs, 162 dag ins, string asm, list<dag> pattern> : 163 InstR600ISA <outs, ins, asm, pattern> 164{ 165 bits<7> RW_GPR; 166 bits<7> INDEX_GPR; 167 168 bits<2> RIM; 169 bits<2> TYPE; 170 bits<1> RW_REL; 171 bits<2> ELEM_SIZE; 172 173 bits<12> ARRAY_SIZE; 174 bits<4> COMP_MASK; 175 bits<4> BURST_COUNT; 176 bits<1> VPM; 177 bits<1> EOP; 178 bits<1> MARK; 179 bits<1> BARRIER; 180 181 /* CF_ALLOC_EXPORT_WORD0_RAT */ 182 let Inst{3-0} = rat_id; 183 let Inst{9-4} = rat_inst; 184 let Inst{10} = 0; /* Reserved */ 185 let Inst{12-11} = RIM; 186 let Inst{14-13} = TYPE; 187 let Inst{21-15} = RW_GPR; 188 let Inst{22} = RW_REL; 189 let Inst{29-23} = INDEX_GPR; 190 let Inst{31-30} = ELEM_SIZE; 191 192 /* CF_ALLOC_EXPORT_WORD1_BUF */ 193 let Inst{43-32} = ARRAY_SIZE; 194 let Inst{47-44} = COMP_MASK; 195 let Inst{51-48} = BURST_COUNT; 196 let Inst{52} = VPM; 197 let Inst{53} = EOP; 198 let Inst{61-54} = cf_inst; 199 let Inst{62} = MARK; 200 let Inst{63} = BARRIER; 201} 202 203/* 204def store_global : PatFrag<(ops node:$value, node:$ptr), 205 (store node:$value, node:$ptr), 206 [{ 207 const Value *Src; 208 const PointerType *Type; 209 if ((src = cast<StoreSDNode>(N)->getSrcValue() && 210 PT = dyn_cast<PointerType>(Src->getType()))) { 211 return PT->getAddressSpace() == 1; 212 } 213 return false; 214 }]>; 215 216*/ 217 218def load_param : PatFrag<(ops node:$ptr), 219 (load node:$ptr), 220 [{ 221 const Value *Src = cast<LoadSDNode>(N)->getSrcValue(); 222 if (Src) { 223 PointerType * PT = dyn_cast<PointerType>(Src->getType()); 224 return PT && PT->getAddressSpace() == AMDGPUAS::PARAM_I_ADDRESS; 225 } 226 return false; 227 }]>; 228 229//class EG_CF <bits<32> inst, string asm> : 230// InstR600 <inst, (outs), (ins), asm, []>; 231 232/* XXX: We will use this when we emit the real ISA. 233 bits<24> ADDR = 0; 234 bits<3> JTS = 0; 235 236 bits<3> PC = 0; 237 bits<5> CF_CONS = 0; 238 bits<2> COND = 0; 239 bits<6> COUNT = 0; 240 bits<1> VPM = 0; 241 bits<1> EOP = 0; 242 bits<8> CF_INST = 0; 243 bits<1> WQM = 0; 244 bits<1> B = 0; 245 246 let Inst{23-0} = ADDR; 247 let Inst{26-24} = JTS; 248 let Inst{34-32} = PC; 249 let Inst{39-35} = CF_CONST; 250 let Inst{41-40} = COND; 251 let Inst{47-42} = COUNT; 252 let Inst{52} = VPM; 253 let Inst{53} = EOP; 254 let Inst{61-54} = CF_INST; 255 let Inst{62} = WQM; 256 let Inst{63} = B; 257//} 258*/ 259def isR600 : Predicate<"Subtarget.device()" 260 "->getGeneration() == AMDGPUDeviceInfo::HD4XXX">; 261def isR700 : Predicate<"Subtarget.device()" 262 "->getGeneration() == AMDGPUDeviceInfo::HD4XXX &&" 263 "Subtarget.device()->getDeviceFlag()" 264 ">= OCL_DEVICE_RV710">; 265def isEG : Predicate<"Subtarget.device()" 266 "->getGeneration() >= AMDGPUDeviceInfo::HD5XXX && " 267 "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">; 268def isCayman : Predicate<"Subtarget.device()" 269 "->getDeviceFlag() == OCL_DEVICE_CAYMAN">; 270def isEGorCayman : Predicate<"Subtarget.device()" 271 "->getGeneration() == AMDGPUDeviceInfo::HD5XXX" 272 "|| Subtarget.device()->getGeneration() ==" 273 "AMDGPUDeviceInfo::HD6XXX">; 274 275def isR600toCayman : Predicate< 276 "Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX">; 277 278 279let Predicates = [isR600toCayman] in { 280 281/* ------------------------------------------- */ 282/* Common Instructions R600, R700, Evergreen, Cayman */ 283/* ------------------------------------------- */ 284def ADD : R600_2OP < 285 0x0, "ADD", 286 [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))] 287>; 288 289// Non-IEEE MUL: 0 * anything = 0 290def MUL : R600_2OP < 291 0x1, "MUL NON-IEEE", 292 [(set R600_Reg32:$dst, (int_AMDGPU_mul R600_Reg32:$src0, R600_Reg32:$src1))] 293>; 294 295def MUL_IEEE : R600_2OP < 296 0x2, "MUL_IEEE", 297 [(set R600_Reg32:$dst, (fmul R600_Reg32:$src0, R600_Reg32:$src1))] 298>; 299 300def MAX : R600_2OP < 301 0x3, "MAX", 302 [(set R600_Reg32:$dst, (AMDGPUfmax R600_Reg32:$src0, R600_Reg32:$src1))] 303>; 304 305def MIN : R600_2OP < 306 0x4, "MIN", 307 [(set R600_Reg32:$dst, (AMDGPUfmin R600_Reg32:$src0, R600_Reg32:$src1))] 308>; 309 310/* For the SET* instructions there is a naming conflict in TargetSelectionDAG.td, 311 * so some of the instruction names don't match the asm string. 312 * XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics. 313 */ 314 315def SETE : R600_2OP < 316 0x08, "SETE", 317 [(set R600_Reg32:$dst, 318 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, 319 COND_EQ))] 320>; 321 322def SGT : R600_2OP < 323 0x09, "SETGT", 324 [(set R600_Reg32:$dst, 325 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, 326 COND_GT))] 327>; 328 329def SGE : R600_2OP < 330 0xA, "SETGE", 331 [(set R600_Reg32:$dst, 332 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, 333 COND_GE))] 334>; 335 336def SNE : R600_2OP < 337 0xB, "SETNE", 338 [(set R600_Reg32:$dst, 339 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, 340 COND_NE))] 341>; 342 343def FRACT : R600_1OP < 344 0x10, "FRACT", 345 [(set R600_Reg32:$dst, (AMDGPUfract R600_Reg32:$src))] 346>; 347 348def TRUNC : R600_1OP < 349 0x11, "TRUNC", 350 [(set R600_Reg32:$dst, (int_AMDGPU_trunc R600_Reg32:$src))] 351>; 352 353def CEIL : R600_1OP < 354 0x12, "CEIL", 355 [(set R600_Reg32:$dst, (fceil R600_Reg32:$src))] 356>; 357 358def RNDNE : R600_1OP < 359 0x13, "RNDNE", 360 [(set R600_Reg32:$dst, (frint R600_Reg32:$src))] 361>; 362 363def FLOOR : R600_1OP < 364 0x14, "FLOOR", 365 [(set R600_Reg32:$dst, (int_AMDGPU_floor R600_Reg32:$src))] 366>; 367 368def MOV : R600_1OP <0x19, "MOV", []>; 369 370class MOV_IMM <ValueType vt, Operand immType> : InstR600 <0x19, 371 (outs R600_Reg32:$dst), 372 (ins R600_Reg32:$alu_literal, R600_Pred:$p, immType:$imm), 373 "MOV_IMM $dst, $imm", 374 [], AnyALU 375>; 376 377def MOV_IMM_I32 : MOV_IMM<i32, i32imm>; 378def : Pat < 379 (imm:$val), 380 (MOV_IMM_I32 (i32 ALU_LITERAL_X), imm:$val) 381>; 382 383def MOV_IMM_F32 : MOV_IMM<f32, f32imm>; 384def : Pat < 385 (fpimm:$val), 386 (MOV_IMM_F32 (i32 ALU_LITERAL_X), fpimm:$val) 387>; 388 389def KILLGT : R600_2OP < 390 0x2D, "KILLGT", 391 [] 392>; 393 394def AND_INT : R600_2OP < 395 0x30, "AND_INT", 396 [(set R600_Reg32:$dst, (and R600_Reg32:$src0, R600_Reg32:$src1))] 397>; 398 399def OR_INT : R600_2OP < 400 0x31, "OR_INT", 401 [(set R600_Reg32:$dst, (or R600_Reg32:$src0, R600_Reg32:$src1))] 402>; 403 404def XOR_INT : R600_2OP < 405 0x32, "XOR_INT", 406 [(set R600_Reg32:$dst, (xor R600_Reg32:$src0, R600_Reg32:$src1))] 407>; 408 409def NOT_INT : R600_1OP < 410 0x33, "NOT_INT", 411 [(set R600_Reg32:$dst, (not R600_Reg32:$src))] 412>; 413 414def ADD_INT : R600_2OP < 415 0x34, "ADD_INT", 416 [(set R600_Reg32:$dst, (add R600_Reg32:$src0, R600_Reg32:$src1))] 417>; 418 419def SUB_INT : R600_2OP < 420 0x35, "SUB_INT", 421 [(set R600_Reg32:$dst, (sub R600_Reg32:$src0, R600_Reg32:$src1))] 422>; 423 424def MAX_INT : R600_2OP < 425 0x36, "MAX_INT", 426 [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]>; 427 428def MIN_INT : R600_2OP < 429 0x37, "MIN_INT", 430 [(set R600_Reg32:$dst, (AMDGPUsmin R600_Reg32:$src0, R600_Reg32:$src1))]>; 431 432def MAX_UINT : R600_2OP < 433 0x38, "MAX_UINT", 434 [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))] 435>; 436 437def MIN_UINT : R600_2OP < 438 0x39, "MIN_UINT", 439 [(set R600_Reg32:$dst, (AMDGPUumin R600_Reg32:$src0, R600_Reg32:$src1))] 440>; 441 442def SETE_INT : R600_2OP < 443 0x3A, "SETE_INT", 444 [(set (i32 R600_Reg32:$dst), 445 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))] 446>; 447 448def SETGT_INT : R600_2OP < 449 0x3B, "SGT_INT", 450 [(set (i32 R600_Reg32:$dst), 451 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGT))] 452>; 453 454def SETGE_INT : R600_2OP < 455 0x3C, "SETGE_INT", 456 [(set (i32 R600_Reg32:$dst), 457 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))] 458>; 459 460def SETNE_INT : R600_2OP < 461 0x3D, "SETNE_INT", 462 [(set (i32 R600_Reg32:$dst), 463 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))] 464>; 465 466def SETGT_UINT : R600_2OP < 467 0x3E, "SETGT_UINT", 468 [(set (i32 R600_Reg32:$dst), 469 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))] 470>; 471 472def SETGE_UINT : R600_2OP < 473 0x3F, "SETGE_UINT", 474 [(set (i32 R600_Reg32:$dst), 475 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))] 476>; 477 478def CNDE_INT : R600_3OP < 479 0x1C, "CNDE_INT", 480 [(set (i32 R600_Reg32:$dst), 481 (select R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))] 482>; 483 484/* Texture instructions */ 485 486 487def TEX_LD : R600_TEX < 488 0x03, "TEX_LD", 489 [(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2, imm:$src3, imm:$src4, imm:$src5))] 490> { 491let AsmString = "TEX_LD $dst, $src0, $src1, $src2, $src3, $src4, $src5"; 492let InOperandList = (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5); 493} 494 495def TEX_GET_TEXTURE_RESINFO : R600_TEX < 496 0x04, "TEX_GET_TEXTURE_RESINFO", 497 [(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$src1, imm:$src2))] 498>; 499 500def TEX_GET_GRADIENTS_H : R600_TEX < 501 0x07, "TEX_GET_GRADIENTS_H", 502 [(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$src1, imm:$src2))] 503>; 504 505def TEX_GET_GRADIENTS_V : R600_TEX < 506 0x08, "TEX_GET_GRADIENTS_V", 507 [(set R600_Reg128:$dst, (int_AMDGPU_ddy R600_Reg128:$src0, imm:$src1, imm:$src2))] 508>; 509 510def TEX_SET_GRADIENTS_H : R600_TEX < 511 0x0B, "TEX_SET_GRADIENTS_H", 512 [] 513>; 514 515def TEX_SET_GRADIENTS_V : R600_TEX < 516 0x0C, "TEX_SET_GRADIENTS_V", 517 [] 518>; 519 520def TEX_SAMPLE : R600_TEX < 521 0x10, "TEX_SAMPLE", 522 [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, imm:$src2))] 523>; 524 525def TEX_SAMPLE_C : R600_TEX < 526 0x18, "TEX_SAMPLE_C", 527 [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))] 528>; 529 530def TEX_SAMPLE_L : R600_TEX < 531 0x11, "TEX_SAMPLE_L", 532 [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, imm:$src2))] 533>; 534 535def TEX_SAMPLE_C_L : R600_TEX < 536 0x19, "TEX_SAMPLE_C_L", 537 [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))] 538>; 539 540def TEX_SAMPLE_LB : R600_TEX < 541 0x12, "TEX_SAMPLE_LB", 542 [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, imm:$src2))] 543>; 544 545def TEX_SAMPLE_C_LB : R600_TEX < 546 0x1A, "TEX_SAMPLE_C_LB", 547 [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))] 548>; 549 550def TEX_SAMPLE_G : R600_TEX < 551 0x14, "TEX_SAMPLE_G", 552 [] 553>; 554 555def TEX_SAMPLE_C_G : R600_TEX < 556 0x1C, "TEX_SAMPLE_C_G", 557 [] 558>; 559 560/* Helper classes for common instructions */ 561 562class MUL_LIT_Common <bits<32> inst> : R600_3OP < 563 inst, "MUL_LIT", 564 [] 565>; 566 567class MULADD_Common <bits<32> inst> : R600_3OP < 568 inst, "MULADD", 569 [(set (f32 R600_Reg32:$dst), 570 (IL_mad R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))] 571>; 572 573class CNDE_Common <bits<32> inst> : R600_3OP < 574 inst, "CNDE", 575 [(set (f32 R600_Reg32:$dst), 576 (select (i32 (fp_to_sint (fneg R600_Reg32:$src0))), (f32 R600_Reg32:$src2), (f32 R600_Reg32:$src1)))] 577>; 578 579class CNDGT_Common <bits<32> inst> : R600_3OP < 580 inst, "CNDGT", 581 [] 582>; 583 584class CNDGE_Common <bits<32> inst> : R600_3OP < 585 inst, "CNDGE", 586 [(set R600_Reg32:$dst, (int_AMDGPU_cndlt R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))] 587>; 588 589class DOT4_Common <bits<32> inst> : R600_REDUCTION < 590 inst, 591 (ins R600_Reg128:$src0, R600_Reg128:$src1), 592 "DOT4 $dst $src0, $src1", 593 [(set R600_Reg32:$dst, (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1))] 594>; 595 596multiclass CUBE_Common <bits<32> inst> { 597 598 def _pseudo : InstR600 < 599 inst, 600 (outs R600_Reg128:$dst), 601 (ins R600_Reg128:$src), 602 "CUBE $dst $src", 603 [(set R600_Reg128:$dst, (int_AMDGPU_cube R600_Reg128:$src))], 604 VecALU 605 >; 606 607 def _real : InstR600 < 608 inst, 609 (outs R600_Reg32:$dst), 610 (ins R600_Reg32:$src0, R600_Reg32:$src1), 611 "CUBE $dst, $src0, $src1", 612 [], VecALU 613 >; 614} 615 616class EXP_IEEE_Common <bits<32> inst> : R600_1OP < 617 inst, "EXP_IEEE", 618 [(set R600_Reg32:$dst, (fexp2 R600_Reg32:$src))] 619>; 620 621class FLT_TO_INT_Common <bits<32> inst> : R600_1OP < 622 inst, "FLT_TO_INT", 623 [(set R600_Reg32:$dst, (fp_to_sint R600_Reg32:$src))] 624>; 625 626class INT_TO_FLT_Common <bits<32> inst> : R600_1OP < 627 inst, "INT_TO_FLT", 628 [(set R600_Reg32:$dst, (sint_to_fp R600_Reg32:$src))] 629>; 630 631class FLT_TO_UINT_Common <bits<32> inst> : R600_1OP < 632 inst, "FLT_TO_UINT", 633 [(set R600_Reg32:$dst, (fp_to_uint R600_Reg32:$src))] 634>; 635 636class UINT_TO_FLT_Common <bits<32> inst> : R600_1OP < 637 inst, "UINT_TO_FLT", 638 [(set R600_Reg32:$dst, (uint_to_fp R600_Reg32:$src))] 639>; 640 641class LOG_CLAMPED_Common <bits<32> inst> : R600_1OP < 642 inst, "LOG_CLAMPED", 643 [] 644>; 645 646class LOG_IEEE_Common <bits<32> inst> : R600_1OP < 647 inst, "LOG_IEEE", 648 [(set R600_Reg32:$dst, (int_AMDIL_log R600_Reg32:$src))] 649>; 650 651class LSHL_Common <bits<32> inst> : R600_2OP < 652 inst, "LSHL $dst, $src0, $src1", 653 [(set R600_Reg32:$dst, (shl R600_Reg32:$src0, R600_Reg32:$src1))] 654>; 655 656class LSHR_Common <bits<32> inst> : R600_2OP < 657 inst, "LSHR $dst, $src0, $src1", 658 [(set R600_Reg32:$dst, (srl R600_Reg32:$src0, R600_Reg32:$src1))] 659>; 660 661class ASHR_Common <bits<32> inst> : R600_2OP < 662 inst, "ASHR $dst, $src0, $src1", 663 [(set R600_Reg32:$dst, (sra R600_Reg32:$src0, R600_Reg32:$src1))] 664>; 665 666class MULHI_INT_Common <bits<32> inst> : R600_2OP < 667 inst, "MULHI_INT $dst, $src0, $src1", 668 [(set R600_Reg32:$dst, (mulhs R600_Reg32:$src0, R600_Reg32:$src1))] 669>; 670 671class MULHI_UINT_Common <bits<32> inst> : R600_2OP < 672 inst, "MULHI $dst, $src0, $src1", 673 [(set R600_Reg32:$dst, (mulhu R600_Reg32:$src0, R600_Reg32:$src1))] 674>; 675 676class MULLO_INT_Common <bits<32> inst> : R600_2OP < 677 inst, "MULLO_INT $dst, $src0, $src1", 678 [(set R600_Reg32:$dst, (mul R600_Reg32:$src0, R600_Reg32:$src1))] 679>; 680 681class MULLO_UINT_Common <bits<32> inst> : R600_2OP < 682 inst, "MULLO_UINT $dst, $src0, $src1", 683 [] 684>; 685 686class RECIP_CLAMPED_Common <bits<32> inst> : R600_1OP < 687 inst, "RECIP_CLAMPED", 688 [] 689>; 690 691class RECIP_IEEE_Common <bits<32> inst> : R600_1OP < 692 inst, "RECIP_IEEE", 693 [(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))] 694>; 695 696class RECIP_UINT_Common <bits<32> inst> : R600_1OP < 697 inst, "RECIP_INT $dst, $src", 698 [(set R600_Reg32:$dst, (AMDGPUurecip R600_Reg32:$src))] 699>; 700 701class RECIPSQRT_CLAMPED_Common <bits<32> inst> : R600_1OP < 702 inst, "RECIPSQRT_CLAMPED", 703 [(set R600_Reg32:$dst, (int_AMDGPU_rsq R600_Reg32:$src))] 704>; 705 706class RECIPSQRT_IEEE_Common <bits<32> inst> : R600_1OP < 707 inst, "RECIPSQRT_IEEE", 708 [] 709>; 710 711class SIN_Common <bits<32> inst> : R600_1OP < 712 inst, "SIN", []>{ 713 let Trig = 1; 714} 715 716class COS_Common <bits<32> inst> : R600_1OP < 717 inst, "COS", []> { 718 let Trig = 1; 719} 720 721/* Helper patterns for complex intrinsics */ 722/* -------------------------------------- */ 723 724class DIV_Common <InstR600 recip_ieee> : Pat< 725 (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1), 726 (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1)) 727>; 728 729class SSG_Common <InstR600 cndgt, InstR600 cndge> : Pat < 730 (int_AMDGPU_ssg R600_Reg32:$src), 731 (cndgt R600_Reg32:$src, (f32 ONE), (cndge R600_Reg32:$src, (f32 ZERO), (f32 NEG_ONE))) 732>; 733 734class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> : Pat < 735 (int_TGSI_lit_z R600_Reg32:$src_x, R600_Reg32:$src_y, R600_Reg32:$src_w), 736 (exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x)) 737>; 738 739/* ---------------------- */ 740/* R600 / R700 Only Instructions */ 741/* ---------------------- */ 742 743let Predicates = [isR600] in { 744 745 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>; 746 def MULADD_r600 : MULADD_Common<0x10>; 747 def CNDE_r600 : CNDE_Common<0x18>; 748 def CNDGT_r600 : CNDGT_Common<0x19>; 749 def CNDGE_r600 : CNDGE_Common<0x1A>; 750 def DOT4_r600 : DOT4_Common<0x50>; 751 defm CUBE_r600 : CUBE_Common<0x52>; 752 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>; 753 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>; 754 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>; 755 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>; 756 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>; 757 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>; 758 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>; 759 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>; 760 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>; 761 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>; 762 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>; 763 def SIN_r600 : SIN_Common<0x6E>; 764 def COS_r600 : COS_Common<0x6F>; 765 def ASHR_r600 : ASHR_Common<0x70>; 766 def LSHR_r600 : LSHR_Common<0x71>; 767 def LSHL_r600 : LSHL_Common<0x72>; 768 def MULLO_INT_r600 : MULLO_INT_Common<0x73>; 769 def MULHI_INT_r600 : MULHI_INT_Common<0x74>; 770 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>; 771 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>; 772 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>; 773 774 def DIV_r600 : DIV_Common<RECIP_IEEE_r600>; 775 def POW_r600 : POW_Common<LOG_IEEE_r600, EXP_IEEE_r600, MUL, GPRF32>; 776 def SSG_r600 : SSG_Common<CNDGT_r600, CNDGE_r600>; 777 def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>; 778 779} 780 781// Helper pattern for normalizing inputs to triginomic instructions for R700+ 782// cards. 783class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat< 784 (intr R600_Reg32:$src), 785 (trig (MUL (MOV_IMM_I32 (i32 ALU_LITERAL_X), CONST.TWO_PI_INV), R600_Reg32:$src)) 786>; 787 788//===----------------------------------------------------------------------===// 789// R700 Only instructions 790//===----------------------------------------------------------------------===// 791 792let Predicates = [isR700] in { 793 def SIN_r700 : SIN_Common<0x6E>; 794 def COS_r700 : COS_Common<0x6F>; 795 796 // R700 normalizes inputs to SIN/COS the same as EG 797 def : TRIG_eg <SIN_r700, int_AMDGPU_sin>; 798 def : TRIG_eg <COS_r700, int_AMDGPU_cos>; 799} 800 801//===----------------------------------------------------------------------===// 802// Evergreen Only instructions 803//===----------------------------------------------------------------------===// 804 805let Predicates = [isEG] in { 806 807def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>; 808 809def MULLO_INT_eg : MULLO_INT_Common<0x8F>; 810def MULHI_INT_eg : MULHI_INT_Common<0x90>; 811def MULLO_UINT_eg : MULLO_UINT_Common<0x91>; 812def MULHI_UINT_eg : MULHI_UINT_Common<0x92>; 813def RECIP_UINT_eg : RECIP_UINT_Common<0x94>; 814 815} // End Predicates = [isEG] 816 817/* ------------------------------- */ 818/* Evergreen / Cayman Instructions */ 819/* ------------------------------- */ 820 821let Predicates = [isEGorCayman] in { 822 823 // BFE_UINT - bit_extract, an optimization for mask and shift 824 // Src0 = Input 825 // Src1 = Offset 826 // Src2 = Width 827 // 828 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width) 829 // 830 // Example Usage: 831 // (Offset, Width) 832 // 833 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0 834 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8 835 // (16,8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16 836 // (24,8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24 837 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT", 838 [(set R600_Reg32:$dst, (int_AMDIL_bit_extract_u32 R600_Reg32:$src0, 839 R600_Reg32:$src1, 840 R600_Reg32:$src2))], 841 VecALU 842 >; 843 844 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", 845 [(set R600_Reg32:$dst, (AMDGPUbitalign R600_Reg32:$src0, R600_Reg32:$src1, 846 R600_Reg32:$src2))], 847 VecALU 848 >; 849 850 def MULADD_eg : MULADD_Common<0x14>; 851 def ASHR_eg : ASHR_Common<0x15>; 852 def LSHR_eg : LSHR_Common<0x16>; 853 def LSHL_eg : LSHL_Common<0x17>; 854 def CNDE_eg : CNDE_Common<0x19>; 855 def CNDGT_eg : CNDGT_Common<0x1A>; 856 def CNDGE_eg : CNDGE_Common<0x1B>; 857 def MUL_LIT_eg : MUL_LIT_Common<0x1F>; 858 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>; 859 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>; 860 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>; 861 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>; 862 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>; 863 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>; 864 def SIN_eg : SIN_Common<0x8D>; 865 def COS_eg : COS_Common<0x8E>; 866 def DOT4_eg : DOT4_Common<0xBE>; 867 defm CUBE_eg : CUBE_Common<0xC0>; 868 869 def DIV_eg : DIV_Common<RECIP_IEEE_eg>; 870 def POW_eg : POW_Common<LOG_IEEE_eg, EXP_IEEE_eg, MUL, GPRF32>; 871 def SSG_eg : SSG_Common<CNDGT_eg, CNDGE_eg>; 872 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>; 873 874 def : TRIG_eg <SIN_eg, int_AMDGPU_sin>; 875 def : TRIG_eg <COS_eg, int_AMDGPU_cos>; 876 877 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> { 878 let Pattern = []; 879 } 880 881 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>; 882 883 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> { 884 let Pattern = []; 885 } 886 887 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>; 888 889 def : Pat<(fp_to_sint R600_Reg32:$src), 890 (FLT_TO_INT_eg (TRUNC R600_Reg32:$src))>; 891 892 def : Pat<(fp_to_uint R600_Reg32:$src), 893 (FLT_TO_UINT_eg (TRUNC R600_Reg32:$src))>; 894 895//===----------------------------------------------------------------------===// 896// Memory read/write instructions 897//===----------------------------------------------------------------------===// 898 899let usesCustomInserter = 1 in { 900 901def RAT_WRITE_CACHELESS_eg : EG_CF_RAT <0x57, 0x2, 0, (outs), 902 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr), 903 "RAT_WRITE_CACHELESS_eg $rw_gpr, $index_gpr", 904 [(global_store (i32 R600_TReg32_X:$rw_gpr), R600_TReg32_X:$index_gpr)]> 905{ 906 let RIM = 0; 907 /* XXX: Have a separate instruction for non-indexed writes. */ 908 let TYPE = 1; 909 let RW_REL = 0; 910 let ELEM_SIZE = 0; 911 912 let ARRAY_SIZE = 0; 913 let COMP_MASK = 1; 914 let BURST_COUNT = 0; 915 let VPM = 0; 916 let EOP = 0; 917 let MARK = 0; 918 let BARRIER = 1; 919} 920 921} // End usesCustomInserter = 1 922 923// Floating point global_store 924def : Pat < 925 (global_store (f32 R600_TReg32_X:$val), R600_TReg32_X:$ptr), 926 (RAT_WRITE_CACHELESS_eg R600_TReg32_X:$val, R600_TReg32_X:$ptr) 927>; 928 929class VTX_READ_eg <bits<8> buffer_id, dag outs, list<dag> pattern> 930 : InstR600ISA <outs, (ins MEMxi:$ptr), "VTX_READ_eg $dst, $ptr", pattern> { 931 932 // Operands 933 bits<7> DST_GPR; 934 bits<7> SRC_GPR; 935 936 // Static fields 937 bits<5> VC_INST = 0; 938 bits<2> FETCH_TYPE = 2; 939 bits<1> FETCH_WHOLE_QUAD = 0; 940 bits<8> BUFFER_ID = buffer_id; 941 bits<1> SRC_REL = 0; 942 // XXX: We can infer this field based on the SRC_GPR. This would allow us 943 // to store vertex addresses in any channel, not just X. 944 bits<2> SRC_SEL_X = 0; 945 bits<6> MEGA_FETCH_COUNT; 946 bits<1> DST_REL = 0; 947 bits<3> DST_SEL_X; 948 bits<3> DST_SEL_Y; 949 bits<3> DST_SEL_Z; 950 bits<3> DST_SEL_W; 951 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL, 952 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored, 953 // however, based on my testing if USE_CONST_FIELDS is set, then all 954 // these fields need to be set to 0. 955 bits<1> USE_CONST_FIELDS = 0; 956 bits<6> DATA_FORMAT; 957 bits<2> NUM_FORMAT_ALL = 1; 958 bits<1> FORMAT_COMP_ALL = 0; 959 bits<1> SRF_MODE_ALL = 0; 960 961 // LLVM can only encode 64-bit instructions, so these fields are manually 962 // encoded in R600CodeEmitter 963 // 964 // bits<16> OFFSET; 965 // bits<2> ENDIAN_SWAP = 0; 966 // bits<1> CONST_BUF_NO_STRIDE = 0; 967 // bits<1> MEGA_FETCH = 0; 968 // bits<1> ALT_CONST = 0; 969 // bits<2> BUFFER_INDEX_MODE = 0; 970 971 // VTX_WORD0 972 let Inst{4-0} = VC_INST; 973 let Inst{6-5} = FETCH_TYPE; 974 let Inst{7} = FETCH_WHOLE_QUAD; 975 let Inst{15-8} = BUFFER_ID; 976 let Inst{22-16} = SRC_GPR; 977 let Inst{23} = SRC_REL; 978 let Inst{25-24} = SRC_SEL_X; 979 let Inst{31-26} = MEGA_FETCH_COUNT; 980 981 // VTX_WORD1_GPR 982 let Inst{38-32} = DST_GPR; 983 let Inst{39} = DST_REL; 984 let Inst{40} = 0; // Reserved 985 let Inst{43-41} = DST_SEL_X; 986 let Inst{46-44} = DST_SEL_Y; 987 let Inst{49-47} = DST_SEL_Z; 988 let Inst{52-50} = DST_SEL_W; 989 let Inst{53} = USE_CONST_FIELDS; 990 let Inst{59-54} = DATA_FORMAT; 991 let Inst{61-60} = NUM_FORMAT_ALL; 992 let Inst{62} = FORMAT_COMP_ALL; 993 let Inst{63} = SRF_MODE_ALL; 994 995 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding 996 // is done in R600CodeEmitter 997 // 998 // Inst{79-64} = OFFSET; 999 // Inst{81-80} = ENDIAN_SWAP; 1000 // Inst{82} = CONST_BUF_NO_STRIDE; 1001 // Inst{83} = MEGA_FETCH; 1002 // Inst{84} = ALT_CONST; 1003 // Inst{86-85} = BUFFER_INDEX_MODE; 1004 // Inst{95-86} = 0; Reserved 1005 1006 // VTX_WORD3 (Padding) 1007 // 1008 // Inst{127-96} = 0; 1009} 1010 1011class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern> 1012 : VTX_READ_eg <buffer_id, (outs R600_TReg32_X:$dst), pattern> { 1013 1014 let MEGA_FETCH_COUNT = 4; 1015 let DST_SEL_X = 0; 1016 let DST_SEL_Y = 7; // Masked 1017 let DST_SEL_Z = 7; // Masked 1018 let DST_SEL_W = 7; // Masked 1019 let DATA_FORMAT = 0xD; // COLOR_32 1020 1021 // This is not really necessary, but there were some GPU hangs that appeared 1022 // to be caused by ALU instructions in the next instruction group that wrote 1023 // to the $ptr registers of the VTX_READ. 1024 // e.g. 1025 // %T3_X<def> = VTX_READ_PARAM_i32_eg %T2_X<kill>, 24 1026 // %T2_X<def> = MOV %ZERO 1027 //Adding this constraint prevents this from happening. 1028 let Constraints = "$ptr.ptr = $dst"; 1029} 1030 1031class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern> 1032 : VTX_READ_eg <buffer_id, (outs R600_Reg128:$dst), pattern> { 1033 1034 let MEGA_FETCH_COUNT = 16; 1035 let DST_SEL_X = 0; 1036 let DST_SEL_Y = 1; 1037 let DST_SEL_Z = 2; 1038 let DST_SEL_W = 3; 1039 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32 1040 1041 // XXX: Need to force VTX_READ_128 instructions to write to the same register 1042 // that holds its buffer address to avoid potential hangs. We can't use 1043 // the same constraint as VTX_READ_32_eg, because the $ptr.ptr and $dst 1044 // registers are different sizes. 1045} 1046 1047//===----------------------------------------------------------------------===// 1048// VTX Read from parameter memory space 1049//===----------------------------------------------------------------------===// 1050 1051class VTX_READ_PARAM_32_eg <ValueType vt> : VTX_READ_32_eg <0, 1052 [(set (vt R600_TReg32_X:$dst), (load_param ADDRVTX_READ:$ptr))] 1053>; 1054 1055def VTX_READ_PARAM_i32_eg : VTX_READ_PARAM_32_eg<i32>; 1056def VTX_READ_PARAM_f32_eg : VTX_READ_PARAM_32_eg<f32>; 1057 1058 1059//===----------------------------------------------------------------------===// 1060// VTX Read from global memory space 1061//===----------------------------------------------------------------------===// 1062 1063// 32-bit reads 1064 1065class VTX_READ_GLOBAL_eg <ValueType vt> : VTX_READ_32_eg <1, 1066 [(set (vt R600_TReg32_X:$dst), (global_load ADDRVTX_READ:$ptr))] 1067>; 1068 1069def VTX_READ_GLOBAL_i32_eg : VTX_READ_GLOBAL_eg<i32>; 1070def VTX_READ_GLOBAL_f32_eg : VTX_READ_GLOBAL_eg<f32>; 1071 1072// 128-bit reads 1073 1074class VTX_READ_GLOBAL_128_eg <ValueType vt> : VTX_READ_128_eg <1, 1075 [(set (vt R600_Reg128:$dst), (global_load ADDRVTX_READ:$ptr))] 1076>; 1077 1078def VTX_READ_GLOBAL_v4i32_eg : VTX_READ_GLOBAL_128_eg<v4i32>; 1079def VTX_READ_GLOBAL_v4f32_eg : VTX_READ_GLOBAL_128_eg<v4f32>; 1080 1081} 1082 1083let Predicates = [isCayman] in { 1084 1085let isVector = 1 in { 1086 1087def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>; 1088 1089def MULLO_INT_cm : MULLO_INT_Common<0x8F>; 1090def MULHI_INT_cm : MULHI_INT_Common<0x90>; 1091def MULLO_UINT_cm : MULLO_UINT_Common<0x91>; 1092def MULHI_UINT_cm : MULHI_UINT_Common<0x92>; 1093 1094} // End isVector = 1 1095 1096// RECIP_UINT emulation for Cayman 1097def : Pat < 1098 (AMDGPUurecip R600_Reg32:$src0), 1099 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg R600_Reg32:$src0)), 1100 (MOV_IMM_I32 (i32 ALU_LITERAL_X), 0x4f800000))) 1101>; 1102 1103} // End isCayman 1104 1105/* Other Instructions */ 1106 1107let isCodeGenOnly = 1 in { 1108/* 1109 def SWIZZLE : AMDGPUShaderInst < 1110 (outs GPRV4F32:$dst), 1111 (ins GPRV4F32:$src0, i32imm:$src1), 1112 "SWIZZLE $dst, $src0, $src1", 1113 [(set GPRV4F32:$dst, (int_AMDGPU_swizzle GPRV4F32:$src0, imm:$src1))] 1114 >; 1115*/ 1116 1117 def LAST : AMDGPUShaderInst < 1118 (outs), 1119 (ins), 1120 "LAST", 1121 [] 1122 >; 1123 1124 def GET_CHAN : AMDGPUShaderInst < 1125 (outs R600_Reg32:$dst), 1126 (ins R600_Reg128:$src0, i32imm:$src1), 1127 "GET_CHAN $dst, $src0, $src1", 1128 [] 1129 >; 1130 1131 def MULLIT : AMDGPUShaderInst < 1132 (outs R600_Reg128:$dst), 1133 (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2), 1134 "MULLIT $dst, $src0, $src1", 1135 [(set R600_Reg128:$dst, (int_AMDGPU_mullit R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))] 1136 >; 1137 1138let usesCustomInserter = 1, isPseudo = 1 in { 1139 1140class R600PreloadInst <string asm, Intrinsic intr> : AMDGPUInst < 1141 (outs R600_TReg32:$dst), 1142 (ins), 1143 asm, 1144 [(set R600_TReg32:$dst, (intr))] 1145>; 1146 1147def R600_LOAD_CONST : AMDGPUShaderInst < 1148 (outs R600_Reg32:$dst), 1149 (ins i32imm:$src0), 1150 "R600_LOAD_CONST $dst, $src0", 1151 [(set R600_Reg32:$dst, (int_AMDGPU_load_const imm:$src0))] 1152>; 1153 1154def RESERVE_REG : AMDGPUShaderInst < 1155 (outs), 1156 (ins i32imm:$src), 1157 "RESERVE_REG $src", 1158 [(int_AMDGPU_reserve_reg imm:$src)] 1159>; 1160 1161def TXD: AMDGPUShaderInst < 1162 (outs R600_Reg128:$dst), 1163 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4), 1164 "TXD $dst, $src0, $src1, $src2, $src3, $src4", 1165 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, imm:$src4))] 1166>; 1167 1168def TXD_SHADOW: AMDGPUShaderInst < 1169 (outs R600_Reg128:$dst), 1170 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4), 1171 "TXD_SHADOW $dst, $src0, $src1, $src2, $src3, $src4", 1172 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, TEX_SHADOW:$src4))] 1173>; 1174 1175} // End usesCustomInserter = 1, isPseudo = 1 1176 1177} // End isCodeGenOnly = 1 1178 1179def CLAMP_R600 : CLAMP <R600_Reg32>; 1180def FABS_R600 : FABS<R600_Reg32>; 1181def FNEG_R600 : FNEG<R600_Reg32>; 1182 1183let usesCustomInserter = 1 in { 1184 1185def MASK_WRITE : AMDGPUShaderInst < 1186 (outs), 1187 (ins R600_Reg32:$src), 1188 "MASK_WRITE $src", 1189 [] 1190>; 1191 1192} // End usesCustomInserter = 1 1193 1194//===----------------------------------------------------------------------===// 1195// ISel Patterns 1196//===----------------------------------------------------------------------===// 1197 1198// KIL Patterns 1199def KILP : Pat < 1200 (int_AMDGPU_kilp), 1201 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO))) 1202>; 1203 1204def KIL : Pat < 1205 (int_AMDGPU_kill R600_Reg32:$src0), 1206 (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0))) 1207>; 1208 1209// SGT Reverse args 1210def : Pat < 1211 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LT), 1212 (SGT R600_Reg32:$src1, R600_Reg32:$src0) 1213>; 1214 1215// SGE Reverse args 1216def : Pat < 1217 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LE), 1218 (SGE R600_Reg32:$src1, R600_Reg32:$src0) 1219>; 1220 1221// SETGT_INT reverse args 1222def : Pat < 1223 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLT), 1224 (SETGT_INT R600_Reg32:$src1, R600_Reg32:$src0) 1225>; 1226 1227// SETGE_INT reverse args 1228def : Pat < 1229 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLE), 1230 (SETGE_INT R600_Reg32:$src1, R600_Reg32:$src0) 1231>; 1232 1233// SETGT_UINT reverse args 1234def : Pat < 1235 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULT), 1236 (SETGT_UINT R600_Reg32:$src1, R600_Reg32:$src0) 1237>; 1238 1239// SETGE_UINT reverse args 1240def : Pat < 1241 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULE), 1242 (SETGE_UINT R600_Reg32:$src0, R600_Reg32:$src1) 1243>; 1244 1245// The next two patterns are special cases for handling 'true if ordered' and 1246// 'true if unordered' conditionals. The assumption here is that the behavior of 1247// SETE and SNE conforms to the Direct3D 10 rules for floating point values 1248// described here: 1249// http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit 1250// We assume that SETE returns false when one of the operands is NAN and 1251// SNE returns true when on of the operands is NAN 1252 1253//SETE - 'true if ordered' 1254def : Pat < 1255 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETO), 1256 (SETE R600_Reg32:$src0, R600_Reg32:$src1) 1257>; 1258 1259//SNE - 'true if unordered' 1260def : Pat < 1261 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETUO), 1262 (SNE R600_Reg32:$src0, R600_Reg32:$src1) 1263>; 1264 1265def : Extract_Element <f32, v4f32, R600_Reg128, 0, sel_x>; 1266def : Extract_Element <f32, v4f32, R600_Reg128, 1, sel_y>; 1267def : Extract_Element <f32, v4f32, R600_Reg128, 2, sel_z>; 1268def : Extract_Element <f32, v4f32, R600_Reg128, 3, sel_w>; 1269 1270def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 4, sel_x>; 1271def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 5, sel_y>; 1272def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 6, sel_z>; 1273def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 7, sel_w>; 1274 1275def : Extract_Element <i32, v4i32, R600_Reg128, 0, sel_x>; 1276def : Extract_Element <i32, v4i32, R600_Reg128, 1, sel_y>; 1277def : Extract_Element <i32, v4i32, R600_Reg128, 2, sel_z>; 1278def : Extract_Element <i32, v4i32, R600_Reg128, 3, sel_w>; 1279 1280def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 4, sel_x>; 1281def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 5, sel_y>; 1282def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 6, sel_z>; 1283def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 7, sel_w>; 1284 1285def : Vector_Build <v4f32, R600_Reg32>; 1286def : Vector_Build <v4i32, R600_Reg32>; 1287 1288// bitconvert patterns 1289 1290def : BitConvert <i32, f32, R600_Reg32>; 1291def : BitConvert <f32, i32, R600_Reg32>; 1292def : BitConvert <v4f32, v4i32, R600_Reg128>; 1293 1294} // End isR600toCayman Predicate 1295