R600Instructions.td revision 8263408a91b6b3beb5af5de6bdc7e5d13197a268
1//===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// R600 Tablegen instruction definitions 11// 12//===----------------------------------------------------------------------===// 13 14include "R600Intrinsics.td" 15 16class InstR600 <bits<32> inst, dag outs, dag ins, string asm, list<dag> pattern, 17 InstrItinClass itin> 18 : AMDGPUInst <outs, ins, asm, pattern> { 19 20 field bits<32> Inst; 21 bit Trig = 0; 22 bit Op3 = 0; 23 bit isVector = 0; 24 25 let Inst = inst; 26 let Namespace = "AMDGPU"; 27 let OutOperandList = outs; 28 let InOperandList = ins; 29 let AsmString = asm; 30 let Pattern = pattern; 31 let Itinerary = itin; 32 33 let TSFlags{4} = Trig; 34 let TSFlags{5} = Op3; 35 36 // Vector instructions are instructions that must fill all slots in an 37 // instruction group 38 let TSFlags{6} = isVector; 39} 40 41class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> : 42 AMDGPUInst <outs, ins, asm, pattern> 43{ 44 field bits<64> Inst; 45 46 let Namespace = "AMDGPU"; 47} 48 49def MEMxi : Operand<iPTR> { 50 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index); 51} 52 53def MEMrr : Operand<iPTR> { 54 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index); 55} 56 57def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>; 58def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>; 59def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>; 60 61class R600_ALU { 62 63 bits<7> DST_GPR = 0; 64 bits<9> SRC0_SEL = 0; 65 bits<1> SRC0_NEG = 0; 66 bits<9> SRC1_SEL = 0; 67 bits<1> SRC1_NEG = 0; 68 bits<1> CLAMP = 0; 69 70} 71 72def R600_Pred : PredicateOperand<i32, (ops R600_Predicate), 73 (ops PRED_SEL_OFF)>; 74 75 76class R600_1OP <bits<32> inst, string opName, list<dag> pattern, 77 InstrItinClass itin = AnyALU> : 78 InstR600 <inst, 79 (outs R600_Reg32:$dst), 80 (ins R600_Reg32:$src, R600_Pred:$p, variable_ops), 81 !strconcat(opName, " $dst, $src ($p)"), 82 pattern, 83 itin 84 >; 85 86class R600_2OP <bits<32> inst, string opName, list<dag> pattern, 87 InstrItinClass itin = AnyALU> : 88 InstR600 <inst, 89 (outs R600_Reg32:$dst), 90 (ins R600_Reg32:$src0, R600_Reg32:$src1,R600_Pred:$p, variable_ops), 91 !strconcat(opName, " $dst, $src0, $src1"), 92 pattern, 93 itin 94 >; 95 96class R600_3OP <bits<32> inst, string opName, list<dag> pattern, 97 InstrItinClass itin = AnyALU> : 98 InstR600 <inst, 99 (outs R600_Reg32:$dst), 100 (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2,R600_Pred:$p, variable_ops), 101 !strconcat(opName, " $dst, $src0, $src1, $src2"), 102 pattern, 103 itin>{ 104 105 let Op3 = 1; 106 } 107 108 109 110def PRED_X : AMDGPUInst <(outs R600_Predicate_Bit:$dst), 111 (ins R600_Reg32:$src0, i32imm:$src1), 112 "PRED $dst, $src0, $src1", 113 []> 114{ 115 let DisableEncoding = "$src0"; 116 field bits<32> Inst; 117 bits<32> src1; 118 119 let Inst = src1; 120} 121 122 123 124class R600_REDUCTION <bits<32> inst, dag ins, string asm, list<dag> pattern, 125 InstrItinClass itin = VecALU> : 126 InstR600 <inst, 127 (outs R600_Reg32:$dst), 128 ins, 129 asm, 130 pattern, 131 itin 132 133 >; 134 135class R600_TEX <bits<32> inst, string opName, list<dag> pattern, 136 InstrItinClass itin = AnyALU> : 137 InstR600 <inst, 138 (outs R600_Reg128:$dst), 139 (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2), 140 !strconcat(opName, "$dst, $src0, $src1, $src2"), 141 pattern, 142 itin 143 >; 144 145def TEX_SHADOW : PatLeaf< 146 (imm), 147 [{uint32_t TType = (uint32_t)N->getZExtValue(); 148 return (TType >= 6 && TType <= 8) || TType == 11 || TType == 12; 149 }] 150>; 151 152class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs, 153 dag ins, string asm, list<dag> pattern> : 154 InstR600ISA <outs, ins, asm, pattern> 155{ 156 bits<7> RW_GPR; 157 bits<7> INDEX_GPR; 158 159 bits<2> RIM; 160 bits<2> TYPE; 161 bits<1> RW_REL; 162 bits<2> ELEM_SIZE; 163 164 bits<12> ARRAY_SIZE; 165 bits<4> COMP_MASK; 166 bits<4> BURST_COUNT; 167 bits<1> VPM; 168 bits<1> EOP; 169 bits<1> MARK; 170 bits<1> BARRIER; 171 172 /* CF_ALLOC_EXPORT_WORD0_RAT */ 173 let Inst{3-0} = rat_id; 174 let Inst{9-4} = rat_inst; 175 let Inst{10} = 0; /* Reserved */ 176 let Inst{12-11} = RIM; 177 let Inst{14-13} = TYPE; 178 let Inst{21-15} = RW_GPR; 179 let Inst{22} = RW_REL; 180 let Inst{29-23} = INDEX_GPR; 181 let Inst{31-30} = ELEM_SIZE; 182 183 /* CF_ALLOC_EXPORT_WORD1_BUF */ 184 let Inst{43-32} = ARRAY_SIZE; 185 let Inst{47-44} = COMP_MASK; 186 let Inst{51-48} = BURST_COUNT; 187 let Inst{52} = VPM; 188 let Inst{53} = EOP; 189 let Inst{61-54} = cf_inst; 190 let Inst{62} = MARK; 191 let Inst{63} = BARRIER; 192} 193 194/* 195def store_global : PatFrag<(ops node:$value, node:$ptr), 196 (store node:$value, node:$ptr), 197 [{ 198 const Value *Src; 199 const PointerType *Type; 200 if ((src = cast<StoreSDNode>(N)->getSrcValue() && 201 PT = dyn_cast<PointerType>(Src->getType()))) { 202 return PT->getAddressSpace() == 1; 203 } 204 return false; 205 }]>; 206 207*/ 208 209def load_param : PatFrag<(ops node:$ptr), 210 (load node:$ptr), 211 [{ 212 const Value *Src = cast<LoadSDNode>(N)->getSrcValue(); 213 if (Src) { 214 PointerType * PT = dyn_cast<PointerType>(Src->getType()); 215 return PT && PT->getAddressSpace() == AMDGPUAS::PARAM_I_ADDRESS; 216 } 217 return false; 218 }]>; 219 220//class EG_CF <bits<32> inst, string asm> : 221// InstR600 <inst, (outs), (ins), asm, []>; 222 223/* XXX: We will use this when we emit the real ISA. 224 bits<24> ADDR = 0; 225 bits<3> JTS = 0; 226 227 bits<3> PC = 0; 228 bits<5> CF_CONS = 0; 229 bits<2> COND = 0; 230 bits<6> COUNT = 0; 231 bits<1> VPM = 0; 232 bits<1> EOP = 0; 233 bits<8> CF_INST = 0; 234 bits<1> WQM = 0; 235 bits<1> B = 0; 236 237 let Inst{23-0} = ADDR; 238 let Inst{26-24} = JTS; 239 let Inst{34-32} = PC; 240 let Inst{39-35} = CF_CONST; 241 let Inst{41-40} = COND; 242 let Inst{47-42} = COUNT; 243 let Inst{52} = VPM; 244 let Inst{53} = EOP; 245 let Inst{61-54} = CF_INST; 246 let Inst{62} = WQM; 247 let Inst{63} = B; 248//} 249*/ 250def isR600 : Predicate<"Subtarget.device()" 251 "->getGeneration() == AMDGPUDeviceInfo::HD4XXX">; 252def isR700 : Predicate<"Subtarget.device()" 253 "->getGeneration() == AMDGPUDeviceInfo::HD4XXX &&" 254 "Subtarget.device()->getDeviceFlag()" 255 ">= OCL_DEVICE_RV710">; 256def isEG : Predicate<"Subtarget.device()" 257 "->getGeneration() >= AMDGPUDeviceInfo::HD5XXX && " 258 "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">; 259def isCayman : Predicate<"Subtarget.device()" 260 "->getDeviceFlag() == OCL_DEVICE_CAYMAN">; 261def isEGorCayman : Predicate<"Subtarget.device()" 262 "->getGeneration() == AMDGPUDeviceInfo::HD5XXX" 263 "|| Subtarget.device()->getGeneration() ==" 264 "AMDGPUDeviceInfo::HD6XXX">; 265 266def isR600toCayman : Predicate< 267 "Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX">; 268 269 270let Predicates = [isR600toCayman] in { 271 272/* ------------------------------------------- */ 273/* Common Instructions R600, R700, Evergreen, Cayman */ 274/* ------------------------------------------- */ 275def ADD : R600_2OP < 276 0x0, "ADD", 277 [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))] 278>; 279 280// Non-IEEE MUL: 0 * anything = 0 281def MUL : R600_2OP < 282 0x1, "MUL NON-IEEE", 283 [(set R600_Reg32:$dst, (int_AMDGPU_mul R600_Reg32:$src0, R600_Reg32:$src1))] 284>; 285 286def MUL_IEEE : R600_2OP < 287 0x2, "MUL_IEEE", 288 [(set R600_Reg32:$dst, (fmul R600_Reg32:$src0, R600_Reg32:$src1))] 289>; 290 291def MAX : R600_2OP < 292 0x3, "MAX", 293 [(set R600_Reg32:$dst, (AMDGPUfmax R600_Reg32:$src0, R600_Reg32:$src1))] 294>; 295 296def MIN : R600_2OP < 297 0x4, "MIN", 298 [(set R600_Reg32:$dst, (AMDGPUfmin R600_Reg32:$src0, R600_Reg32:$src1))] 299>; 300 301/* For the SET* instructions there is a naming conflict in TargetSelectionDAG.td, 302 * so some of the instruction names don't match the asm string. 303 * XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics. 304 */ 305 306def SETE : R600_2OP < 307 0x08, "SETE", 308 [(set R600_Reg32:$dst, 309 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, 310 COND_EQ))] 311>; 312 313def SGT : R600_2OP < 314 0x09, "SETGT", 315 [(set R600_Reg32:$dst, 316 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, 317 COND_GT))] 318>; 319 320def SGE : R600_2OP < 321 0xA, "SETGE", 322 [(set R600_Reg32:$dst, 323 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, 324 COND_GE))] 325>; 326 327def SNE : R600_2OP < 328 0xB, "SETNE", 329 [(set R600_Reg32:$dst, 330 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, 331 COND_NE))] 332>; 333 334def FRACT : R600_1OP < 335 0x10, "FRACT", 336 [(set R600_Reg32:$dst, (AMDGPUfract R600_Reg32:$src))] 337>; 338 339def TRUNC : R600_1OP < 340 0x11, "TRUNC", 341 [(set R600_Reg32:$dst, (int_AMDGPU_trunc R600_Reg32:$src))] 342>; 343 344def CEIL : R600_1OP < 345 0x12, "CEIL", 346 [(set R600_Reg32:$dst, (fceil R600_Reg32:$src))] 347>; 348 349def RNDNE : R600_1OP < 350 0x13, "RNDNE", 351 [(set R600_Reg32:$dst, (frint R600_Reg32:$src))] 352>; 353 354def FLOOR : R600_1OP < 355 0x14, "FLOOR", 356 [(set R600_Reg32:$dst, (int_AMDGPU_floor R600_Reg32:$src))] 357>; 358 359def MOV : R600_1OP <0x19, "MOV", []>; 360 361class MOV_IMM <ValueType vt, Operand immType> : InstR600 <0x19, 362 (outs R600_Reg32:$dst), 363 (ins R600_Reg32:$alu_literal, R600_Pred:$p, immType:$imm), 364 "MOV_IMM $dst, $imm", 365 [], AnyALU 366>; 367 368def MOV_IMM_I32 : MOV_IMM<i32, i32imm>; 369def : Pat < 370 (imm:$val), 371 (MOV_IMM_I32 (i32 ALU_LITERAL_X), imm:$val) 372>; 373 374def MOV_IMM_F32 : MOV_IMM<f32, f32imm>; 375def : Pat < 376 (fpimm:$val), 377 (MOV_IMM_F32 (i32 ALU_LITERAL_X), fpimm:$val) 378>; 379 380def KILLGT : R600_2OP < 381 0x2D, "KILLGT", 382 [] 383>; 384 385def AND_INT : R600_2OP < 386 0x30, "AND_INT", 387 [(set R600_Reg32:$dst, (and R600_Reg32:$src0, R600_Reg32:$src1))] 388>; 389 390def OR_INT : R600_2OP < 391 0x31, "OR_INT", 392 [(set R600_Reg32:$dst, (or R600_Reg32:$src0, R600_Reg32:$src1))] 393>; 394 395def XOR_INT : R600_2OP < 396 0x32, "XOR_INT", 397 [(set R600_Reg32:$dst, (xor R600_Reg32:$src0, R600_Reg32:$src1))] 398>; 399 400def NOT_INT : R600_1OP < 401 0x33, "NOT_INT", 402 [(set R600_Reg32:$dst, (not R600_Reg32:$src))] 403>; 404 405def ADD_INT : R600_2OP < 406 0x34, "ADD_INT", 407 [(set R600_Reg32:$dst, (add R600_Reg32:$src0, R600_Reg32:$src1))] 408>; 409 410def SUB_INT : R600_2OP < 411 0x35, "SUB_INT", 412 [(set R600_Reg32:$dst, (sub R600_Reg32:$src0, R600_Reg32:$src1))] 413>; 414 415def MAX_INT : R600_2OP < 416 0x36, "MAX_INT", 417 [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]>; 418 419def MIN_INT : R600_2OP < 420 0x37, "MIN_INT", 421 [(set R600_Reg32:$dst, (AMDGPUsmin R600_Reg32:$src0, R600_Reg32:$src1))]>; 422 423def MAX_UINT : R600_2OP < 424 0x38, "MAX_UINT", 425 [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))] 426>; 427 428def MIN_UINT : R600_2OP < 429 0x39, "MIN_UINT", 430 [(set R600_Reg32:$dst, (AMDGPUumin R600_Reg32:$src0, R600_Reg32:$src1))] 431>; 432 433def SETE_INT : R600_2OP < 434 0x3A, "SETE_INT", 435 [(set (i32 R600_Reg32:$dst), 436 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))] 437>; 438 439def SETGT_INT : R600_2OP < 440 0x3B, "SGT_INT", 441 [(set (i32 R600_Reg32:$dst), 442 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGT))] 443>; 444 445def SETGE_INT : R600_2OP < 446 0x3C, "SETGE_INT", 447 [(set (i32 R600_Reg32:$dst), 448 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))] 449>; 450 451def SETNE_INT : R600_2OP < 452 0x3D, "SETNE_INT", 453 [(set (i32 R600_Reg32:$dst), 454 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))] 455>; 456 457def SETGT_UINT : R600_2OP < 458 0x3E, "SETGT_UINT", 459 [(set (i32 R600_Reg32:$dst), 460 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))] 461>; 462 463def SETGE_UINT : R600_2OP < 464 0x3F, "SETGE_UINT", 465 [(set (i32 R600_Reg32:$dst), 466 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))] 467>; 468 469def CNDE_INT : R600_3OP < 470 0x1C, "CNDE_INT", 471 [(set (i32 R600_Reg32:$dst), 472 (select R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))] 473>; 474 475/* Texture instructions */ 476 477 478def TEX_LD : R600_TEX < 479 0x03, "TEX_LD", 480 [(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2, imm:$src3, imm:$src4, imm:$src5))] 481> { 482let AsmString = "TEX_LD $dst, $src0, $src1, $src2, $src3, $src4, $src5"; 483let InOperandList = (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5); 484} 485 486def TEX_GET_TEXTURE_RESINFO : R600_TEX < 487 0x04, "TEX_GET_TEXTURE_RESINFO", 488 [(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$src1, imm:$src2))] 489>; 490 491def TEX_GET_GRADIENTS_H : R600_TEX < 492 0x07, "TEX_GET_GRADIENTS_H", 493 [(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$src1, imm:$src2))] 494>; 495 496def TEX_GET_GRADIENTS_V : R600_TEX < 497 0x08, "TEX_GET_GRADIENTS_V", 498 [(set R600_Reg128:$dst, (int_AMDGPU_ddy R600_Reg128:$src0, imm:$src1, imm:$src2))] 499>; 500 501def TEX_SET_GRADIENTS_H : R600_TEX < 502 0x0B, "TEX_SET_GRADIENTS_H", 503 [] 504>; 505 506def TEX_SET_GRADIENTS_V : R600_TEX < 507 0x0C, "TEX_SET_GRADIENTS_V", 508 [] 509>; 510 511def TEX_SAMPLE : R600_TEX < 512 0x10, "TEX_SAMPLE", 513 [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, imm:$src2))] 514>; 515 516def TEX_SAMPLE_C : R600_TEX < 517 0x18, "TEX_SAMPLE_C", 518 [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))] 519>; 520 521def TEX_SAMPLE_L : R600_TEX < 522 0x11, "TEX_SAMPLE_L", 523 [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, imm:$src2))] 524>; 525 526def TEX_SAMPLE_C_L : R600_TEX < 527 0x19, "TEX_SAMPLE_C_L", 528 [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))] 529>; 530 531def TEX_SAMPLE_LB : R600_TEX < 532 0x12, "TEX_SAMPLE_LB", 533 [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, imm:$src2))] 534>; 535 536def TEX_SAMPLE_C_LB : R600_TEX < 537 0x1A, "TEX_SAMPLE_C_LB", 538 [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))] 539>; 540 541def TEX_SAMPLE_G : R600_TEX < 542 0x14, "TEX_SAMPLE_G", 543 [] 544>; 545 546def TEX_SAMPLE_C_G : R600_TEX < 547 0x1C, "TEX_SAMPLE_C_G", 548 [] 549>; 550 551/* Helper classes for common instructions */ 552 553class MUL_LIT_Common <bits<32> inst> : R600_3OP < 554 inst, "MUL_LIT", 555 [] 556>; 557 558class MULADD_Common <bits<32> inst> : R600_3OP < 559 inst, "MULADD", 560 [(set (f32 R600_Reg32:$dst), 561 (IL_mad R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))] 562>; 563 564class CNDE_Common <bits<32> inst> : R600_3OP < 565 inst, "CNDE", 566 [(set (f32 R600_Reg32:$dst), 567 (select (i32 (fp_to_sint (fneg R600_Reg32:$src0))), (f32 R600_Reg32:$src2), (f32 R600_Reg32:$src1)))] 568>; 569 570class CNDGT_Common <bits<32> inst> : R600_3OP < 571 inst, "CNDGT", 572 [] 573>; 574 575class CNDGE_Common <bits<32> inst> : R600_3OP < 576 inst, "CNDGE", 577 [(set R600_Reg32:$dst, (int_AMDGPU_cndlt R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))] 578>; 579 580class DOT4_Common <bits<32> inst> : R600_REDUCTION < 581 inst, 582 (ins R600_Reg128:$src0, R600_Reg128:$src1), 583 "DOT4 $dst $src0, $src1", 584 [(set R600_Reg32:$dst, (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1))] 585>; 586 587class CUBE_Common <bits<32> inst> : InstR600 < 588 inst, 589 (outs R600_Reg128:$dst), 590 (ins R600_Reg128:$src), 591 "CUBE $dst $src", 592 [(set R600_Reg128:$dst, (int_AMDGPU_cube R600_Reg128:$src))], 593 VecALU 594>; 595 596class EXP_IEEE_Common <bits<32> inst> : R600_1OP < 597 inst, "EXP_IEEE", 598 [(set R600_Reg32:$dst, (fexp2 R600_Reg32:$src))] 599>; 600 601class FLT_TO_INT_Common <bits<32> inst> : R600_1OP < 602 inst, "FLT_TO_INT", 603 [(set R600_Reg32:$dst, (fp_to_sint R600_Reg32:$src))] 604>; 605 606class INT_TO_FLT_Common <bits<32> inst> : R600_1OP < 607 inst, "INT_TO_FLT", 608 [(set R600_Reg32:$dst, (sint_to_fp R600_Reg32:$src))] 609>; 610 611class FLT_TO_UINT_Common <bits<32> inst> : R600_1OP < 612 inst, "FLT_TO_UINT", 613 [(set R600_Reg32:$dst, (fp_to_uint R600_Reg32:$src))] 614>; 615 616class UINT_TO_FLT_Common <bits<32> inst> : R600_1OP < 617 inst, "UINT_TO_FLT", 618 [(set R600_Reg32:$dst, (uint_to_fp R600_Reg32:$src))] 619>; 620 621class LOG_CLAMPED_Common <bits<32> inst> : R600_1OP < 622 inst, "LOG_CLAMPED", 623 [] 624>; 625 626class LOG_IEEE_Common <bits<32> inst> : R600_1OP < 627 inst, "LOG_IEEE", 628 [(set R600_Reg32:$dst, (int_AMDIL_log R600_Reg32:$src))] 629>; 630 631class LSHL_Common <bits<32> inst> : R600_2OP < 632 inst, "LSHL $dst, $src0, $src1", 633 [(set R600_Reg32:$dst, (shl R600_Reg32:$src0, R600_Reg32:$src1))] 634>; 635 636class LSHR_Common <bits<32> inst> : R600_2OP < 637 inst, "LSHR $dst, $src0, $src1", 638 [(set R600_Reg32:$dst, (srl R600_Reg32:$src0, R600_Reg32:$src1))] 639>; 640 641class ASHR_Common <bits<32> inst> : R600_2OP < 642 inst, "ASHR $dst, $src0, $src1", 643 [(set R600_Reg32:$dst, (sra R600_Reg32:$src0, R600_Reg32:$src1))] 644>; 645 646class MULHI_INT_Common <bits<32> inst> : R600_2OP < 647 inst, "MULHI_INT $dst, $src0, $src1", 648 [(set R600_Reg32:$dst, (mulhs R600_Reg32:$src0, R600_Reg32:$src1))] 649>; 650 651class MULHI_UINT_Common <bits<32> inst> : R600_2OP < 652 inst, "MULHI $dst, $src0, $src1", 653 [(set R600_Reg32:$dst, (mulhu R600_Reg32:$src0, R600_Reg32:$src1))] 654>; 655 656class MULLO_INT_Common <bits<32> inst> : R600_2OP < 657 inst, "MULLO_INT $dst, $src0, $src1", 658 [(set R600_Reg32:$dst, (mul R600_Reg32:$src0, R600_Reg32:$src1))] 659>; 660 661class MULLO_UINT_Common <bits<32> inst> : R600_2OP < 662 inst, "MULLO_UINT $dst, $src0, $src1", 663 [] 664>; 665 666class RECIP_CLAMPED_Common <bits<32> inst> : R600_1OP < 667 inst, "RECIP_CLAMPED", 668 [] 669>; 670 671class RECIP_IEEE_Common <bits<32> inst> : R600_1OP < 672 inst, "RECIP_IEEE", 673 [(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))] 674>; 675 676class RECIP_UINT_Common <bits<32> inst> : R600_1OP < 677 inst, "RECIP_INT $dst, $src", 678 [(set R600_Reg32:$dst, (AMDGPUurecip R600_Reg32:$src))] 679>; 680 681class RECIPSQRT_CLAMPED_Common <bits<32> inst> : R600_1OP < 682 inst, "RECIPSQRT_CLAMPED", 683 [(set R600_Reg32:$dst, (int_AMDGPU_rsq R600_Reg32:$src))] 684>; 685 686class RECIPSQRT_IEEE_Common <bits<32> inst> : R600_1OP < 687 inst, "RECIPSQRT_IEEE", 688 [] 689>; 690 691class SIN_Common <bits<32> inst> : R600_1OP < 692 inst, "SIN", []>{ 693 let Trig = 1; 694} 695 696class COS_Common <bits<32> inst> : R600_1OP < 697 inst, "COS", []> { 698 let Trig = 1; 699} 700 701/* Helper patterns for complex intrinsics */ 702/* -------------------------------------- */ 703 704class DIV_Common <InstR600 recip_ieee> : Pat< 705 (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1), 706 (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1)) 707>; 708 709class SSG_Common <InstR600 cndgt, InstR600 cndge> : Pat < 710 (int_AMDGPU_ssg R600_Reg32:$src), 711 (cndgt R600_Reg32:$src, (f32 ONE), (cndge R600_Reg32:$src, (f32 ZERO), (f32 NEG_ONE))) 712>; 713 714class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> : Pat < 715 (int_TGSI_lit_z R600_Reg32:$src_x, R600_Reg32:$src_y, R600_Reg32:$src_w), 716 (exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x)) 717>; 718 719/* ---------------------- */ 720/* R600 / R700 Only Instructions */ 721/* ---------------------- */ 722 723let Predicates = [isR600] in { 724 725 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>; 726 def MULADD_r600 : MULADD_Common<0x10>; 727 def CNDE_r600 : CNDE_Common<0x18>; 728 def CNDGT_r600 : CNDGT_Common<0x19>; 729 def CNDGE_r600 : CNDGE_Common<0x1A>; 730 def DOT4_r600 : DOT4_Common<0x50>; 731 def CUBE_r600 : CUBE_Common<0x52>; 732 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>; 733 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>; 734 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>; 735 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>; 736 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>; 737 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>; 738 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>; 739 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>; 740 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>; 741 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>; 742 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>; 743 def SIN_r600 : SIN_Common<0x6E>; 744 def COS_r600 : COS_Common<0x6F>; 745 def ASHR_r600 : ASHR_Common<0x70>; 746 def LSHR_r600 : LSHR_Common<0x71>; 747 def LSHL_r600 : LSHL_Common<0x72>; 748 def MULLO_INT_r600 : MULLO_INT_Common<0x73>; 749 def MULHI_INT_r600 : MULHI_INT_Common<0x74>; 750 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>; 751 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>; 752 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>; 753 754 def DIV_r600 : DIV_Common<RECIP_IEEE_r600>; 755 def POW_r600 : POW_Common<LOG_IEEE_r600, EXP_IEEE_r600, MUL, GPRF32>; 756 def SSG_r600 : SSG_Common<CNDGT_r600, CNDGE_r600>; 757 def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>; 758 759} 760 761// Helper pattern for normalizing inputs to triginomic instructions for R700+ 762// cards. 763class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat< 764 (intr R600_Reg32:$src), 765 (trig (MUL (MOV_IMM_I32 (i32 ALU_LITERAL_X), CONST.TWO_PI_INV), R600_Reg32:$src)) 766>; 767 768//===----------------------------------------------------------------------===// 769// R700 Only instructions 770//===----------------------------------------------------------------------===// 771 772let Predicates = [isR700] in { 773 def SIN_r700 : SIN_Common<0x6E>; 774 def COS_r700 : COS_Common<0x6F>; 775 776 // R700 normalizes inputs to SIN/COS the same as EG 777 def : TRIG_eg <SIN_r700, int_AMDGPU_sin>; 778 def : TRIG_eg <COS_r700, int_AMDGPU_cos>; 779} 780 781//===----------------------------------------------------------------------===// 782// Evergreen Only instructions 783//===----------------------------------------------------------------------===// 784 785let Predicates = [isEG] in { 786 787def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>; 788 789def MULLO_INT_eg : MULLO_INT_Common<0x8F>; 790def MULHI_INT_eg : MULHI_INT_Common<0x90>; 791def MULLO_UINT_eg : MULLO_UINT_Common<0x91>; 792def MULHI_UINT_eg : MULHI_UINT_Common<0x92>; 793def RECIP_UINT_eg : RECIP_UINT_Common<0x94>; 794 795} // End Predicates = [isEG] 796 797/* ------------------------------- */ 798/* Evergreen / Cayman Instructions */ 799/* ------------------------------- */ 800 801let Predicates = [isEGorCayman] in { 802 803 // BFE_UINT - bit_extract, an optimization for mask and shift 804 // Src0 = Input 805 // Src1 = Offset 806 // Src2 = Width 807 // 808 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width) 809 // 810 // Example Usage: 811 // (Offset, Width) 812 // 813 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0 814 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8 815 // (16,8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16 816 // (24,8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24 817 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT", 818 [(set R600_Reg32:$dst, (int_AMDIL_bit_extract_u32 R600_Reg32:$src0, 819 R600_Reg32:$src1, 820 R600_Reg32:$src2))], 821 VecALU 822 >; 823 824 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", 825 [(set R600_Reg32:$dst, (AMDGPUbitalign R600_Reg32:$src0, R600_Reg32:$src1, 826 R600_Reg32:$src2))], 827 VecALU 828 >; 829 830 def MULADD_eg : MULADD_Common<0x14>; 831 def ASHR_eg : ASHR_Common<0x15>; 832 def LSHR_eg : LSHR_Common<0x16>; 833 def LSHL_eg : LSHL_Common<0x17>; 834 def CNDE_eg : CNDE_Common<0x19>; 835 def CNDGT_eg : CNDGT_Common<0x1A>; 836 def CNDGE_eg : CNDGE_Common<0x1B>; 837 def MUL_LIT_eg : MUL_LIT_Common<0x1F>; 838 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>; 839 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>; 840 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>; 841 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>; 842 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>; 843 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>; 844 def SIN_eg : SIN_Common<0x8D>; 845 def COS_eg : COS_Common<0x8E>; 846 def DOT4_eg : DOT4_Common<0xBE>; 847 def CUBE_eg : CUBE_Common<0xC0>; 848 849 def DIV_eg : DIV_Common<RECIP_IEEE_eg>; 850 def POW_eg : POW_Common<LOG_IEEE_eg, EXP_IEEE_eg, MUL, GPRF32>; 851 def SSG_eg : SSG_Common<CNDGT_eg, CNDGE_eg>; 852 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>; 853 854 def : TRIG_eg <SIN_eg, int_AMDGPU_sin>; 855 def : TRIG_eg <COS_eg, int_AMDGPU_cos>; 856 857 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> { 858 let Pattern = []; 859 } 860 861 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>; 862 863 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> { 864 let Pattern = []; 865 } 866 867 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>; 868 869 def : Pat<(fp_to_sint R600_Reg32:$src), 870 (FLT_TO_INT_eg (TRUNC R600_Reg32:$src))>; 871 872 def : Pat<(fp_to_uint R600_Reg32:$src), 873 (FLT_TO_UINT_eg (TRUNC R600_Reg32:$src))>; 874 875//===----------------------------------------------------------------------===// 876// Memory read/write instructions 877//===----------------------------------------------------------------------===// 878 879let usesCustomInserter = 1 in { 880 881def RAT_WRITE_CACHELESS_eg : EG_CF_RAT <0x57, 0x2, 0, (outs), 882 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr), 883 "RAT_WRITE_CACHELESS_eg $rw_gpr, $index_gpr", 884 [(global_store (i32 R600_TReg32_X:$rw_gpr), R600_TReg32_X:$index_gpr)]> 885{ 886 let RIM = 0; 887 /* XXX: Have a separate instruction for non-indexed writes. */ 888 let TYPE = 1; 889 let RW_REL = 0; 890 let ELEM_SIZE = 0; 891 892 let ARRAY_SIZE = 0; 893 let COMP_MASK = 1; 894 let BURST_COUNT = 0; 895 let VPM = 0; 896 let EOP = 0; 897 let MARK = 0; 898 let BARRIER = 1; 899} 900 901} // End usesCustomInserter = 1 902 903// Floating point global_store 904def : Pat < 905 (global_store (f32 R600_TReg32_X:$val), R600_TReg32_X:$ptr), 906 (RAT_WRITE_CACHELESS_eg R600_TReg32_X:$val, R600_TReg32_X:$ptr) 907>; 908 909class VTX_READ_eg <bits<8> buffer_id, dag outs, list<dag> pattern> 910 : InstR600ISA <outs, (ins MEMxi:$ptr), "VTX_READ_eg $dst, $ptr", pattern> { 911 912 // Operands 913 bits<7> DST_GPR; 914 bits<7> SRC_GPR; 915 916 // Static fields 917 bits<5> VC_INST = 0; 918 bits<2> FETCH_TYPE = 2; 919 bits<1> FETCH_WHOLE_QUAD = 0; 920 bits<8> BUFFER_ID = buffer_id; 921 bits<1> SRC_REL = 0; 922 // XXX: We can infer this field based on the SRC_GPR. This would allow us 923 // to store vertex addresses in any channel, not just X. 924 bits<2> SRC_SEL_X = 0; 925 bits<6> MEGA_FETCH_COUNT; 926 bits<1> DST_REL = 0; 927 bits<3> DST_SEL_X; 928 bits<3> DST_SEL_Y; 929 bits<3> DST_SEL_Z; 930 bits<3> DST_SEL_W; 931 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL, 932 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored, 933 // however, based on my testing if USE_CONST_FIELDS is set, then all 934 // these fields need to be set to 0. 935 bits<1> USE_CONST_FIELDS = 0; 936 bits<6> DATA_FORMAT; 937 bits<2> NUM_FORMAT_ALL = 1; 938 bits<1> FORMAT_COMP_ALL = 0; 939 bits<1> SRF_MODE_ALL = 0; 940 941 // LLVM can only encode 64-bit instructions, so these fields are manually 942 // encoded in R600CodeEmitter 943 // 944 // bits<16> OFFSET; 945 // bits<2> ENDIAN_SWAP = 0; 946 // bits<1> CONST_BUF_NO_STRIDE = 0; 947 // bits<1> MEGA_FETCH = 0; 948 // bits<1> ALT_CONST = 0; 949 // bits<2> BUFFER_INDEX_MODE = 0; 950 951 // VTX_WORD0 952 let Inst{4-0} = VC_INST; 953 let Inst{6-5} = FETCH_TYPE; 954 let Inst{7} = FETCH_WHOLE_QUAD; 955 let Inst{15-8} = BUFFER_ID; 956 let Inst{22-16} = SRC_GPR; 957 let Inst{23} = SRC_REL; 958 let Inst{25-24} = SRC_SEL_X; 959 let Inst{31-26} = MEGA_FETCH_COUNT; 960 961 // VTX_WORD1_GPR 962 let Inst{38-32} = DST_GPR; 963 let Inst{39} = DST_REL; 964 let Inst{40} = 0; // Reserved 965 let Inst{43-41} = DST_SEL_X; 966 let Inst{46-44} = DST_SEL_Y; 967 let Inst{49-47} = DST_SEL_Z; 968 let Inst{52-50} = DST_SEL_W; 969 let Inst{53} = USE_CONST_FIELDS; 970 let Inst{59-54} = DATA_FORMAT; 971 let Inst{61-60} = NUM_FORMAT_ALL; 972 let Inst{62} = FORMAT_COMP_ALL; 973 let Inst{63} = SRF_MODE_ALL; 974 975 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding 976 // is done in R600CodeEmitter 977 // 978 // Inst{79-64} = OFFSET; 979 // Inst{81-80} = ENDIAN_SWAP; 980 // Inst{82} = CONST_BUF_NO_STRIDE; 981 // Inst{83} = MEGA_FETCH; 982 // Inst{84} = ALT_CONST; 983 // Inst{86-85} = BUFFER_INDEX_MODE; 984 // Inst{95-86} = 0; Reserved 985 986 // VTX_WORD3 (Padding) 987 // 988 // Inst{127-96} = 0; 989} 990 991class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern> 992 : VTX_READ_eg <buffer_id, (outs R600_TReg32_X:$dst), pattern> { 993 994 let MEGA_FETCH_COUNT = 4; 995 let DST_SEL_X = 0; 996 let DST_SEL_Y = 7; // Masked 997 let DST_SEL_Z = 7; // Masked 998 let DST_SEL_W = 7; // Masked 999 let DATA_FORMAT = 0xD; // COLOR_32 1000 1001 // This is not really necessary, but there were some GPU hangs that appeared 1002 // to be caused by ALU instructions in the next instruction group that wrote 1003 // to the $ptr registers of the VTX_READ. 1004 // e.g. 1005 // %T3_X<def> = VTX_READ_PARAM_i32_eg %T2_X<kill>, 24 1006 // %T2_X<def> = MOV %ZERO 1007 //Adding this constraint prevents this from happening. 1008 let Constraints = "$ptr.ptr = $dst"; 1009} 1010 1011class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern> 1012 : VTX_READ_eg <buffer_id, (outs R600_Reg128:$dst), pattern> { 1013 1014 let MEGA_FETCH_COUNT = 16; 1015 let DST_SEL_X = 0; 1016 let DST_SEL_Y = 1; 1017 let DST_SEL_Z = 2; 1018 let DST_SEL_W = 3; 1019 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32 1020 1021 // XXX: Need to force VTX_READ_128 instructions to write to the same register 1022 // that holds its buffer address to avoid potential hangs. We can't use 1023 // the same constraint as VTX_READ_32_eg, because the $ptr.ptr and $dst 1024 // registers are different sizes. 1025} 1026 1027//===----------------------------------------------------------------------===// 1028// VTX Read from parameter memory space 1029//===----------------------------------------------------------------------===// 1030 1031class VTX_READ_PARAM_32_eg <ValueType vt> : VTX_READ_32_eg <0, 1032 [(set (vt R600_TReg32_X:$dst), (load_param ADDRVTX_READ:$ptr))] 1033>; 1034 1035def VTX_READ_PARAM_i32_eg : VTX_READ_PARAM_32_eg<i32>; 1036def VTX_READ_PARAM_f32_eg : VTX_READ_PARAM_32_eg<f32>; 1037 1038 1039//===----------------------------------------------------------------------===// 1040// VTX Read from global memory space 1041//===----------------------------------------------------------------------===// 1042 1043// 32-bit reads 1044 1045class VTX_READ_GLOBAL_eg <ValueType vt> : VTX_READ_32_eg <1, 1046 [(set (vt R600_TReg32_X:$dst), (global_load ADDRVTX_READ:$ptr))] 1047>; 1048 1049def VTX_READ_GLOBAL_i32_eg : VTX_READ_GLOBAL_eg<i32>; 1050def VTX_READ_GLOBAL_f32_eg : VTX_READ_GLOBAL_eg<f32>; 1051 1052// 128-bit reads 1053 1054class VTX_READ_GLOBAL_128_eg <ValueType vt> : VTX_READ_128_eg <1, 1055 [(set (vt R600_Reg128:$dst), (global_load ADDRVTX_READ:$ptr))] 1056>; 1057 1058def VTX_READ_GLOBAL_v4i32_eg : VTX_READ_GLOBAL_128_eg<v4i32>; 1059def VTX_READ_GLOBAL_v4f32_eg : VTX_READ_GLOBAL_128_eg<v4f32>; 1060 1061} 1062 1063let Predicates = [isCayman] in { 1064 1065let isVector = 1 in { 1066 1067def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>; 1068 1069def MULLO_INT_cm : MULLO_INT_Common<0x8F>; 1070def MULHI_INT_cm : MULHI_INT_Common<0x90>; 1071def MULLO_UINT_cm : MULLO_UINT_Common<0x91>; 1072def MULHI_UINT_cm : MULHI_UINT_Common<0x92>; 1073 1074} // End isVector = 1 1075 1076// RECIP_UINT emulation for Cayman 1077def : Pat < 1078 (AMDGPUurecip R600_Reg32:$src0), 1079 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg R600_Reg32:$src0)), 1080 (MOV_IMM_I32 (i32 ALU_LITERAL_X), 0x4f800000))) 1081>; 1082 1083} // End isCayman 1084 1085/* Other Instructions */ 1086 1087let isCodeGenOnly = 1 in { 1088/* 1089 def SWIZZLE : AMDGPUShaderInst < 1090 (outs GPRV4F32:$dst), 1091 (ins GPRV4F32:$src0, i32imm:$src1), 1092 "SWIZZLE $dst, $src0, $src1", 1093 [(set GPRV4F32:$dst, (int_AMDGPU_swizzle GPRV4F32:$src0, imm:$src1))] 1094 >; 1095*/ 1096 1097 def LAST : AMDGPUShaderInst < 1098 (outs), 1099 (ins), 1100 "LAST", 1101 [] 1102 >; 1103 1104 def GET_CHAN : AMDGPUShaderInst < 1105 (outs R600_Reg32:$dst), 1106 (ins R600_Reg128:$src0, i32imm:$src1), 1107 "GET_CHAN $dst, $src0, $src1", 1108 [] 1109 >; 1110 1111 def MULLIT : AMDGPUShaderInst < 1112 (outs R600_Reg128:$dst), 1113 (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2), 1114 "MULLIT $dst, $src0, $src1", 1115 [(set R600_Reg128:$dst, (int_AMDGPU_mullit R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))] 1116 >; 1117 1118let usesCustomInserter = 1, isPseudo = 1 in { 1119 1120class R600PreloadInst <string asm, Intrinsic intr> : AMDGPUInst < 1121 (outs R600_TReg32:$dst), 1122 (ins), 1123 asm, 1124 [(set R600_TReg32:$dst, (intr))] 1125>; 1126 1127def NGROUPS_X : R600PreloadInst <"NGROUPS_X", int_r600_read_ngroups_x>; 1128def NGROUPS_Y : R600PreloadInst <"NGROUPS_Y", int_r600_read_ngroups_y>; 1129def NGROUPS_Z : R600PreloadInst <"NGROUPS_Z", int_r600_read_ngroups_z>; 1130 1131def GLOBAL_SIZE_X : R600PreloadInst <"GLOBAL_SIZE_X", 1132 int_r600_read_global_size_x>; 1133def GLOBAL_SIZE_Y : R600PreloadInst <"GLOBAL_SIZE_Y", 1134 int_r600_read_global_size_y>; 1135def GLOBAL_SIZE_Z : R600PreloadInst <"GLOBAL_SIZE_Z", 1136 int_r600_read_global_size_z>; 1137 1138def LOCAL_SIZE_X : R600PreloadInst <"LOCAL_SIZE_X", 1139 int_r600_read_local_size_x>; 1140def LOCAL_SIZE_Y : R600PreloadInst <"LOCAL_SIZE_Y", 1141 int_r600_read_local_size_y>; 1142def LOCAL_SIZE_Z : R600PreloadInst <"LOCAL_SIZE_Z", 1143 int_r600_read_local_size_z>; 1144 1145def R600_LOAD_CONST : AMDGPUShaderInst < 1146 (outs R600_Reg32:$dst), 1147 (ins i32imm:$src0), 1148 "R600_LOAD_CONST $dst, $src0", 1149 [(set R600_Reg32:$dst, (int_AMDGPU_load_const imm:$src0))] 1150>; 1151 1152def RESERVE_REG : AMDGPUShaderInst < 1153 (outs), 1154 (ins i32imm:$src), 1155 "RESERVE_REG $src", 1156 [(int_AMDGPU_reserve_reg imm:$src)] 1157>; 1158 1159def TXD: AMDGPUShaderInst < 1160 (outs R600_Reg128:$dst), 1161 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4), 1162 "TXD $dst, $src0, $src1, $src2, $src3, $src4", 1163 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, imm:$src4))] 1164>; 1165 1166def TXD_SHADOW: AMDGPUShaderInst < 1167 (outs R600_Reg128:$dst), 1168 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4), 1169 "TXD_SHADOW $dst, $src0, $src1, $src2, $src3, $src4", 1170 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, TEX_SHADOW:$src4))] 1171>; 1172 1173} // End usesCustomInserter = 1, isPseudo = 1 1174 1175} // End isCodeGenOnly = 1 1176 1177def CLAMP_R600 : CLAMP <R600_Reg32>; 1178def FABS_R600 : FABS<R600_Reg32>; 1179def FNEG_R600 : FNEG<R600_Reg32>; 1180 1181let usesCustomInserter = 1 in { 1182 1183def MASK_WRITE : AMDGPUShaderInst < 1184 (outs), 1185 (ins R600_Reg32:$src), 1186 "MASK_WRITE $src", 1187 [] 1188>; 1189 1190} // End usesCustomInserter = 1 1191 1192//===----------------------------------------------------------------------===// 1193// ISel Patterns 1194//===----------------------------------------------------------------------===// 1195 1196// KIL Patterns 1197def KILP : Pat < 1198 (int_AMDGPU_kilp), 1199 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO))) 1200>; 1201 1202def KIL : Pat < 1203 (int_AMDGPU_kill R600_Reg32:$src0), 1204 (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0))) 1205>; 1206 1207// SGT Reverse args 1208def : Pat < 1209 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LT), 1210 (SGT R600_Reg32:$src1, R600_Reg32:$src0) 1211>; 1212 1213// SGE Reverse args 1214def : Pat < 1215 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LE), 1216 (SGE R600_Reg32:$src1, R600_Reg32:$src0) 1217>; 1218 1219// SETGT_INT reverse args 1220def : Pat < 1221 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLT), 1222 (SETGT_INT R600_Reg32:$src1, R600_Reg32:$src0) 1223>; 1224 1225// SETGE_INT reverse args 1226def : Pat < 1227 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLE), 1228 (SETGE_INT R600_Reg32:$src1, R600_Reg32:$src0) 1229>; 1230 1231// SETGT_UINT reverse args 1232def : Pat < 1233 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULT), 1234 (SETGT_UINT R600_Reg32:$src1, R600_Reg32:$src0) 1235>; 1236 1237// SETGE_UINT reverse args 1238def : Pat < 1239 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULE), 1240 (SETGE_UINT R600_Reg32:$src0, R600_Reg32:$src1) 1241>; 1242 1243// The next two patterns are special cases for handling 'true if ordered' and 1244// 'true if unordered' conditionals. The assumption here is that the behavior of 1245// SETE and SNE conforms to the Direct3D 10 rules for floating point values 1246// described here: 1247// http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit 1248// We assume that SETE returns false when one of the operands is NAN and 1249// SNE returns true when on of the operands is NAN 1250 1251//SETE - 'true if ordered' 1252def : Pat < 1253 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETO), 1254 (SETE R600_Reg32:$src0, R600_Reg32:$src1) 1255>; 1256 1257//SNE - 'true if unordered' 1258def : Pat < 1259 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETUO), 1260 (SNE R600_Reg32:$src0, R600_Reg32:$src1) 1261>; 1262 1263def : Extract_Element <f32, v4f32, R600_Reg128, 0, sel_x>; 1264def : Extract_Element <f32, v4f32, R600_Reg128, 1, sel_y>; 1265def : Extract_Element <f32, v4f32, R600_Reg128, 2, sel_z>; 1266def : Extract_Element <f32, v4f32, R600_Reg128, 3, sel_w>; 1267 1268def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 4, sel_x>; 1269def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 5, sel_y>; 1270def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 6, sel_z>; 1271def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 7, sel_w>; 1272 1273def : Extract_Element <i32, v4i32, R600_Reg128, 0, sel_x>; 1274def : Extract_Element <i32, v4i32, R600_Reg128, 1, sel_y>; 1275def : Extract_Element <i32, v4i32, R600_Reg128, 2, sel_z>; 1276def : Extract_Element <i32, v4i32, R600_Reg128, 3, sel_w>; 1277 1278def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 4, sel_x>; 1279def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 5, sel_y>; 1280def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 6, sel_z>; 1281def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 7, sel_w>; 1282 1283def : Vector_Build <v4f32, R600_Reg32>; 1284def : Vector_Build <v4i32, R600_Reg32>; 1285 1286// bitconvert patterns 1287 1288def : BitConvert <i32, f32, R600_Reg32>; 1289def : BitConvert <f32, i32, R600_Reg32>; 1290def : BitConvert <v4f32, v4i32, R600_Reg128>; 1291 1292} // End isR600toCayman Predicate 1293