R600Instructions.td revision e61c54cb6b220dea243568919a001e5dc7c01303
1//===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// R600 Tablegen instruction definitions 11// 12//===----------------------------------------------------------------------===// 13 14include "R600Intrinsics.td" 15 16class InstR600 <bits<32> inst, dag outs, dag ins, string asm, list<dag> pattern, 17 InstrItinClass itin> 18 : AMDGPUInst <outs, ins, asm, pattern> { 19 20 field bits<32> Inst; 21 bit Trig = 0; 22 bit Op3 = 0; 23 bit isVector = 0; 24 bits<2> FlagOperandIdx = 0; 25 26 let Inst = inst; 27 let Namespace = "AMDGPU"; 28 let OutOperandList = outs; 29 let InOperandList = ins; 30 let AsmString = asm; 31 let Pattern = pattern; 32 let Itinerary = itin; 33 34 let TSFlags{4} = Trig; 35 let TSFlags{5} = Op3; 36 37 // Vector instructions are instructions that must fill all slots in an 38 // instruction group 39 let TSFlags{6} = isVector; 40 let TSFlags{8-7} = FlagOperandIdx; 41} 42 43class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> : 44 AMDGPUInst <outs, ins, asm, pattern> 45{ 46 field bits<64> Inst; 47 48 let Namespace = "AMDGPU"; 49} 50 51def MEMxi : Operand<iPTR> { 52 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index); 53} 54 55def MEMrr : Operand<iPTR> { 56 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index); 57} 58 59def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>; 60def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>; 61def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>; 62 63class R600_ALU { 64 65 bits<7> DST_GPR = 0; 66 bits<9> SRC0_SEL = 0; 67 bits<1> SRC0_NEG = 0; 68 bits<9> SRC1_SEL = 0; 69 bits<1> SRC1_NEG = 0; 70 bits<1> CLAMP = 0; 71 72} 73 74def R600_Pred : PredicateOperand<i32, (ops R600_Predicate), 75 (ops PRED_SEL_OFF)>; 76 77 78class R600_1OP <bits<32> inst, string opName, list<dag> pattern, 79 InstrItinClass itin = AnyALU> : 80 InstR600 <inst, 81 (outs R600_Reg32:$dst), 82 (ins R600_Reg32:$src, R600_Pred:$p, variable_ops), 83 !strconcat(opName, " $dst, $src ($p)"), 84 pattern, 85 itin 86 >; 87 88class R600_2OP <bits<32> inst, string opName, list<dag> pattern, 89 InstrItinClass itin = AnyALU> : 90 InstR600 <inst, 91 (outs R600_Reg32:$dst), 92 (ins R600_Reg32:$src0, R600_Reg32:$src1,R600_Pred:$p, variable_ops), 93 !strconcat(opName, " $dst, $src0, $src1"), 94 pattern, 95 itin 96 >; 97 98class R600_3OP <bits<32> inst, string opName, list<dag> pattern, 99 InstrItinClass itin = AnyALU> : 100 InstR600 <inst, 101 (outs R600_Reg32:$dst), 102 (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2,R600_Pred:$p, variable_ops), 103 !strconcat(opName, " $dst, $src0, $src1, $src2"), 104 pattern, 105 itin>{ 106 107 let Op3 = 1; 108 } 109 110 111 112def PRED_X : InstR600 <0, (outs R600_Predicate_Bit:$dst), 113 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags), 114 "PRED $dst, $src0, $src1", 115 [], NullALU> 116{ 117 let DisableEncoding = "$src0"; 118 field bits<32> Inst; 119 bits<32> src1; 120 121 let Inst = src1; 122 let FlagOperandIdx = 3; 123} 124 125let isTerminator = 1, isBranch = 1, isPseudo = 1 in { 126def JUMP : InstR600 <0x10, 127 (outs), 128 (ins brtarget:$target, R600_Pred:$p), 129 "JUMP $target ($p)", 130 [], AnyALU 131 >; 132} 133 134class R600_REDUCTION <bits<32> inst, dag ins, string asm, list<dag> pattern, 135 InstrItinClass itin = VecALU> : 136 InstR600 <inst, 137 (outs R600_Reg32:$dst), 138 ins, 139 asm, 140 pattern, 141 itin 142 143 >; 144 145class R600_TEX <bits<32> inst, string opName, list<dag> pattern, 146 InstrItinClass itin = AnyALU> : 147 InstR600 <inst, 148 (outs R600_Reg128:$dst), 149 (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2), 150 !strconcat(opName, "$dst, $src0, $src1, $src2"), 151 pattern, 152 itin 153 >; 154 155def TEX_SHADOW : PatLeaf< 156 (imm), 157 [{uint32_t TType = (uint32_t)N->getZExtValue(); 158 return (TType >= 6 && TType <= 8) || TType == 11 || TType == 12; 159 }] 160>; 161 162class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs, 163 dag ins, string asm, list<dag> pattern> : 164 InstR600ISA <outs, ins, asm, pattern> 165{ 166 bits<7> RW_GPR; 167 bits<7> INDEX_GPR; 168 169 bits<2> RIM; 170 bits<2> TYPE; 171 bits<1> RW_REL; 172 bits<2> ELEM_SIZE; 173 174 bits<12> ARRAY_SIZE; 175 bits<4> COMP_MASK; 176 bits<4> BURST_COUNT; 177 bits<1> VPM; 178 bits<1> EOP; 179 bits<1> MARK; 180 bits<1> BARRIER; 181 182 /* CF_ALLOC_EXPORT_WORD0_RAT */ 183 let Inst{3-0} = rat_id; 184 let Inst{9-4} = rat_inst; 185 let Inst{10} = 0; /* Reserved */ 186 let Inst{12-11} = RIM; 187 let Inst{14-13} = TYPE; 188 let Inst{21-15} = RW_GPR; 189 let Inst{22} = RW_REL; 190 let Inst{29-23} = INDEX_GPR; 191 let Inst{31-30} = ELEM_SIZE; 192 193 /* CF_ALLOC_EXPORT_WORD1_BUF */ 194 let Inst{43-32} = ARRAY_SIZE; 195 let Inst{47-44} = COMP_MASK; 196 let Inst{51-48} = BURST_COUNT; 197 let Inst{52} = VPM; 198 let Inst{53} = EOP; 199 let Inst{61-54} = cf_inst; 200 let Inst{62} = MARK; 201 let Inst{63} = BARRIER; 202} 203 204/* 205def store_global : PatFrag<(ops node:$value, node:$ptr), 206 (store node:$value, node:$ptr), 207 [{ 208 const Value *Src; 209 const PointerType *Type; 210 if ((src = cast<StoreSDNode>(N)->getSrcValue() && 211 PT = dyn_cast<PointerType>(Src->getType()))) { 212 return PT->getAddressSpace() == 1; 213 } 214 return false; 215 }]>; 216 217*/ 218 219def load_param : PatFrag<(ops node:$ptr), 220 (load node:$ptr), 221 [{ 222 const Value *Src = cast<LoadSDNode>(N)->getSrcValue(); 223 if (Src) { 224 PointerType * PT = dyn_cast<PointerType>(Src->getType()); 225 return PT && PT->getAddressSpace() == AMDGPUAS::PARAM_I_ADDRESS; 226 } 227 return false; 228 }]>; 229 230//class EG_CF <bits<32> inst, string asm> : 231// InstR600 <inst, (outs), (ins), asm, []>; 232 233/* XXX: We will use this when we emit the real ISA. 234 bits<24> ADDR = 0; 235 bits<3> JTS = 0; 236 237 bits<3> PC = 0; 238 bits<5> CF_CONS = 0; 239 bits<2> COND = 0; 240 bits<6> COUNT = 0; 241 bits<1> VPM = 0; 242 bits<1> EOP = 0; 243 bits<8> CF_INST = 0; 244 bits<1> WQM = 0; 245 bits<1> B = 0; 246 247 let Inst{23-0} = ADDR; 248 let Inst{26-24} = JTS; 249 let Inst{34-32} = PC; 250 let Inst{39-35} = CF_CONST; 251 let Inst{41-40} = COND; 252 let Inst{47-42} = COUNT; 253 let Inst{52} = VPM; 254 let Inst{53} = EOP; 255 let Inst{61-54} = CF_INST; 256 let Inst{62} = WQM; 257 let Inst{63} = B; 258//} 259*/ 260def isR600 : Predicate<"Subtarget.device()" 261 "->getGeneration() == AMDGPUDeviceInfo::HD4XXX">; 262def isR700 : Predicate<"Subtarget.device()" 263 "->getGeneration() == AMDGPUDeviceInfo::HD4XXX &&" 264 "Subtarget.device()->getDeviceFlag()" 265 ">= OCL_DEVICE_RV710">; 266def isEG : Predicate<"Subtarget.device()" 267 "->getGeneration() >= AMDGPUDeviceInfo::HD5XXX && " 268 "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">; 269def isCayman : Predicate<"Subtarget.device()" 270 "->getDeviceFlag() == OCL_DEVICE_CAYMAN">; 271def isEGorCayman : Predicate<"Subtarget.device()" 272 "->getGeneration() == AMDGPUDeviceInfo::HD5XXX" 273 "|| Subtarget.device()->getGeneration() ==" 274 "AMDGPUDeviceInfo::HD6XXX">; 275 276def isR600toCayman : Predicate< 277 "Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX">; 278 279 280let Predicates = [isR600toCayman] in { 281 282/* ------------------------------------------- */ 283/* Common Instructions R600, R700, Evergreen, Cayman */ 284/* ------------------------------------------- */ 285def ADD : R600_2OP < 286 0x0, "ADD", 287 [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))] 288>; 289 290// Non-IEEE MUL: 0 * anything = 0 291def MUL : R600_2OP < 292 0x1, "MUL NON-IEEE", 293 [(set R600_Reg32:$dst, (int_AMDGPU_mul R600_Reg32:$src0, R600_Reg32:$src1))] 294>; 295 296def MUL_IEEE : R600_2OP < 297 0x2, "MUL_IEEE", 298 [(set R600_Reg32:$dst, (fmul R600_Reg32:$src0, R600_Reg32:$src1))] 299>; 300 301def MAX : R600_2OP < 302 0x3, "MAX", 303 [(set R600_Reg32:$dst, (AMDGPUfmax R600_Reg32:$src0, R600_Reg32:$src1))] 304>; 305 306def MIN : R600_2OP < 307 0x4, "MIN", 308 [(set R600_Reg32:$dst, (AMDGPUfmin R600_Reg32:$src0, R600_Reg32:$src1))] 309>; 310 311/* For the SET* instructions there is a naming conflict in TargetSelectionDAG.td, 312 * so some of the instruction names don't match the asm string. 313 * XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics. 314 */ 315 316def SETE : R600_2OP < 317 0x08, "SETE", 318 [(set R600_Reg32:$dst, 319 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, 320 COND_EQ))] 321>; 322 323def SGT : R600_2OP < 324 0x09, "SETGT", 325 [(set R600_Reg32:$dst, 326 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, 327 COND_GT))] 328>; 329 330def SGE : R600_2OP < 331 0xA, "SETGE", 332 [(set R600_Reg32:$dst, 333 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, 334 COND_GE))] 335>; 336 337def SNE : R600_2OP < 338 0xB, "SETNE", 339 [(set R600_Reg32:$dst, 340 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, 341 COND_NE))] 342>; 343 344def FRACT : R600_1OP < 345 0x10, "FRACT", 346 [(set R600_Reg32:$dst, (AMDGPUfract R600_Reg32:$src))] 347>; 348 349def TRUNC : R600_1OP < 350 0x11, "TRUNC", 351 [(set R600_Reg32:$dst, (int_AMDGPU_trunc R600_Reg32:$src))] 352>; 353 354def CEIL : R600_1OP < 355 0x12, "CEIL", 356 [(set R600_Reg32:$dst, (fceil R600_Reg32:$src))] 357>; 358 359def RNDNE : R600_1OP < 360 0x13, "RNDNE", 361 [(set R600_Reg32:$dst, (frint R600_Reg32:$src))] 362>; 363 364def FLOOR : R600_1OP < 365 0x14, "FLOOR", 366 [(set R600_Reg32:$dst, (int_AMDGPU_floor R600_Reg32:$src))] 367>; 368 369def MOV : InstR600 <0x19, (outs R600_Reg32:$dst), 370 (ins R600_Reg32:$src0, i32imm:$flags, 371 R600_Pred:$p), 372 "MOV $dst, $src0", [], AnyALU> { 373 let FlagOperandIdx = 2; 374} 375 376class MOV_IMM <ValueType vt, Operand immType> : InstR600 <0x19, 377 (outs R600_Reg32:$dst), 378 (ins R600_Reg32:$alu_literal, R600_Pred:$p, immType:$imm), 379 "MOV_IMM $dst, $imm", 380 [], AnyALU 381>; 382 383def MOV_IMM_I32 : MOV_IMM<i32, i32imm>; 384def : Pat < 385 (imm:$val), 386 (MOV_IMM_I32 (i32 ALU_LITERAL_X), imm:$val) 387>; 388 389def MOV_IMM_F32 : MOV_IMM<f32, f32imm>; 390def : Pat < 391 (fpimm:$val), 392 (MOV_IMM_F32 (i32 ALU_LITERAL_X), fpimm:$val) 393>; 394 395def KILLGT : InstR600 <0x2D, 396 (outs R600_Reg32:$dst), 397 (ins R600_Reg32:$src0, R600_Reg32:$src1, i32imm:$flags, R600_Pred:$p, 398 variable_ops), 399 "KILLGT $dst, $src0, $src1, $flags ($p)", 400 [], 401 NullALU>{ 402 let FlagOperandIdx = 3; 403} 404 405def AND_INT : R600_2OP < 406 0x30, "AND_INT", 407 [(set R600_Reg32:$dst, (and R600_Reg32:$src0, R600_Reg32:$src1))] 408>; 409 410def OR_INT : R600_2OP < 411 0x31, "OR_INT", 412 [(set R600_Reg32:$dst, (or R600_Reg32:$src0, R600_Reg32:$src1))] 413>; 414 415def XOR_INT : R600_2OP < 416 0x32, "XOR_INT", 417 [(set R600_Reg32:$dst, (xor R600_Reg32:$src0, R600_Reg32:$src1))] 418>; 419 420def NOT_INT : R600_1OP < 421 0x33, "NOT_INT", 422 [(set R600_Reg32:$dst, (not R600_Reg32:$src))] 423>; 424 425def ADD_INT : R600_2OP < 426 0x34, "ADD_INT", 427 [(set R600_Reg32:$dst, (add R600_Reg32:$src0, R600_Reg32:$src1))] 428>; 429 430def SUB_INT : R600_2OP < 431 0x35, "SUB_INT", 432 [(set R600_Reg32:$dst, (sub R600_Reg32:$src0, R600_Reg32:$src1))] 433>; 434 435def MAX_INT : R600_2OP < 436 0x36, "MAX_INT", 437 [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]>; 438 439def MIN_INT : R600_2OP < 440 0x37, "MIN_INT", 441 [(set R600_Reg32:$dst, (AMDGPUsmin R600_Reg32:$src0, R600_Reg32:$src1))]>; 442 443def MAX_UINT : R600_2OP < 444 0x38, "MAX_UINT", 445 [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))] 446>; 447 448def MIN_UINT : R600_2OP < 449 0x39, "MIN_UINT", 450 [(set R600_Reg32:$dst, (AMDGPUumin R600_Reg32:$src0, R600_Reg32:$src1))] 451>; 452 453def SETE_INT : R600_2OP < 454 0x3A, "SETE_INT", 455 [(set (i32 R600_Reg32:$dst), 456 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))] 457>; 458 459def SETGT_INT : R600_2OP < 460 0x3B, "SGT_INT", 461 [(set (i32 R600_Reg32:$dst), 462 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGT))] 463>; 464 465def SETGE_INT : R600_2OP < 466 0x3C, "SETGE_INT", 467 [(set (i32 R600_Reg32:$dst), 468 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))] 469>; 470 471def SETNE_INT : R600_2OP < 472 0x3D, "SETNE_INT", 473 [(set (i32 R600_Reg32:$dst), 474 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))] 475>; 476 477def SETGT_UINT : R600_2OP < 478 0x3E, "SETGT_UINT", 479 [(set (i32 R600_Reg32:$dst), 480 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))] 481>; 482 483def SETGE_UINT : R600_2OP < 484 0x3F, "SETGE_UINT", 485 [(set (i32 R600_Reg32:$dst), 486 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))] 487>; 488 489def CNDE_INT : R600_3OP < 490 0x1C, "CNDE_INT", 491 [(set (i32 R600_Reg32:$dst), 492 (select R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))] 493>; 494 495/* Texture instructions */ 496 497 498def TEX_LD : R600_TEX < 499 0x03, "TEX_LD", 500 [(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2, imm:$src3, imm:$src4, imm:$src5))] 501> { 502let AsmString = "TEX_LD $dst, $src0, $src1, $src2, $src3, $src4, $src5"; 503let InOperandList = (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5); 504} 505 506def TEX_GET_TEXTURE_RESINFO : R600_TEX < 507 0x04, "TEX_GET_TEXTURE_RESINFO", 508 [(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$src1, imm:$src2))] 509>; 510 511def TEX_GET_GRADIENTS_H : R600_TEX < 512 0x07, "TEX_GET_GRADIENTS_H", 513 [(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$src1, imm:$src2))] 514>; 515 516def TEX_GET_GRADIENTS_V : R600_TEX < 517 0x08, "TEX_GET_GRADIENTS_V", 518 [(set R600_Reg128:$dst, (int_AMDGPU_ddy R600_Reg128:$src0, imm:$src1, imm:$src2))] 519>; 520 521def TEX_SET_GRADIENTS_H : R600_TEX < 522 0x0B, "TEX_SET_GRADIENTS_H", 523 [] 524>; 525 526def TEX_SET_GRADIENTS_V : R600_TEX < 527 0x0C, "TEX_SET_GRADIENTS_V", 528 [] 529>; 530 531def TEX_SAMPLE : R600_TEX < 532 0x10, "TEX_SAMPLE", 533 [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, imm:$src2))] 534>; 535 536def TEX_SAMPLE_C : R600_TEX < 537 0x18, "TEX_SAMPLE_C", 538 [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))] 539>; 540 541def TEX_SAMPLE_L : R600_TEX < 542 0x11, "TEX_SAMPLE_L", 543 [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, imm:$src2))] 544>; 545 546def TEX_SAMPLE_C_L : R600_TEX < 547 0x19, "TEX_SAMPLE_C_L", 548 [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))] 549>; 550 551def TEX_SAMPLE_LB : R600_TEX < 552 0x12, "TEX_SAMPLE_LB", 553 [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, imm:$src2))] 554>; 555 556def TEX_SAMPLE_C_LB : R600_TEX < 557 0x1A, "TEX_SAMPLE_C_LB", 558 [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))] 559>; 560 561def TEX_SAMPLE_G : R600_TEX < 562 0x14, "TEX_SAMPLE_G", 563 [] 564>; 565 566def TEX_SAMPLE_C_G : R600_TEX < 567 0x1C, "TEX_SAMPLE_C_G", 568 [] 569>; 570 571/* Helper classes for common instructions */ 572 573class MUL_LIT_Common <bits<32> inst> : R600_3OP < 574 inst, "MUL_LIT", 575 [] 576>; 577 578class MULADD_Common <bits<32> inst> : R600_3OP < 579 inst, "MULADD", 580 [(set (f32 R600_Reg32:$dst), 581 (IL_mad R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))] 582>; 583 584class CNDE_Common <bits<32> inst> : R600_3OP < 585 inst, "CNDE", 586 [(set (f32 R600_Reg32:$dst), 587 (select (i32 (fp_to_sint (fneg R600_Reg32:$src0))), (f32 R600_Reg32:$src2), (f32 R600_Reg32:$src1)))] 588>; 589 590class CNDGT_Common <bits<32> inst> : R600_3OP < 591 inst, "CNDGT", 592 [] 593>; 594 595class CNDGE_Common <bits<32> inst> : R600_3OP < 596 inst, "CNDGE", 597 [(set R600_Reg32:$dst, (int_AMDGPU_cndlt R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))] 598>; 599 600class DOT4_Common <bits<32> inst> : R600_REDUCTION < 601 inst, 602 (ins R600_Reg128:$src0, R600_Reg128:$src1, i32imm:$flags), 603 "DOT4 $dst $src0, $src1", 604 [] 605 > { 606 let FlagOperandIdx = 3; 607} 608 609class DOT4_Pat <Instruction dot4> : Pat < 610 (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1), 611 (dot4 R600_Reg128:$src0, R600_Reg128:$src1, 0) 612>; 613 614multiclass CUBE_Common <bits<32> inst> { 615 616 def _pseudo : InstR600 < 617 inst, 618 (outs R600_Reg128:$dst), 619 (ins R600_Reg128:$src), 620 "CUBE $dst $src", 621 [(set R600_Reg128:$dst, (int_AMDGPU_cube R600_Reg128:$src))], 622 VecALU 623 >; 624 625 def _real : InstR600 < 626 inst, 627 (outs R600_Reg32:$dst), 628 (ins R600_Reg32:$src0, R600_Reg32:$src1, i32imm:$flags), 629 "CUBE $dst, $src0, $src1", 630 [], VecALU 631 >{ 632 let FlagOperandIdx = 3; 633 } 634} 635 636class EXP_IEEE_Common <bits<32> inst> : R600_1OP < 637 inst, "EXP_IEEE", 638 [(set R600_Reg32:$dst, (fexp2 R600_Reg32:$src))] 639>; 640 641class FLT_TO_INT_Common <bits<32> inst> : R600_1OP < 642 inst, "FLT_TO_INT", 643 [(set R600_Reg32:$dst, (fp_to_sint R600_Reg32:$src))] 644>; 645 646class INT_TO_FLT_Common <bits<32> inst> : R600_1OP < 647 inst, "INT_TO_FLT", 648 [(set R600_Reg32:$dst, (sint_to_fp R600_Reg32:$src))] 649>; 650 651class FLT_TO_UINT_Common <bits<32> inst> : R600_1OP < 652 inst, "FLT_TO_UINT", 653 [(set R600_Reg32:$dst, (fp_to_uint R600_Reg32:$src))] 654>; 655 656class UINT_TO_FLT_Common <bits<32> inst> : R600_1OP < 657 inst, "UINT_TO_FLT", 658 [(set R600_Reg32:$dst, (uint_to_fp R600_Reg32:$src))] 659>; 660 661class LOG_CLAMPED_Common <bits<32> inst> : R600_1OP < 662 inst, "LOG_CLAMPED", 663 [] 664>; 665 666class LOG_IEEE_Common <bits<32> inst> : R600_1OP < 667 inst, "LOG_IEEE", 668 [(set R600_Reg32:$dst, (int_AMDIL_log R600_Reg32:$src))] 669>; 670 671class LSHL_Common <bits<32> inst> : R600_2OP < 672 inst, "LSHL $dst, $src0, $src1", 673 [(set R600_Reg32:$dst, (shl R600_Reg32:$src0, R600_Reg32:$src1))] 674>; 675 676class LSHR_Common <bits<32> inst> : R600_2OP < 677 inst, "LSHR $dst, $src0, $src1", 678 [(set R600_Reg32:$dst, (srl R600_Reg32:$src0, R600_Reg32:$src1))] 679>; 680 681class ASHR_Common <bits<32> inst> : R600_2OP < 682 inst, "ASHR $dst, $src0, $src1", 683 [(set R600_Reg32:$dst, (sra R600_Reg32:$src0, R600_Reg32:$src1))] 684>; 685 686class MULHI_INT_Common <bits<32> inst> : R600_2OP < 687 inst, "MULHI_INT $dst, $src0, $src1", 688 [(set R600_Reg32:$dst, (mulhs R600_Reg32:$src0, R600_Reg32:$src1))] 689>; 690 691class MULHI_UINT_Common <bits<32> inst> : R600_2OP < 692 inst, "MULHI $dst, $src0, $src1", 693 [(set R600_Reg32:$dst, (mulhu R600_Reg32:$src0, R600_Reg32:$src1))] 694>; 695 696class MULLO_INT_Common <bits<32> inst> : R600_2OP < 697 inst, "MULLO_INT $dst, $src0, $src1", 698 [(set R600_Reg32:$dst, (mul R600_Reg32:$src0, R600_Reg32:$src1))] 699>; 700 701class MULLO_UINT_Common <bits<32> inst> : R600_2OP < 702 inst, "MULLO_UINT $dst, $src0, $src1", 703 [] 704>; 705 706class RECIP_CLAMPED_Common <bits<32> inst> : R600_1OP < 707 inst, "RECIP_CLAMPED", 708 [] 709>; 710 711class RECIP_IEEE_Common <bits<32> inst> : R600_1OP < 712 inst, "RECIP_IEEE", 713 [(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))] 714>; 715 716class RECIP_UINT_Common <bits<32> inst> : R600_1OP < 717 inst, "RECIP_INT $dst, $src", 718 [(set R600_Reg32:$dst, (AMDGPUurecip R600_Reg32:$src))] 719>; 720 721class RECIPSQRT_CLAMPED_Common <bits<32> inst> : R600_1OP < 722 inst, "RECIPSQRT_CLAMPED", 723 [(set R600_Reg32:$dst, (int_AMDGPU_rsq R600_Reg32:$src))] 724>; 725 726class RECIPSQRT_IEEE_Common <bits<32> inst> : R600_1OP < 727 inst, "RECIPSQRT_IEEE", 728 [] 729>; 730 731class SIN_Common <bits<32> inst> : R600_1OP < 732 inst, "SIN", []>{ 733 let Trig = 1; 734} 735 736class COS_Common <bits<32> inst> : R600_1OP < 737 inst, "COS", []> { 738 let Trig = 1; 739} 740 741/* Helper patterns for complex intrinsics */ 742/* -------------------------------------- */ 743 744class DIV_Common <InstR600 recip_ieee> : Pat< 745 (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1), 746 (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1)) 747>; 748 749class SSG_Common <InstR600 cndgt, InstR600 cndge> : Pat < 750 (int_AMDGPU_ssg R600_Reg32:$src), 751 (cndgt R600_Reg32:$src, (f32 ONE), (cndge R600_Reg32:$src, (f32 ZERO), (f32 NEG_ONE))) 752>; 753 754class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> : Pat < 755 (int_TGSI_lit_z R600_Reg32:$src_x, R600_Reg32:$src_y, R600_Reg32:$src_w), 756 (exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x)) 757>; 758 759/* ---------------------- */ 760/* R600 / R700 Only Instructions */ 761/* ---------------------- */ 762 763let Predicates = [isR600] in { 764 765 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>; 766 def MULADD_r600 : MULADD_Common<0x10>; 767 def CNDE_r600 : CNDE_Common<0x18>; 768 def CNDGT_r600 : CNDGT_Common<0x19>; 769 def CNDGE_r600 : CNDGE_Common<0x1A>; 770 def DOT4_r600 : DOT4_Common<0x50>; 771 def : DOT4_Pat <DOT4_r600>; 772 defm CUBE_r600 : CUBE_Common<0x52>; 773 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>; 774 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>; 775 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>; 776 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>; 777 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>; 778 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>; 779 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>; 780 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>; 781 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>; 782 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>; 783 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>; 784 def SIN_r600 : SIN_Common<0x6E>; 785 def COS_r600 : COS_Common<0x6F>; 786 def ASHR_r600 : ASHR_Common<0x70>; 787 def LSHR_r600 : LSHR_Common<0x71>; 788 def LSHL_r600 : LSHL_Common<0x72>; 789 def MULLO_INT_r600 : MULLO_INT_Common<0x73>; 790 def MULHI_INT_r600 : MULHI_INT_Common<0x74>; 791 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>; 792 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>; 793 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>; 794 795 def DIV_r600 : DIV_Common<RECIP_IEEE_r600>; 796 def POW_r600 : POW_Common<LOG_IEEE_r600, EXP_IEEE_r600, MUL, GPRF32>; 797 def SSG_r600 : SSG_Common<CNDGT_r600, CNDGE_r600>; 798 def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>; 799 800} 801 802// Helper pattern for normalizing inputs to triginomic instructions for R700+ 803// cards. 804class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat< 805 (intr R600_Reg32:$src), 806 (trig (MUL (MOV_IMM_I32 (i32 ALU_LITERAL_X), CONST.TWO_PI_INV), R600_Reg32:$src)) 807>; 808 809//===----------------------------------------------------------------------===// 810// R700 Only instructions 811//===----------------------------------------------------------------------===// 812 813let Predicates = [isR700] in { 814 def SIN_r700 : SIN_Common<0x6E>; 815 def COS_r700 : COS_Common<0x6F>; 816 817 // R700 normalizes inputs to SIN/COS the same as EG 818 def : TRIG_eg <SIN_r700, int_AMDGPU_sin>; 819 def : TRIG_eg <COS_r700, int_AMDGPU_cos>; 820} 821 822//===----------------------------------------------------------------------===// 823// Evergreen Only instructions 824//===----------------------------------------------------------------------===// 825 826let Predicates = [isEG] in { 827 828def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>; 829 830def MULLO_INT_eg : MULLO_INT_Common<0x8F>; 831def MULHI_INT_eg : MULHI_INT_Common<0x90>; 832def MULLO_UINT_eg : MULLO_UINT_Common<0x91>; 833def MULHI_UINT_eg : MULHI_UINT_Common<0x92>; 834def RECIP_UINT_eg : RECIP_UINT_Common<0x94>; 835 836} // End Predicates = [isEG] 837 838/* ------------------------------- */ 839/* Evergreen / Cayman Instructions */ 840/* ------------------------------- */ 841 842let Predicates = [isEGorCayman] in { 843 844 // BFE_UINT - bit_extract, an optimization for mask and shift 845 // Src0 = Input 846 // Src1 = Offset 847 // Src2 = Width 848 // 849 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width) 850 // 851 // Example Usage: 852 // (Offset, Width) 853 // 854 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0 855 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8 856 // (16,8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16 857 // (24,8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24 858 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT", 859 [(set R600_Reg32:$dst, (int_AMDIL_bit_extract_u32 R600_Reg32:$src0, 860 R600_Reg32:$src1, 861 R600_Reg32:$src2))], 862 VecALU 863 >; 864 865 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", 866 [(set R600_Reg32:$dst, (AMDGPUbitalign R600_Reg32:$src0, R600_Reg32:$src1, 867 R600_Reg32:$src2))], 868 VecALU 869 >; 870 871 def MULADD_eg : MULADD_Common<0x14>; 872 def ASHR_eg : ASHR_Common<0x15>; 873 def LSHR_eg : LSHR_Common<0x16>; 874 def LSHL_eg : LSHL_Common<0x17>; 875 def CNDE_eg : CNDE_Common<0x19>; 876 def CNDGT_eg : CNDGT_Common<0x1A>; 877 def CNDGE_eg : CNDGE_Common<0x1B>; 878 def MUL_LIT_eg : MUL_LIT_Common<0x1F>; 879 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>; 880 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>; 881 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>; 882 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>; 883 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>; 884 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>; 885 def SIN_eg : SIN_Common<0x8D>; 886 def COS_eg : COS_Common<0x8E>; 887 def DOT4_eg : DOT4_Common<0xBE>; 888 def : DOT4_Pat <DOT4_eg>; 889 defm CUBE_eg : CUBE_Common<0xC0>; 890 891 def DIV_eg : DIV_Common<RECIP_IEEE_eg>; 892 def POW_eg : POW_Common<LOG_IEEE_eg, EXP_IEEE_eg, MUL, GPRF32>; 893 def SSG_eg : SSG_Common<CNDGT_eg, CNDGE_eg>; 894 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>; 895 896 def : TRIG_eg <SIN_eg, int_AMDGPU_sin>; 897 def : TRIG_eg <COS_eg, int_AMDGPU_cos>; 898 899 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> { 900 let Pattern = []; 901 } 902 903 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>; 904 905 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> { 906 let Pattern = []; 907 } 908 909 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>; 910 911 def : Pat<(fp_to_sint R600_Reg32:$src), 912 (FLT_TO_INT_eg (TRUNC R600_Reg32:$src))>; 913 914 def : Pat<(fp_to_uint R600_Reg32:$src), 915 (FLT_TO_UINT_eg (TRUNC R600_Reg32:$src))>; 916 917//===----------------------------------------------------------------------===// 918// Memory read/write instructions 919//===----------------------------------------------------------------------===// 920 921let usesCustomInserter = 1 in { 922 923def RAT_WRITE_CACHELESS_eg : EG_CF_RAT <0x57, 0x2, 0, (outs), 924 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr), 925 "RAT_WRITE_CACHELESS_eg $rw_gpr, $index_gpr", 926 [(global_store (i32 R600_TReg32_X:$rw_gpr), R600_TReg32_X:$index_gpr)]> 927{ 928 let RIM = 0; 929 /* XXX: Have a separate instruction for non-indexed writes. */ 930 let TYPE = 1; 931 let RW_REL = 0; 932 let ELEM_SIZE = 0; 933 934 let ARRAY_SIZE = 0; 935 let COMP_MASK = 1; 936 let BURST_COUNT = 0; 937 let VPM = 0; 938 let EOP = 0; 939 let MARK = 0; 940 let BARRIER = 1; 941} 942 943} // End usesCustomInserter = 1 944 945// Floating point global_store 946def : Pat < 947 (global_store (f32 R600_TReg32_X:$val), R600_TReg32_X:$ptr), 948 (RAT_WRITE_CACHELESS_eg R600_TReg32_X:$val, R600_TReg32_X:$ptr) 949>; 950 951class VTX_READ_eg <bits<8> buffer_id, dag outs, list<dag> pattern> 952 : InstR600ISA <outs, (ins MEMxi:$ptr), "VTX_READ_eg $dst, $ptr", pattern> { 953 954 // Operands 955 bits<7> DST_GPR; 956 bits<7> SRC_GPR; 957 958 // Static fields 959 bits<5> VC_INST = 0; 960 bits<2> FETCH_TYPE = 2; 961 bits<1> FETCH_WHOLE_QUAD = 0; 962 bits<8> BUFFER_ID = buffer_id; 963 bits<1> SRC_REL = 0; 964 // XXX: We can infer this field based on the SRC_GPR. This would allow us 965 // to store vertex addresses in any channel, not just X. 966 bits<2> SRC_SEL_X = 0; 967 bits<6> MEGA_FETCH_COUNT; 968 bits<1> DST_REL = 0; 969 bits<3> DST_SEL_X; 970 bits<3> DST_SEL_Y; 971 bits<3> DST_SEL_Z; 972 bits<3> DST_SEL_W; 973 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL, 974 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored, 975 // however, based on my testing if USE_CONST_FIELDS is set, then all 976 // these fields need to be set to 0. 977 bits<1> USE_CONST_FIELDS = 0; 978 bits<6> DATA_FORMAT; 979 bits<2> NUM_FORMAT_ALL = 1; 980 bits<1> FORMAT_COMP_ALL = 0; 981 bits<1> SRF_MODE_ALL = 0; 982 983 // LLVM can only encode 64-bit instructions, so these fields are manually 984 // encoded in R600CodeEmitter 985 // 986 // bits<16> OFFSET; 987 // bits<2> ENDIAN_SWAP = 0; 988 // bits<1> CONST_BUF_NO_STRIDE = 0; 989 // bits<1> MEGA_FETCH = 0; 990 // bits<1> ALT_CONST = 0; 991 // bits<2> BUFFER_INDEX_MODE = 0; 992 993 // VTX_WORD0 994 let Inst{4-0} = VC_INST; 995 let Inst{6-5} = FETCH_TYPE; 996 let Inst{7} = FETCH_WHOLE_QUAD; 997 let Inst{15-8} = BUFFER_ID; 998 let Inst{22-16} = SRC_GPR; 999 let Inst{23} = SRC_REL; 1000 let Inst{25-24} = SRC_SEL_X; 1001 let Inst{31-26} = MEGA_FETCH_COUNT; 1002 1003 // VTX_WORD1_GPR 1004 let Inst{38-32} = DST_GPR; 1005 let Inst{39} = DST_REL; 1006 let Inst{40} = 0; // Reserved 1007 let Inst{43-41} = DST_SEL_X; 1008 let Inst{46-44} = DST_SEL_Y; 1009 let Inst{49-47} = DST_SEL_Z; 1010 let Inst{52-50} = DST_SEL_W; 1011 let Inst{53} = USE_CONST_FIELDS; 1012 let Inst{59-54} = DATA_FORMAT; 1013 let Inst{61-60} = NUM_FORMAT_ALL; 1014 let Inst{62} = FORMAT_COMP_ALL; 1015 let Inst{63} = SRF_MODE_ALL; 1016 1017 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding 1018 // is done in R600CodeEmitter 1019 // 1020 // Inst{79-64} = OFFSET; 1021 // Inst{81-80} = ENDIAN_SWAP; 1022 // Inst{82} = CONST_BUF_NO_STRIDE; 1023 // Inst{83} = MEGA_FETCH; 1024 // Inst{84} = ALT_CONST; 1025 // Inst{86-85} = BUFFER_INDEX_MODE; 1026 // Inst{95-86} = 0; Reserved 1027 1028 // VTX_WORD3 (Padding) 1029 // 1030 // Inst{127-96} = 0; 1031} 1032 1033class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern> 1034 : VTX_READ_eg <buffer_id, (outs R600_TReg32_X:$dst), pattern> { 1035 1036 let MEGA_FETCH_COUNT = 4; 1037 let DST_SEL_X = 0; 1038 let DST_SEL_Y = 7; // Masked 1039 let DST_SEL_Z = 7; // Masked 1040 let DST_SEL_W = 7; // Masked 1041 let DATA_FORMAT = 0xD; // COLOR_32 1042 1043 // This is not really necessary, but there were some GPU hangs that appeared 1044 // to be caused by ALU instructions in the next instruction group that wrote 1045 // to the $ptr registers of the VTX_READ. 1046 // e.g. 1047 // %T3_X<def> = VTX_READ_PARAM_i32_eg %T2_X<kill>, 24 1048 // %T2_X<def> = MOV %ZERO 1049 //Adding this constraint prevents this from happening. 1050 let Constraints = "$ptr.ptr = $dst"; 1051} 1052 1053class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern> 1054 : VTX_READ_eg <buffer_id, (outs R600_Reg128:$dst), pattern> { 1055 1056 let MEGA_FETCH_COUNT = 16; 1057 let DST_SEL_X = 0; 1058 let DST_SEL_Y = 1; 1059 let DST_SEL_Z = 2; 1060 let DST_SEL_W = 3; 1061 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32 1062 1063 // XXX: Need to force VTX_READ_128 instructions to write to the same register 1064 // that holds its buffer address to avoid potential hangs. We can't use 1065 // the same constraint as VTX_READ_32_eg, because the $ptr.ptr and $dst 1066 // registers are different sizes. 1067} 1068 1069//===----------------------------------------------------------------------===// 1070// VTX Read from parameter memory space 1071//===----------------------------------------------------------------------===// 1072 1073class VTX_READ_PARAM_32_eg <ValueType vt> : VTX_READ_32_eg <0, 1074 [(set (vt R600_TReg32_X:$dst), (load_param ADDRVTX_READ:$ptr))] 1075>; 1076 1077def VTX_READ_PARAM_i32_eg : VTX_READ_PARAM_32_eg<i32>; 1078def VTX_READ_PARAM_f32_eg : VTX_READ_PARAM_32_eg<f32>; 1079 1080 1081//===----------------------------------------------------------------------===// 1082// VTX Read from global memory space 1083//===----------------------------------------------------------------------===// 1084 1085// 32-bit reads 1086 1087class VTX_READ_GLOBAL_eg <ValueType vt> : VTX_READ_32_eg <1, 1088 [(set (vt R600_TReg32_X:$dst), (global_load ADDRVTX_READ:$ptr))] 1089>; 1090 1091def VTX_READ_GLOBAL_i32_eg : VTX_READ_GLOBAL_eg<i32>; 1092def VTX_READ_GLOBAL_f32_eg : VTX_READ_GLOBAL_eg<f32>; 1093 1094// 128-bit reads 1095 1096class VTX_READ_GLOBAL_128_eg <ValueType vt> : VTX_READ_128_eg <1, 1097 [(set (vt R600_Reg128:$dst), (global_load ADDRVTX_READ:$ptr))] 1098>; 1099 1100def VTX_READ_GLOBAL_v4i32_eg : VTX_READ_GLOBAL_128_eg<v4i32>; 1101def VTX_READ_GLOBAL_v4f32_eg : VTX_READ_GLOBAL_128_eg<v4f32>; 1102 1103} 1104 1105let Predicates = [isCayman] in { 1106 1107let isVector = 1 in { 1108 1109def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>; 1110 1111def MULLO_INT_cm : MULLO_INT_Common<0x8F>; 1112def MULHI_INT_cm : MULHI_INT_Common<0x90>; 1113def MULLO_UINT_cm : MULLO_UINT_Common<0x91>; 1114def MULHI_UINT_cm : MULHI_UINT_Common<0x92>; 1115 1116} // End isVector = 1 1117 1118// RECIP_UINT emulation for Cayman 1119def : Pat < 1120 (AMDGPUurecip R600_Reg32:$src0), 1121 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg R600_Reg32:$src0)), 1122 (MOV_IMM_I32 (i32 ALU_LITERAL_X), 0x4f800000))) 1123>; 1124 1125} // End isCayman 1126 1127/* Other Instructions */ 1128 1129let isCodeGenOnly = 1 in { 1130/* 1131 def SWIZZLE : AMDGPUShaderInst < 1132 (outs GPRV4F32:$dst), 1133 (ins GPRV4F32:$src0, i32imm:$src1), 1134 "SWIZZLE $dst, $src0, $src1", 1135 [(set GPRV4F32:$dst, (int_AMDGPU_swizzle GPRV4F32:$src0, imm:$src1))] 1136 >; 1137*/ 1138 1139 def LAST : AMDGPUShaderInst < 1140 (outs), 1141 (ins), 1142 "LAST", 1143 [] 1144 >; 1145 1146 def GET_CHAN : AMDGPUShaderInst < 1147 (outs R600_Reg32:$dst), 1148 (ins R600_Reg128:$src0, i32imm:$src1), 1149 "GET_CHAN $dst, $src0, $src1", 1150 [] 1151 >; 1152 1153 def MULLIT : AMDGPUShaderInst < 1154 (outs R600_Reg128:$dst), 1155 (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2), 1156 "MULLIT $dst, $src0, $src1", 1157 [(set R600_Reg128:$dst, (int_AMDGPU_mullit R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))] 1158 >; 1159 1160let usesCustomInserter = 1, isPseudo = 1 in { 1161 1162class R600PreloadInst <string asm, Intrinsic intr> : AMDGPUInst < 1163 (outs R600_TReg32:$dst), 1164 (ins), 1165 asm, 1166 [(set R600_TReg32:$dst, (intr))] 1167>; 1168 1169def R600_LOAD_CONST : AMDGPUShaderInst < 1170 (outs R600_Reg32:$dst), 1171 (ins i32imm:$src0), 1172 "R600_LOAD_CONST $dst, $src0", 1173 [(set R600_Reg32:$dst, (int_AMDGPU_load_const imm:$src0))] 1174>; 1175 1176def RESERVE_REG : AMDGPUShaderInst < 1177 (outs), 1178 (ins i32imm:$src), 1179 "RESERVE_REG $src", 1180 [(int_AMDGPU_reserve_reg imm:$src)] 1181>; 1182 1183def TXD: AMDGPUShaderInst < 1184 (outs R600_Reg128:$dst), 1185 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4), 1186 "TXD $dst, $src0, $src1, $src2, $src3, $src4", 1187 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, imm:$src4))] 1188>; 1189 1190def TXD_SHADOW: AMDGPUShaderInst < 1191 (outs R600_Reg128:$dst), 1192 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4), 1193 "TXD_SHADOW $dst, $src0, $src1, $src2, $src3, $src4", 1194 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, TEX_SHADOW:$src4))] 1195>; 1196 1197} // End usesCustomInserter = 1, isPseudo = 1 1198 1199} // End isCodeGenOnly = 1 1200 1201def CLAMP_R600 : CLAMP <R600_Reg32>; 1202def FABS_R600 : FABS<R600_Reg32>; 1203def FNEG_R600 : FNEG<R600_Reg32>; 1204 1205let usesCustomInserter = 1 in { 1206 1207def MASK_WRITE : AMDGPUShaderInst < 1208 (outs), 1209 (ins R600_Reg32:$src), 1210 "MASK_WRITE $src", 1211 [] 1212>; 1213 1214} // End usesCustomInserter = 1 1215 1216//===----------------------------------------------------------------------===// 1217// ISel Patterns 1218//===----------------------------------------------------------------------===// 1219 1220// KIL Patterns 1221def KILP : Pat < 1222 (int_AMDGPU_kilp), 1223 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO), 0)) 1224>; 1225 1226def KIL : Pat < 1227 (int_AMDGPU_kill R600_Reg32:$src0), 1228 (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0), 0)) 1229>; 1230 1231// SGT Reverse args 1232def : Pat < 1233 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LT), 1234 (SGT R600_Reg32:$src1, R600_Reg32:$src0) 1235>; 1236 1237// SGE Reverse args 1238def : Pat < 1239 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LE), 1240 (SGE R600_Reg32:$src1, R600_Reg32:$src0) 1241>; 1242 1243// SETGT_INT reverse args 1244def : Pat < 1245 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLT), 1246 (SETGT_INT R600_Reg32:$src1, R600_Reg32:$src0) 1247>; 1248 1249// SETGE_INT reverse args 1250def : Pat < 1251 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLE), 1252 (SETGE_INT R600_Reg32:$src1, R600_Reg32:$src0) 1253>; 1254 1255// SETGT_UINT reverse args 1256def : Pat < 1257 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULT), 1258 (SETGT_UINT R600_Reg32:$src1, R600_Reg32:$src0) 1259>; 1260 1261// SETGE_UINT reverse args 1262def : Pat < 1263 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULE), 1264 (SETGE_UINT R600_Reg32:$src0, R600_Reg32:$src1) 1265>; 1266 1267// The next two patterns are special cases for handling 'true if ordered' and 1268// 'true if unordered' conditionals. The assumption here is that the behavior of 1269// SETE and SNE conforms to the Direct3D 10 rules for floating point values 1270// described here: 1271// http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit 1272// We assume that SETE returns false when one of the operands is NAN and 1273// SNE returns true when on of the operands is NAN 1274 1275//SETE - 'true if ordered' 1276def : Pat < 1277 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETO), 1278 (SETE R600_Reg32:$src0, R600_Reg32:$src1) 1279>; 1280 1281//SNE - 'true if unordered' 1282def : Pat < 1283 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETUO), 1284 (SNE R600_Reg32:$src0, R600_Reg32:$src1) 1285>; 1286 1287def : Extract_Element <f32, v4f32, R600_Reg128, 0, sel_x>; 1288def : Extract_Element <f32, v4f32, R600_Reg128, 1, sel_y>; 1289def : Extract_Element <f32, v4f32, R600_Reg128, 2, sel_z>; 1290def : Extract_Element <f32, v4f32, R600_Reg128, 3, sel_w>; 1291 1292def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 4, sel_x>; 1293def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 5, sel_y>; 1294def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 6, sel_z>; 1295def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 7, sel_w>; 1296 1297def : Extract_Element <i32, v4i32, R600_Reg128, 0, sel_x>; 1298def : Extract_Element <i32, v4i32, R600_Reg128, 1, sel_y>; 1299def : Extract_Element <i32, v4i32, R600_Reg128, 2, sel_z>; 1300def : Extract_Element <i32, v4i32, R600_Reg128, 3, sel_w>; 1301 1302def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 4, sel_x>; 1303def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 5, sel_y>; 1304def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 6, sel_z>; 1305def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 7, sel_w>; 1306 1307def : Vector_Build <v4f32, R600_Reg32>; 1308def : Vector_Build <v4i32, R600_Reg32>; 1309 1310// bitconvert patterns 1311 1312def : BitConvert <i32, f32, R600_Reg32>; 1313def : BitConvert <f32, i32, R600_Reg32>; 1314def : BitConvert <v4f32, v4i32, R600_Reg128>; 1315 1316} // End isR600toCayman Predicate 1317