R600RegisterInfo.cpp revision a75c6163e605f35b14f26930dd9227e4f337ec9e 
1//===-- R600RegisterInfo.cpp - TODO: Add brief description -------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// TODO: Add full description
11//
12//===----------------------------------------------------------------------===//
13
14#include "R600RegisterInfo.h"
15#include "AMDGPUTargetMachine.h"
16
17using namespace llvm;
18
19R600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm,
20    const TargetInstrInfo &tii)
21: AMDGPURegisterInfo(tm, tii),
22  TM(tm),
23  TII(tii)
24  { }
25
26BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const
27{
28  BitVector Reserved(getNumRegs());
29  Reserved.set(AMDIL::ZERO);
30  Reserved.set(AMDIL::HALF);
31  Reserved.set(AMDIL::ONE);
32  Reserved.set(AMDIL::ONE_INT);
33  Reserved.set(AMDIL::NEG_HALF);
34  Reserved.set(AMDIL::NEG_ONE);
35  Reserved.set(AMDIL::PV_X);
36  Reserved.set(AMDIL::ALU_LITERAL_X);
37
38  for (TargetRegisterClass::iterator I = AMDIL::R600_CReg32RegClass.begin(),
39                        E = AMDIL::R600_CReg32RegClass.end(); I != E; ++I) {
40    Reserved.set(*I);
41  }
42
43  for (MachineFunction::const_iterator BB = MF.begin(),
44                                 BB_E = MF.end(); BB != BB_E; ++BB) {
45    const MachineBasicBlock &MBB = *BB;
46    for (MachineBasicBlock::const_iterator I = MBB.begin(), E = MBB.end();
47                                                                  I != E; ++I) {
48      const MachineInstr &MI = *I;
49      if (MI.getOpcode() == AMDIL::RESERVE_REG) {
50        if (!TargetRegisterInfo::isVirtualRegister(MI.getOperand(0).getReg())) {
51          Reserved.set(MI.getOperand(0).getReg());
52        }
53      }
54    }
55  }
56  return Reserved;
57}
58
59const TargetRegisterClass *
60R600RegisterInfo::getISARegClass(const TargetRegisterClass * rc) const
61{
62  switch (rc->getID()) {
63  case AMDIL::GPRV4F32RegClassID:
64  case AMDIL::GPRV4I32RegClassID:
65    return &AMDIL::R600_Reg128RegClass;
66  case AMDIL::GPRF32RegClassID:
67  case AMDIL::GPRI32RegClassID:
68    return &AMDIL::R600_Reg32RegClass;
69  default: return rc;
70  }
71}
72
73unsigned R600RegisterInfo::getHWRegIndex(unsigned reg) const
74{
75  switch(reg) {
76  case AMDIL::ZERO: return 248;
77  case AMDIL::ONE:
78  case AMDIL::NEG_ONE: return 249;
79  case AMDIL::ONE_INT: return 250;
80  case AMDIL::HALF:
81  case AMDIL::NEG_HALF: return 252;
82  case AMDIL::ALU_LITERAL_X: return 253;
83  default: return getHWRegIndexGen(reg);
84  }
85}
86
87unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const
88{
89  switch(reg) {
90  case AMDIL::ZERO:
91  case AMDIL::ONE:
92  case AMDIL::ONE_INT:
93  case AMDIL::NEG_ONE:
94  case AMDIL::HALF:
95  case AMDIL::NEG_HALF:
96  case AMDIL::ALU_LITERAL_X:
97    return 0;
98  default: return getHWRegChanGen(reg);
99  }
100}
101
102#include "R600HwRegInfo.include"
103