SIGenRegisterInfo.pl revision 16e42a5dd065c09f6d561537009639906b22ce45
1#===-- SIGenRegisterInfo.pl - Script for generating register info files ----===# 2# 3# The LLVM Compiler Infrastructure 4# 5# This file is distributed under the University of Illinois Open Source 6# License. See LICENSE.TXT for details. 7# 8#===------------------------------------------------------------------------===# 9# 10# This perl script prints to stdout .td code to be used as SIRegisterInfo.td 11# it also generates a file called SIHwRegInfo.include, which contains helper 12# functions for determining the hw encoding of registers. 13# 14#===------------------------------------------------------------------------===# 15 16use strict; 17use warnings; 18 19my $SGPR_COUNT = 104; 20my $VGPR_COUNT = 256; 21 22my $SGPR_MAX_IDX = $SGPR_COUNT - 1; 23my $VGPR_MAX_IDX = $VGPR_COUNT - 1; 24 25my $INDEX_FILE = defined($ARGV[0]) ? $ARGV[0] : ''; 26 27print <<STRING; 28 29let Namespace = "AMDGPU" in { 30 def low : SubRegIndex; 31 def high : SubRegIndex; 32 33 def sub0 : SubRegIndex; 34 def sub1 : SubRegIndex; 35 def sub2 : SubRegIndex; 36 def sub3 : SubRegIndex; 37 def sub4 : SubRegIndex; 38 def sub5 : SubRegIndex; 39 def sub6 : SubRegIndex; 40 def sub7 : SubRegIndex; 41} 42 43class SIReg <string n> : Register<n> { 44 let Namespace = "AMDGPU"; 45} 46 47class SI_64 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> { 48 let Namespace = "AMDGPU"; 49 let SubRegIndices = [low, high]; 50} 51 52class SI_128 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> { 53 let Namespace = "AMDGPU"; 54 let SubRegIndices = [sel_x, sel_y, sel_z, sel_w]; 55} 56 57class SI_256 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> { 58 let Namespace = "AMDGPU"; 59 let SubRegIndices = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7]; 60} 61 62class SGPR_32 <bits<8> num, string name> : SIReg<name> { 63 field bits<8> Num; 64 65 let Num = num; 66} 67 68 69class VGPR_32 <bits<9> num, string name> : SIReg<name> { 70 field bits<9> Num; 71 72 let Num = num; 73} 74 75class SGPR_64 <bits<8> num, string name, list<Register> subregs> : 76 SI_64 <name, subregs>; 77 78class VGPR_64 <bits<9> num, string name, list<Register> subregs> : 79 SI_64 <name, subregs>; 80 81class SGPR_128 <bits<8> num, string name, list<Register> subregs> : 82 SI_128 <name, subregs>; 83 84class VGPR_128 <bits<9> num, string name, list<Register> subregs> : 85 SI_128 <name, subregs>; 86 87class SGPR_256 <bits<8> num, string name, list<Register> subregs> : 88 SI_256 <name, subregs>; 89 90def VCC : SIReg<"VCC">; 91def EXEC : SIReg<"EXEC">; 92def SCC : SIReg<"SCC">; 93def SREG_LIT_0 : SIReg <"S LIT 0">; 94 95def M0 : SIReg <"M0">; 96 97//Interpolation registers 98 99def PERSP_SAMPLE_I : SIReg <"PERSP_SAMPLE_I">; 100def PERSP_SAMPLE_J : SIReg <"PERSP_SAMPLE_J">; 101def PERSP_CENTER_I : SIReg <"PERSP_CENTER_I">; 102def PERSP_CENTER_J : SIReg <"PERSP_CENTER_J">; 103def PERSP_CENTROID_I : SIReg <"PERSP_CENTROID_I">; 104def PERSP_CENTROID_J : SIReg <"PERP_CENTROID_J">; 105def PERSP_I_W : SIReg <"PERSP_I_W">; 106def PERSP_J_W : SIReg <"PERSP_J_W">; 107def PERSP_1_W : SIReg <"PERSP_1_W">; 108def LINEAR_SAMPLE_I : SIReg <"LINEAR_SAMPLE_I">; 109def LINEAR_SAMPLE_J : SIReg <"LINEAR_SAMPLE_J">; 110def LINEAR_CENTER_I : SIReg <"LINEAR_CENTER_I">; 111def LINEAR_CENTER_J : SIReg <"LINEAR_CENTER_J">; 112def LINEAR_CENTROID_I : SIReg <"LINEAR_CENTROID_I">; 113def LINEAR_CENTROID_J : SIReg <"LINEAR_CENTROID_J">; 114def LINE_STIPPLE_TEX_COORD : SIReg <"LINE_STIPPLE_TEX_COORD">; 115def POS_X_FLOAT : SIReg <"POS_X_FLOAT">; 116def POS_Y_FLOAT : SIReg <"POS_Y_FLOAT">; 117def POS_Z_FLOAT : SIReg <"POS_Z_FLOAT">; 118def POS_W_FLOAT : SIReg <"POS_W_FLOAT">; 119def FRONT_FACE : SIReg <"FRONT_FACE">; 120def ANCILLARY : SIReg <"ANCILLARY">; 121def SAMPLE_COVERAGE : SIReg <"SAMPLE_COVERAGE">; 122def POS_FIXED_PT : SIReg <"POS_FIXED_PT">; 123 124STRING 125 126#32 bit register 127 128my @SGPR; 129for (my $i = 0; $i < $SGPR_COUNT; $i++) { 130 print "def SGPR$i : SGPR_32 <$i, \"SGPR$i\">;\n"; 131 $SGPR[$i] = "SGPR$i"; 132} 133 134my @VGPR; 135for (my $i = 0; $i < $VGPR_COUNT; $i++) { 136 print "def VGPR$i : VGPR_32 <$i, \"VGPR$i\">;\n"; 137 $VGPR[$i] = "VGPR$i"; 138} 139 140print <<STRING; 141 142def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32, 143 (add (sequence "SGPR%u", 0, $SGPR_MAX_IDX), SREG_LIT_0, M0) 144>; 145 146def VReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32, 147 (add (sequence "VGPR%u", 0, $VGPR_MAX_IDX), 148 PERSP_SAMPLE_I, PERSP_SAMPLE_J, 149 PERSP_CENTER_I, PERSP_CENTER_J, 150 PERSP_CENTROID_I, PERSP_CENTROID_J, 151 PERSP_I_W, PERSP_J_W, PERSP_1_W, 152 LINEAR_SAMPLE_I, LINEAR_SAMPLE_J, 153 LINEAR_CENTER_I, LINEAR_CENTER_J, 154 LINEAR_CENTROID_I, LINEAR_CENTROID_J, 155 LINE_STIPPLE_TEX_COORD, 156 POS_X_FLOAT, 157 POS_Y_FLOAT, 158 POS_Z_FLOAT, 159 POS_W_FLOAT, 160 FRONT_FACE, 161 ANCILLARY, 162 SAMPLE_COVERAGE, 163 POS_FIXED_PT 164 ) 165>; 166 167def AllReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32, 168 (add VReg_32, SReg_32) 169>; 170 171def SCCReg : RegisterClass<"AMDGPU", [i1], 1, (add SCC)>; 172def VCCReg : RegisterClass<"AMDGPU", [i1], 1, (add VCC)>; 173def EXECReg : RegisterClass<"AMDGPU", [i1], 1, (add EXEC)>; 174 175STRING 176 177my @subregs_64 = ('low', 'high'); 178my @subregs_128 = ('sel_x', 'sel_y', 'sel_z', 'sel_w'); 179my @subregs_256 = ('sub0', 'sub1', 'sub2', 'sub3', 'sub4', 'sub5', 'sub6', 'sub7'); 180 181my @SGPR64 = print_sgpr_class(64, \@subregs_64, ('i64')); 182my @SGPR128 = print_sgpr_class(128, \@subregs_128, ('v4f32', 'v4i32')); 183my @SGPR256 = print_sgpr_class(256, \@subregs_256, ('v8i32')); 184 185my @VGPR64 = print_vgpr_class(64, \@subregs_64, ('i64')); 186my @VGPR128 = print_vgpr_class(128, \@subregs_128, ('v4f32')); 187 188 189my $sgpr64_list = join(',', @SGPR64); 190my $vgpr64_list = join(',', @VGPR64); 191print <<STRING; 192 193def AllReg_64 : RegisterClass<"AMDGPU", [f64, i64], 64, 194 (add $sgpr64_list, $vgpr64_list) 195>; 196 197STRING 198 199if ($INDEX_FILE ne '') { 200 open(my $fh, ">", $INDEX_FILE); 201 my %hw_values; 202 203 for (my $i = 0; $i <= $#SGPR; $i++) { 204 push (@{$hw_values{$i}}, $SGPR[$i]); 205 } 206 207 for (my $i = 0; $i <= $#SGPR64; $i++) { 208 push (@{$hw_values{$i * 2}}, $SGPR64[$i]) 209 } 210 211 for (my $i = 0; $i <= $#SGPR128; $i++) { 212 push (@{$hw_values{$i * 4}}, $SGPR128[$i]); 213 } 214 215 for (my $i = 0; $i <= $#SGPR256; $i++) { 216 push (@{$hw_values{$i * 8}}, $SGPR256[$i]); 217 } 218 219 for (my $i = 0; $i <= $#VGPR; $i++) { 220 push (@{$hw_values{$i}}, $VGPR[$i]); 221 } 222 for (my $i = 0; $i <= $#VGPR64; $i++) { 223 push (@{$hw_values{$i * 2}}, $VGPR64[$i]); 224 } 225 226 for (my $i = 0; $i <= $#VGPR128; $i++) { 227 push (@{$hw_values{$i * 4}}, $VGPR128[$i]); 228 } 229 230 231 print $fh "unsigned SIRegisterInfo::getHWRegNum(unsigned reg) const\n{\n switch(reg) {\n"; 232 for my $key (keys(%hw_values)) { 233 my @names = @{$hw_values{$key}}; 234 for my $regname (@names) { 235 print $fh " case AMDGPU::$regname:\n" 236 } 237 print $fh " return $key;\n"; 238 } 239 print $fh " default: return 0;\n }\n}\n" 240} 241 242 243 244 245sub print_sgpr_class { 246 my ($reg_width, $sub_reg_ref, @types) = @_; 247 return print_reg_class('SReg', 'SGPR', $reg_width, $SGPR_COUNT, $sub_reg_ref, @types); 248} 249 250sub print_vgpr_class { 251 my ($reg_width, $sub_reg_ref, @types) = @_; 252 return print_reg_class('VReg', 'VGPR', $reg_width, $VGPR_COUNT, $sub_reg_ref, @types); 253} 254 255sub print_reg_class { 256 my ($class_prefix, $reg_prefix, $reg_width, $reg_count, $sub_reg_ref, @types) = @_; 257 my @registers; 258 my $component_count = $reg_width / 32; 259 260 for (my $i = 0; $i < $reg_count; $i += $component_count) { 261 my $reg_name = $reg_prefix . $i . '_' . $reg_width; 262 my @sub_regs; 263 for (my $idx = 0; $idx < $component_count; $idx++) { 264 my $sub_idx = $i + $idx; 265 push(@sub_regs, $reg_prefix . $sub_idx); 266 } 267 print "def $reg_name : $reg_prefix\_$reg_width <$i, \"$reg_name\", [ ", join(',', @sub_regs) , "]>;\n"; 268 push (@registers, $reg_name); 269 } 270 271 #Add VCC to SReg_64 272 if ($class_prefix eq 'SReg' and $reg_width == 64) { 273 push (@registers, 'VCC') 274 } 275 276 #Add EXEC to SReg_64 277 if ($class_prefix eq 'SReg' and $reg_width == 64) { 278 push (@registers, 'EXEC') 279 } 280 281 my $reg_list = join(', ', @registers); 282 283 print "def $class_prefix\_$reg_width : RegisterClass<\"AMDGPU\", [" . join (', ', @types) . "], $reg_width,\n (add $reg_list)\n>{\n"; 284 print " let SubRegClasses = [($class_prefix\_", ($reg_width / $component_count) , ' ', join(', ', @{$sub_reg_ref}), ")];\n}\n"; 285 return @registers; 286} 287