1fa63f976522bd4faf19249e8c9ac4d3edda498d9Tom Stellard//===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===// 2a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 3a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// The LLVM Compiler Infrastructure 4a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 5a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// This file is distributed under the University of Illinois Open Source 6a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// License. See LICENSE.TXT for details. 7a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 8a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard//===----------------------------------------------------------------------===// 9a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 1083169900fb96f1a51d8292e66c203c64a82e204dTom Stellard// Most of the DAG lowering is handled in AMDGPUISelLowering.cpp. This file is 11fa63f976522bd4faf19249e8c9ac4d3edda498d9Tom Stellard// mostly EmitInstrWithCustomInserter(). 12a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 13a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard//===----------------------------------------------------------------------===// 14a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 15a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#include "SIISelLowering.h" 163aaa209293a281e103ef71e3578fad042972e092Tom Stellard#include "AMDIL.h" 1740c41fe890e53d99afb4e2c3fbf10043081edd9eTom Stellard#include "AMDILIntrinsicInfo.h" 18a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#include "SIInstrInfo.h" 19a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#include "SIRegisterInfo.h" 2027ae41c83dafcec09e870b3cf08b060064dbb122Tom Stellard#include "llvm/CodeGen/MachineInstrBuilder.h" 21a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#include "llvm/CodeGen/MachineRegisterInfo.h" 2227ae41c83dafcec09e870b3cf08b060064dbb122Tom Stellard#include "llvm/CodeGen/SelectionDAG.h" 23a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 24a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellardusing namespace llvm; 25a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 26a75c6163e605f35b14f26930dd9227e4f337ec9eTom StellardSITargetLowering::SITargetLowering(TargetMachine &TM) : 27a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard AMDGPUTargetLowering(TM), 28a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard TII(static_cast<const SIInstrInfo*>(TM.getInstrInfo())) 29a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard{ 3076b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass); 3176b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass); 3276b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard addRegisterClass(MVT::i32, &AMDGPU::VReg_32RegClass); 3376b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard addRegisterClass(MVT::i64, &AMDGPU::VReg_64RegClass); 34c424975572af2edd46863e5bb9fe3c51c96b4f9bTom Stellard addRegisterClass(MVT::i1, &AMDGPU::SCCRegRegClass); 35c424975572af2edd46863e5bb9fe3c51c96b4f9bTom Stellard addRegisterClass(MVT::i1, &AMDGPU::VCCRegRegClass); 36467f51613eb1f2cdaa8624bbbb3d5fae2abca4f2Tom Stellard 3776b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass); 3876b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass); 39467f51613eb1f2cdaa8624bbbb3d5fae2abca4f2Tom Stellard 40467f51613eb1f2cdaa8624bbbb3d5fae2abca4f2Tom Stellard computeRegisterProperties(); 41a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 4250ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard setOperationAction(ISD::AND, MVT::i1, Custom); 4350ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard 44467f51613eb1f2cdaa8624bbbb3d5fae2abca4f2Tom Stellard setOperationAction(ISD::ADD, MVT::i64, Legal); 45467f51613eb1f2cdaa8624bbbb3d5fae2abca4f2Tom Stellard setOperationAction(ISD::ADD, MVT::i32, Legal); 46467f51613eb1f2cdaa8624bbbb3d5fae2abca4f2Tom Stellard 47e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard setOperationAction(ISD::BR_CC, MVT::i32, Custom); 484cab682184640242d1e6f034f2b6bd7c4378c162Tom Stellard 4940c41fe890e53d99afb4e2c3fbf10043081edd9eTom Stellard setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 5040c41fe890e53d99afb4e2c3fbf10043081edd9eTom Stellard 513aaa209293a281e103ef71e3578fad042972e092Tom Stellard // We need to custom lower loads from the USER_SGPR address space, so we can 523aaa209293a281e103ef71e3578fad042972e092Tom Stellard // add the SGPRs as livein registers. 533aaa209293a281e103ef71e3578fad042972e092Tom Stellard setOperationAction(ISD::LOAD, MVT::i32, Custom); 543aaa209293a281e103ef71e3578fad042972e092Tom Stellard setOperationAction(ISD::LOAD, MVT::i64, Custom); 553aaa209293a281e103ef71e3578fad042972e092Tom Stellard 564cab682184640242d1e6f034f2b6bd7c4378c162Tom Stellard setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 574cab682184640242d1e6f034f2b6bd7c4378c162Tom Stellard setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 584cab682184640242d1e6f034f2b6bd7c4378c162Tom Stellard 594cab682184640242d1e6f034f2b6bd7c4378c162Tom Stellard setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 60fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard setTargetDAGCombine(ISD::SELECT_CC); 61fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard 62fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard setTargetDAGCombine(ISD::SETCC); 63a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard} 64a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 65a75c6163e605f35b14f26930dd9227e4f337ec9eTom StellardMachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter( 66a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MachineInstr * MI, MachineBasicBlock * BB) const 67a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard{ 68bcfc97dbf40c256ed59c2424e0c55b845f0f2569Tom Stellard const TargetInstrInfo * TII = getTargetMachine().getInstrInfo(); 69a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MachineRegisterInfo & MRI = BB->getParent()->getRegInfo(); 70a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MachineBasicBlock::iterator I = MI; 71a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 72a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard if (TII->get(MI->getOpcode()).TSFlags & SIInstrFlags::NEED_WAIT) { 73a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard AppendS_WAITCNT(MI, *BB, llvm::next(I)); 74cc7a6d269170cc3668caa4f5af29228920e8d7a7Tom Stellard return BB; 75a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard } 76a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 77a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard switch (MI->getOpcode()) { 78a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard default: 79a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); 8017f852892346fdf3b1e9eec56b7a55c470279bc8Tom Stellard 8176b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::CLAMP_SI: 8276b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64)) 83d784bc77405012b442ae9d68f200e9d115030b3cTom Stellard .addOperand(MI->getOperand(0)) 84d784bc77405012b442ae9d68f200e9d115030b3cTom Stellard .addOperand(MI->getOperand(1)) 8583169900fb96f1a51d8292e66c203c64a82e204dTom Stellard // VSRC1-2 are unused, but we still need to fill all the 8683169900fb96f1a51d8292e66c203c64a82e204dTom Stellard // operand slots, so we just reuse the VSRC0 operand 87d784bc77405012b442ae9d68f200e9d115030b3cTom Stellard .addOperand(MI->getOperand(1)) 88d784bc77405012b442ae9d68f200e9d115030b3cTom Stellard .addOperand(MI->getOperand(1)) 89d784bc77405012b442ae9d68f200e9d115030b3cTom Stellard .addImm(0) // ABS 90d784bc77405012b442ae9d68f200e9d115030b3cTom Stellard .addImm(1) // CLAMP 91d784bc77405012b442ae9d68f200e9d115030b3cTom Stellard .addImm(0) // OMOD 92d784bc77405012b442ae9d68f200e9d115030b3cTom Stellard .addImm(0); // NEG 93d784bc77405012b442ae9d68f200e9d115030b3cTom Stellard MI->eraseFromParent(); 94d784bc77405012b442ae9d68f200e9d115030b3cTom Stellard break; 95d784bc77405012b442ae9d68f200e9d115030b3cTom Stellard 9676b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::FABS_SI: 9776b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64)) 9817f852892346fdf3b1e9eec56b7a55c470279bc8Tom Stellard .addOperand(MI->getOperand(0)) 9917f852892346fdf3b1e9eec56b7a55c470279bc8Tom Stellard .addOperand(MI->getOperand(1)) 10083169900fb96f1a51d8292e66c203c64a82e204dTom Stellard // VSRC1-2 are unused, but we still need to fill all the 10183169900fb96f1a51d8292e66c203c64a82e204dTom Stellard // operand slots, so we just reuse the VSRC0 operand 10217f852892346fdf3b1e9eec56b7a55c470279bc8Tom Stellard .addOperand(MI->getOperand(1)) 10317f852892346fdf3b1e9eec56b7a55c470279bc8Tom Stellard .addOperand(MI->getOperand(1)) 10417f852892346fdf3b1e9eec56b7a55c470279bc8Tom Stellard .addImm(1) // ABS 10517f852892346fdf3b1e9eec56b7a55c470279bc8Tom Stellard .addImm(0) // CLAMP 10617f852892346fdf3b1e9eec56b7a55c470279bc8Tom Stellard .addImm(0) // OMOD 10717f852892346fdf3b1e9eec56b7a55c470279bc8Tom Stellard .addImm(0); // NEG 10817f852892346fdf3b1e9eec56b7a55c470279bc8Tom Stellard MI->eraseFromParent(); 10917f852892346fdf3b1e9eec56b7a55c470279bc8Tom Stellard break; 11017f852892346fdf3b1e9eec56b7a55c470279bc8Tom Stellard 111a35eea786823f0130b925cb25486d7d162f2d68cTom Stellard case AMDGPU::FNEG_SI: 112a35eea786823f0130b925cb25486d7d162f2d68cTom Stellard BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64)) 113a35eea786823f0130b925cb25486d7d162f2d68cTom Stellard .addOperand(MI->getOperand(0)) 114a35eea786823f0130b925cb25486d7d162f2d68cTom Stellard .addOperand(MI->getOperand(1)) 115a35eea786823f0130b925cb25486d7d162f2d68cTom Stellard // VSRC1-2 are unused, but we still need to fill all the 116a35eea786823f0130b925cb25486d7d162f2d68cTom Stellard // operand slots, so we just reuse the VSRC0 operand 117a35eea786823f0130b925cb25486d7d162f2d68cTom Stellard .addOperand(MI->getOperand(1)) 118a35eea786823f0130b925cb25486d7d162f2d68cTom Stellard .addOperand(MI->getOperand(1)) 119a35eea786823f0130b925cb25486d7d162f2d68cTom Stellard .addImm(0) // ABS 120a35eea786823f0130b925cb25486d7d162f2d68cTom Stellard .addImm(0) // CLAMP 121a35eea786823f0130b925cb25486d7d162f2d68cTom Stellard .addImm(0) // OMOD 122a35eea786823f0130b925cb25486d7d162f2d68cTom Stellard .addImm(1); // NEG 123a35eea786823f0130b925cb25486d7d162f2d68cTom Stellard MI->eraseFromParent(); 124a35eea786823f0130b925cb25486d7d162f2d68cTom Stellard break; 125a35eea786823f0130b925cb25486d7d162f2d68cTom Stellard 12676b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::SI_INTERP: 127a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard LowerSI_INTERP(MI, *BB, I, MRI); 128a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard break; 12976b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::SI_INTERP_CONST: 13005113fd2662eeb0d17fd1074001b7405eeeca43cTom Stellard LowerSI_INTERP_CONST(MI, *BB, I, MRI); 131a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard break; 13270f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer case AMDGPU::SI_KIL: 13370f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer LowerSI_KIL(MI, *BB, I, MRI); 13470f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer break; 13576b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::SI_V_CNDLT: 136a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard LowerSI_V_CNDLT(MI, *BB, I, MRI); 137a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard break; 138a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard } 139a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard return BB; 140a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard} 141a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 142a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellardvoid SITargetLowering::AppendS_WAITCNT(MachineInstr *MI, MachineBasicBlock &BB, 143a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MachineBasicBlock::iterator I) const 144a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard{ 14576b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_WAITCNT)) 146a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard .addImm(0); 147a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard} 148a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 149a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellardvoid SITargetLowering::LowerSI_INTERP(MachineInstr *MI, MachineBasicBlock &BB, 150a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const 151a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard{ 15276b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard unsigned tmp = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass); 15305113fd2662eeb0d17fd1074001b7405eeeca43cTom Stellard unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass); 154a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MachineOperand dst = MI->getOperand(0); 155a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MachineOperand iReg = MI->getOperand(1); 156a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MachineOperand jReg = MI->getOperand(2); 157a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MachineOperand attr_chan = MI->getOperand(3); 158a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MachineOperand attr = MI->getOperand(4); 159a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MachineOperand params = MI->getOperand(5); 160a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 16105113fd2662eeb0d17fd1074001b7405eeeca43cTom Stellard BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0) 162a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard .addOperand(params); 163a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 16476b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P1_F32), tmp) 165a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard .addOperand(iReg) 166a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard .addOperand(attr_chan) 16705113fd2662eeb0d17fd1074001b7405eeeca43cTom Stellard .addOperand(attr) 16805113fd2662eeb0d17fd1074001b7405eeeca43cTom Stellard .addReg(M0); 169a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 17076b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P2_F32)) 171a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard .addOperand(dst) 172a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard .addReg(tmp) 173a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard .addOperand(jReg) 174a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard .addOperand(attr_chan) 17505113fd2662eeb0d17fd1074001b7405eeeca43cTom Stellard .addOperand(attr) 17605113fd2662eeb0d17fd1074001b7405eeeca43cTom Stellard .addReg(M0); 177a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 178a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MI->eraseFromParent(); 179a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard} 180a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 181a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellardvoid SITargetLowering::LowerSI_INTERP_CONST(MachineInstr *MI, 18205113fd2662eeb0d17fd1074001b7405eeeca43cTom Stellard MachineBasicBlock &BB, MachineBasicBlock::iterator I, 18305113fd2662eeb0d17fd1074001b7405eeeca43cTom Stellard MachineRegisterInfo &MRI) const 184a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard{ 185a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MachineOperand dst = MI->getOperand(0); 186a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MachineOperand attr_chan = MI->getOperand(1); 187a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MachineOperand attr = MI->getOperand(2); 188a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MachineOperand params = MI->getOperand(3); 18905113fd2662eeb0d17fd1074001b7405eeeca43cTom Stellard unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass); 190a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 19105113fd2662eeb0d17fd1074001b7405eeeca43cTom Stellard BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0) 192a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard .addOperand(params); 193a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 19476b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_MOV_F32)) 195a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard .addOperand(dst) 196a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard .addOperand(attr_chan) 19705113fd2662eeb0d17fd1074001b7405eeeca43cTom Stellard .addOperand(attr) 19805113fd2662eeb0d17fd1074001b7405eeeca43cTom Stellard .addReg(M0); 199a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 200a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MI->eraseFromParent(); 20170f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer} 20270f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer 20370f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzervoid SITargetLowering::LowerSI_KIL(MachineInstr *MI, MachineBasicBlock &BB, 20470f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const 20570f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer{ 20670f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer // Clear this pixel from the exec mask if the operand is negative 20770f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CMPX_LE_F32_e32), 20870f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer AMDGPU::VCC) 20970f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer .addReg(AMDGPU::SREG_LIT_0) 21070f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer .addOperand(MI->getOperand(0)); 21170f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer 21270f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer // If the exec mask is non-zero, skip the next two instructions 21370f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_CBRANCH_EXECNZ)) 21470f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer .addImm(3) 21570f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer .addReg(AMDGPU::EXEC); 21670f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer 21770f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer // Exec mask is zero: Export to NULL target... 21870f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::EXP)) 21970f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer .addImm(0) 22070f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer .addImm(0x09) // V_008DFC_SQ_EXP_NULL 22170f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer .addImm(0) 22270f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer .addImm(1) 22370f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer .addImm(1) 22470f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer .addReg(AMDGPU::SREG_LIT_0) 22570f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer .addReg(AMDGPU::SREG_LIT_0) 22670f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer .addReg(AMDGPU::SREG_LIT_0) 22770f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer .addReg(AMDGPU::SREG_LIT_0); 22870f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer 22970f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer // ... and terminate wavefront 23070f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_ENDPGM)); 23170f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer 23270f9dbe298043f0e3914e6956ddcc0a098f7eca3Michel Dänzer MI->eraseFromParent(); 233a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard} 234a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 235a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellardvoid SITargetLowering::LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB, 236a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const 237a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard{ 238ee0f0f03c6c174a160e5fb3882ec5c03cdfcd163Tom Stellard BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CMP_LT_F32_e32), 239ee0f0f03c6c174a160e5fb3882ec5c03cdfcd163Tom Stellard AMDGPU::VCC) 240a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard .addOperand(MI->getOperand(1)) 24176b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard .addReg(AMDGPU::SREG_LIT_0); 242a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 24376b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CNDMASK_B32)) 244a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard .addOperand(MI->getOperand(0)) 245ee0f0f03c6c174a160e5fb3882ec5c03cdfcd163Tom Stellard .addReg(AMDGPU::VCC) 246a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard .addOperand(MI->getOperand(2)) 247a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard .addOperand(MI->getOperand(3)); 248a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 249a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MI->eraseFromParent(); 250a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard} 251a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 252d36455ba2c3febe5da6fc6f53e4acd98f771532aTom StellardEVT SITargetLowering::getSetCCResultType(EVT VT) const 253d36455ba2c3febe5da6fc6f53e4acd98f771532aTom Stellard{ 254d36455ba2c3febe5da6fc6f53e4acd98f771532aTom Stellard return MVT::i1; 255d36455ba2c3febe5da6fc6f53e4acd98f771532aTom Stellard} 256d36455ba2c3febe5da6fc6f53e4acd98f771532aTom Stellard 257e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard//===----------------------------------------------------------------------===// 258e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard// Custom DAG Lowering Operations 259e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard//===----------------------------------------------------------------------===// 260e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard 261e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom StellardSDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const 262e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard{ 263e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard switch (Op.getOpcode()) { 264e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); 265e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard case ISD::BR_CC: return LowerBR_CC(Op, DAG); 2663aaa209293a281e103ef71e3578fad042972e092Tom Stellard case ISD::LOAD: return LowerLOAD(Op, DAG); 2674cab682184640242d1e6f034f2b6bd7c4378c162Tom Stellard case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 26850ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard case ISD::AND: return Loweri1ContextSwitch(Op, DAG, ISD::AND); 26940c41fe890e53d99afb4e2c3fbf10043081edd9eTom Stellard case ISD::INTRINSIC_WO_CHAIN: { 27040c41fe890e53d99afb4e2c3fbf10043081edd9eTom Stellard unsigned IntrinsicID = 27140c41fe890e53d99afb4e2c3fbf10043081edd9eTom Stellard cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 27240c41fe890e53d99afb4e2c3fbf10043081edd9eTom Stellard EVT VT = Op.getValueType(); 27340c41fe890e53d99afb4e2c3fbf10043081edd9eTom Stellard switch (IntrinsicID) { 27440c41fe890e53d99afb4e2c3fbf10043081edd9eTom Stellard case AMDGPUIntrinsic::SI_vs_load_buffer_index: 27540c41fe890e53d99afb4e2c3fbf10043081edd9eTom Stellard return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass, 27640c41fe890e53d99afb4e2c3fbf10043081edd9eTom Stellard AMDGPU::VGPR0, VT); 27740c41fe890e53d99afb4e2c3fbf10043081edd9eTom Stellard default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); 27840c41fe890e53d99afb4e2c3fbf10043081edd9eTom Stellard } 27940c41fe890e53d99afb4e2c3fbf10043081edd9eTom Stellard break; 28040c41fe890e53d99afb4e2c3fbf10043081edd9eTom Stellard } 281e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard } 28240c41fe890e53d99afb4e2c3fbf10043081edd9eTom Stellard return SDValue(); 283e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard} 284e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard 28550ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard/// Loweri1ContextSwitch - The function is for lowering i1 operations on the 28650ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard/// VCC register. In the VALU context, VCC is a one bit register, but in the 28750ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard/// SALU context the VCC is a 64-bit register (1-bit per thread). Since only 28850ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard/// the SALU can perform operations on the VCC register, we need to promote 28950ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard/// the operand types from i1 to i64 in order for tablegen to be able to match 29050ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard/// this operation to the correct SALU instruction. We do this promotion by 29150ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard/// wrapping the operands in a CopyToReg node. 29250ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard/// 29350ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom StellardSDValue SITargetLowering::Loweri1ContextSwitch(SDValue Op, 29450ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard SelectionDAG &DAG, 29550ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard unsigned VCCNode) const 29650ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard{ 29750ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard DebugLoc DL = Op.getDebugLoc(); 29850ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard 29950ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard SDValue OpNode = DAG.getNode(VCCNode, DL, MVT::i64, 30050ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard DAG.getNode(SIISD::VCC_BITCAST, DL, MVT::i64, 30150ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard Op.getOperand(0)), 30250ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard DAG.getNode(SIISD::VCC_BITCAST, DL, MVT::i64, 30350ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard Op.getOperand(1))); 30450ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard 30550ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard return DAG.getNode(SIISD::VCC_BITCAST, DL, MVT::i1, OpNode); 30650ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard} 30750ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard 308e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom StellardSDValue SITargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const 309e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard{ 310e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard SDValue Chain = Op.getOperand(0); 311e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard SDValue CC = Op.getOperand(1); 312e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard SDValue LHS = Op.getOperand(2); 313e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard SDValue RHS = Op.getOperand(3); 314e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard SDValue JumpT = Op.getOperand(4); 315e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard SDValue CmpValue; 316e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard SDValue Result; 317e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard CmpValue = DAG.getNode( 318e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard ISD::SETCC, 319e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard Op.getDebugLoc(), 320e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard MVT::i1, 321e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard LHS, RHS, 322e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard CC); 323e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard 324e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard Result = DAG.getNode( 32527ae41c83dafcec09e870b3cf08b060064dbb122Tom Stellard AMDGPUISD::BRANCH_COND, 326e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard CmpValue.getDebugLoc(), 327e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard MVT::Other, Chain, 328e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard JumpT, CmpValue); 329e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard return Result; 330e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard} 331e8825ce6e12a8ec6fbe1ef76fb5e8ef8eb1b1218Tom Stellard 3323aaa209293a281e103ef71e3578fad042972e092Tom StellardSDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const 3333aaa209293a281e103ef71e3578fad042972e092Tom Stellard{ 3343aaa209293a281e103ef71e3578fad042972e092Tom Stellard EVT VT = Op.getValueType(); 3353aaa209293a281e103ef71e3578fad042972e092Tom Stellard LoadSDNode *Ptr = dyn_cast<LoadSDNode>(Op); 3363aaa209293a281e103ef71e3578fad042972e092Tom Stellard 3373aaa209293a281e103ef71e3578fad042972e092Tom Stellard assert(Ptr); 3383aaa209293a281e103ef71e3578fad042972e092Tom Stellard 3393aaa209293a281e103ef71e3578fad042972e092Tom Stellard unsigned AddrSpace = Ptr->getPointerInfo().getAddrSpace(); 3403aaa209293a281e103ef71e3578fad042972e092Tom Stellard 3413aaa209293a281e103ef71e3578fad042972e092Tom Stellard // We only need to lower USER_SGPR address space loads 3423aaa209293a281e103ef71e3578fad042972e092Tom Stellard if (AddrSpace != AMDGPUAS::USER_SGPR_ADDRESS) { 3433aaa209293a281e103ef71e3578fad042972e092Tom Stellard return SDValue(); 3443aaa209293a281e103ef71e3578fad042972e092Tom Stellard } 3453aaa209293a281e103ef71e3578fad042972e092Tom Stellard 3463aaa209293a281e103ef71e3578fad042972e092Tom Stellard // Loads from the USER_SGPR address space can only have constant value 3473aaa209293a281e103ef71e3578fad042972e092Tom Stellard // pointers. 3483aaa209293a281e103ef71e3578fad042972e092Tom Stellard ConstantSDNode *BasePtr = dyn_cast<ConstantSDNode>(Ptr->getBasePtr()); 3493aaa209293a281e103ef71e3578fad042972e092Tom Stellard assert(BasePtr); 3503aaa209293a281e103ef71e3578fad042972e092Tom Stellard 3513aaa209293a281e103ef71e3578fad042972e092Tom Stellard unsigned TypeDwordWidth = VT.getSizeInBits() / 32; 3523aaa209293a281e103ef71e3578fad042972e092Tom Stellard const TargetRegisterClass * dstClass; 3533aaa209293a281e103ef71e3578fad042972e092Tom Stellard switch (TypeDwordWidth) { 3543aaa209293a281e103ef71e3578fad042972e092Tom Stellard default: 3553aaa209293a281e103ef71e3578fad042972e092Tom Stellard assert(!"USER_SGPR value size not implemented"); 3563aaa209293a281e103ef71e3578fad042972e092Tom Stellard return SDValue(); 3573aaa209293a281e103ef71e3578fad042972e092Tom Stellard case 1: 3583aaa209293a281e103ef71e3578fad042972e092Tom Stellard dstClass = &AMDGPU::SReg_32RegClass; 3593aaa209293a281e103ef71e3578fad042972e092Tom Stellard break; 3603aaa209293a281e103ef71e3578fad042972e092Tom Stellard case 2: 3613aaa209293a281e103ef71e3578fad042972e092Tom Stellard dstClass = &AMDGPU::SReg_64RegClass; 3623aaa209293a281e103ef71e3578fad042972e092Tom Stellard break; 3633aaa209293a281e103ef71e3578fad042972e092Tom Stellard } 3643aaa209293a281e103ef71e3578fad042972e092Tom Stellard uint64_t Index = BasePtr->getZExtValue(); 3653aaa209293a281e103ef71e3578fad042972e092Tom Stellard assert(Index % TypeDwordWidth == 0 && "USER_SGPR not properly aligned"); 3663aaa209293a281e103ef71e3578fad042972e092Tom Stellard unsigned SGPRIndex = Index / TypeDwordWidth; 3673aaa209293a281e103ef71e3578fad042972e092Tom Stellard unsigned Reg = dstClass->getRegister(SGPRIndex); 3683aaa209293a281e103ef71e3578fad042972e092Tom Stellard 3693aaa209293a281e103ef71e3578fad042972e092Tom Stellard DAG.ReplaceAllUsesOfValueWith(Op, CreateLiveInRegister(DAG, dstClass, Reg, 3703aaa209293a281e103ef71e3578fad042972e092Tom Stellard VT)); 3713aaa209293a281e103ef71e3578fad042972e092Tom Stellard return SDValue(); 3723aaa209293a281e103ef71e3578fad042972e092Tom Stellard} 3733aaa209293a281e103ef71e3578fad042972e092Tom Stellard 3744cab682184640242d1e6f034f2b6bd7c4378c162Tom StellardSDValue SITargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const 3754cab682184640242d1e6f034f2b6bd7c4378c162Tom Stellard{ 3764cab682184640242d1e6f034f2b6bd7c4378c162Tom Stellard SDValue LHS = Op.getOperand(0); 3774cab682184640242d1e6f034f2b6bd7c4378c162Tom Stellard SDValue RHS = Op.getOperand(1); 3784cab682184640242d1e6f034f2b6bd7c4378c162Tom Stellard SDValue True = Op.getOperand(2); 3794cab682184640242d1e6f034f2b6bd7c4378c162Tom Stellard SDValue False = Op.getOperand(3); 3804cab682184640242d1e6f034f2b6bd7c4378c162Tom Stellard SDValue CC = Op.getOperand(4); 3814cab682184640242d1e6f034f2b6bd7c4378c162Tom Stellard EVT VT = Op.getValueType(); 3824cab682184640242d1e6f034f2b6bd7c4378c162Tom Stellard DebugLoc DL = Op.getDebugLoc(); 3834cab682184640242d1e6f034f2b6bd7c4378c162Tom Stellard 3844cab682184640242d1e6f034f2b6bd7c4378c162Tom Stellard SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC); 3854cab682184640242d1e6f034f2b6bd7c4378c162Tom Stellard return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False); 3864cab682184640242d1e6f034f2b6bd7c4378c162Tom Stellard} 38750ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard 388fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard//===----------------------------------------------------------------------===// 389fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard// Custom DAG optimizations 390fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard//===----------------------------------------------------------------------===// 391fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard 392fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom StellardSDValue SITargetLowering::PerformDAGCombine(SDNode *N, 393fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard DAGCombinerInfo &DCI) const { 394fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard SelectionDAG &DAG = DCI.DAG; 395fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard DebugLoc DL = N->getDebugLoc(); 396fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard EVT VT = N->getValueType(0); 397fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard 398fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard switch (N->getOpcode()) { 399fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard default: break; 400fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard case ISD::SELECT_CC: { 401fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard N->dump(); 402fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard ConstantSDNode *True, *False; 403fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc) 404fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard if ((True = dyn_cast<ConstantSDNode>(N->getOperand(2))) 405fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard && (False = dyn_cast<ConstantSDNode>(N->getOperand(3))) 406fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard && True->isAllOnesValue() 407fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard && False->isNullValue() 408fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard && VT == MVT::i1) { 409fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0), 410fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard N->getOperand(1), N->getOperand(4)); 411fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard 412fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard } 413fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard break; 414fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard } 415fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard case ISD::SETCC: { 416fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard SDValue Arg0 = N->getOperand(0); 417fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard SDValue Arg1 = N->getOperand(1); 418fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard SDValue CC = N->getOperand(2); 419fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard ConstantSDNode * C = NULL; 420fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard ISD::CondCode CCOp = dyn_cast<CondCodeSDNode>(CC)->get(); 421fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard 422fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne) 423fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard if (VT == MVT::i1 424fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard && Arg0.getOpcode() == ISD::SIGN_EXTEND 425fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard && Arg0.getOperand(0).getValueType() == MVT::i1 426fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard && (C = dyn_cast<ConstantSDNode>(Arg1)) 427fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard && C->isNullValue() 428fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard && CCOp == ISD::SETNE) { 429fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard return SimplifySetCC(VT, Arg0.getOperand(0), 430fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard DAG.getConstant(0, MVT::i1), CCOp, true, DCI, DL); 431fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard } 432fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard break; 433fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard } 434fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard } 435fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard return SDValue(); 436fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard} 437fd1f19a191c648e7c6fdaac3167e900e4fed4a6dTom Stellard 43850ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard#define NODE_NAME_CASE(node) case SIISD::node: return #node; 43950ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard 44050ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellardconst char* SITargetLowering::getTargetNodeName(unsigned Opcode) const 44150ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard{ 44250ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard switch (Opcode) { 44350ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard default: return AMDGPUTargetLowering::getTargetNodeName(Opcode); 44450ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard NODE_NAME_CASE(VCC_AND) 44550ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard NODE_NAME_CASE(VCC_BITCAST) 44650ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard } 44750ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48Tom Stellard} 448