1fa63f976522bd4faf19249e8c9ac4d3edda498d9Tom Stellard//===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===// 2a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 3a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// The LLVM Compiler Infrastructure 4a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 5a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// This file is distributed under the University of Illinois Open Source 6a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// License. See LICENSE.TXT for details. 7a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 8a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard//===----------------------------------------------------------------------===// 9a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 10fa63f976522bd4faf19249e8c9ac4d3edda498d9Tom Stellard// SI Implementation of TargetInstrInfo. 11a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 12a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard//===----------------------------------------------------------------------===// 13a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 14a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 15a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#include "SIInstrInfo.h" 16a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#include "AMDGPUTargetMachine.h" 1727ae41c83dafcec09e870b3cf08b060064dbb122Tom Stellard#include "llvm/CodeGen/MachineInstrBuilder.h" 18a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#include "llvm/CodeGen/MachineRegisterInfo.h" 19a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#include "llvm/MC/MCInstrDesc.h" 20a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 21a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#include <stdio.h> 22a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 23a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellardusing namespace llvm; 24a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 25a75c6163e605f35b14f26930dd9227e4f337ec9eTom StellardSIInstrInfo::SIInstrInfo(AMDGPUTargetMachine &tm) 26a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard : AMDGPUInstrInfo(tm), 27a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard RI(tm, *this), 28a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard TM(tm) 29a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard { } 30a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 31a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellardconst SIRegisterInfo &SIInstrInfo::getRegisterInfo() const 32a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard{ 33a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard return RI; 34a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard} 35a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 36a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellardvoid 37a75c6163e605f35b14f26930dd9227e4f337ec9eTom StellardSIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 38a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MachineBasicBlock::iterator MI, DebugLoc DL, 39a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard unsigned DestReg, unsigned SrcReg, 40a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard bool KillSrc) const 41a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard{ 42d4bdd09d4714ae51b9f5675f7f5c678d431061e8Tom Stellard 43d4bdd09d4714ae51b9f5675f7f5c678d431061e8Tom Stellard // If we are trying to copy to or from SCC, there is a bug somewhere else in 44d4bdd09d4714ae51b9f5675f7f5c678d431061e8Tom Stellard // the backend. While it may be theoretically possible to do this, it should 45d4bdd09d4714ae51b9f5675f7f5c678d431061e8Tom Stellard // never be necessary. 46d4bdd09d4714ae51b9f5675f7f5c678d431061e8Tom Stellard assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC); 47d4bdd09d4714ae51b9f5675f7f5c678d431061e8Tom Stellard 4876b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg) 49a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard .addReg(SrcReg, getKillRegState(KillSrc)); 50a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard} 51a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 52d6c2d3722d795381d3cdf11fe00f63780ad0725aTom StellardMachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg, 53d6c2d3722d795381d3cdf11fe00f63780ad0725aTom Stellard int64_t Imm) const 54d6c2d3722d795381d3cdf11fe00f63780ad0725aTom Stellard{ 5576b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_IMM_I32), DebugLoc()); 56d6c2d3722d795381d3cdf11fe00f63780ad0725aTom Stellard MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); 57d6c2d3722d795381d3cdf11fe00f63780ad0725aTom Stellard MachineInstrBuilder(MI).addImm(Imm); 58d6c2d3722d795381d3cdf11fe00f63780ad0725aTom Stellard 59d6c2d3722d795381d3cdf11fe00f63780ad0725aTom Stellard return MI; 60d6c2d3722d795381d3cdf11fe00f63780ad0725aTom Stellard 61d6c2d3722d795381d3cdf11fe00f63780ad0725aTom Stellard} 62f81e4663a766e71e907886640327abea4a0d78e2Tom Stellard 63f81e4663a766e71e907886640327abea4a0d78e2Tom Stellardbool SIInstrInfo::isMov(unsigned Opcode) const 64f81e4663a766e71e907886640327abea4a0d78e2Tom Stellard{ 65f81e4663a766e71e907886640327abea4a0d78e2Tom Stellard switch(Opcode) { 66f81e4663a766e71e907886640327abea4a0d78e2Tom Stellard default: return false; 6776b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::S_MOV_B32: 6876b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::S_MOV_B64: 6976b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::V_MOV_B32_e32: 7076b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::V_MOV_B32_e64: 7176b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::V_MOV_IMM_F32: 7276b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::V_MOV_IMM_I32: 7376b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::S_MOV_IMM_I32: 74f81e4663a766e71e907886640327abea4a0d78e2Tom Stellard return true; 75f81e4663a766e71e907886640327abea4a0d78e2Tom Stellard } 76f81e4663a766e71e907886640327abea4a0d78e2Tom Stellard} 77