SIInstrInfo.cpp revision d6c2d3722d795381d3cdf11fe00f63780ad0725a 
1//===-- SIInstrInfo.cpp - SI Instruction Information  ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// SI Implementation of TargetInstrInfo.
11//
12//===----------------------------------------------------------------------===//
13
14
15#include "SIInstrInfo.h"
16#include "AMDGPUTargetMachine.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/MC/MCInstrDesc.h"
19
20#include <stdio.h>
21
22using namespace llvm;
23
24SIInstrInfo::SIInstrInfo(AMDGPUTargetMachine &tm)
25  : AMDGPUInstrInfo(tm),
26    RI(tm, *this),
27    TM(tm)
28    { }
29
30const SIRegisterInfo &SIInstrInfo::getRegisterInfo() const
31{
32  return RI;
33}
34
35void
36SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
37                           MachineBasicBlock::iterator MI, DebugLoc DL,
38                           unsigned DestReg, unsigned SrcReg,
39                           bool KillSrc) const
40{
41  BuildMI(MBB, MI, DL, get(AMDIL::V_MOV_B32_e32), DestReg)
42   .addReg(SrcReg, getKillRegState(KillSrc));
43}
44
45unsigned SIInstrInfo::getEncodingType(const MachineInstr &MI) const
46{
47  return get(MI.getOpcode()).TSFlags & SI_INSTR_FLAGS_ENCODING_MASK;
48}
49
50unsigned SIInstrInfo::getEncodingBytes(const MachineInstr &MI) const
51{
52
53  /* Instructions with literal constants are expanded to 64-bits, and
54   * the constant is stored in bits [63:32] */
55  for (unsigned i = 0; i < MI.getNumOperands(); i++) {
56    if (MI.getOperand(i).getType() == MachineOperand::MO_FPImmediate) {
57      return 8;
58    }
59  }
60
61  /* This instruction always has a literal */
62  if (MI.getOpcode() == AMDIL::S_MOV_IMM_I32) {
63    return 8;
64  }
65
66  unsigned encoding_type = getEncodingType(MI);
67  switch (encoding_type) {
68    case SIInstrEncodingType::EXP:
69    case SIInstrEncodingType::LDS:
70    case SIInstrEncodingType::MUBUF:
71    case SIInstrEncodingType::MTBUF:
72    case SIInstrEncodingType::MIMG:
73    case SIInstrEncodingType::VOP3:
74      return 8;
75    default:
76      return 4;
77  }
78}
79
80MachineInstr * SIInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF,
81    DebugLoc DL) const
82{
83  MachineInstr * newMI = AMDGPUInstrInfo::convertToISA(MI, MF, DL);
84  const MCInstrDesc &newDesc = get(newMI->getOpcode());
85
86  /* If this instruction was converted to a VOP3, we need to add the extra
87   * operands for abs, clamp, omod, and negate. */
88  if (getEncodingType(*newMI) == SIInstrEncodingType::VOP3
89      && newMI->getNumOperands() < newDesc.getNumOperands()) {
90    MachineInstrBuilder builder(newMI);
91    for (unsigned op_idx = newMI->getNumOperands();
92                  op_idx < newDesc.getNumOperands(); op_idx++) {
93      builder.addImm(0);
94    }
95  }
96  return newMI;
97}
98
99unsigned SIInstrInfo::getISAOpcode(unsigned AMDILopcode) const
100{
101  switch (AMDILopcode) {
102  //XXX We need a better way of detecting end of program
103  case AMDIL::RETURN: return AMDIL::S_ENDPGM;
104  case AMDIL::MOVE_f32: return AMDIL::V_MOV_B32_e32;
105  default: return AMDILopcode;
106  }
107}
108
109MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg,
110                                           int64_t Imm) const
111{
112  MachineInstr * MI = MF->CreateMachineInstr(get(AMDIL::V_MOV_IMM), DebugLoc());
113  MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
114  MachineInstrBuilder(MI).addImm(Imm);
115
116  return MI;
117
118}
119