SIInstrInfo.h revision d6c2d3722d795381d3cdf11fe00f63780ad0725a 
1//===-- SIInstrInfo.h - SI Instruction Info Interface ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Interface definition for SIInstrInfo.
11//
12//===----------------------------------------------------------------------===//
13
14
15#ifndef SIINSTRINFO_H
16#define SIINSTRINFO_H
17
18#include "AMDGPUInstrInfo.h"
19#include "SIRegisterInfo.h"
20
21namespace llvm {
22
23class SIInstrInfo : public AMDGPUInstrInfo {
24private:
25  const SIRegisterInfo RI;
26  AMDGPUTargetMachine &TM;
27
28public:
29  explicit SIInstrInfo(AMDGPUTargetMachine &tm);
30
31  const SIRegisterInfo &getRegisterInfo() const;
32
33  virtual void copyPhysReg(MachineBasicBlock &MBB,
34                           MachineBasicBlock::iterator MI, DebugLoc DL,
35                           unsigned DestReg, unsigned SrcReg,
36                           bool KillSrc) const;
37
38  /// getEncodingType - Returns the encoding type of this instruction.
39  unsigned getEncodingType(const MachineInstr &MI) const;
40
41  /// getEncodingBytes - Returns the size of this instructions encoding in
42  /// number of bytes.
43  unsigned getEncodingBytes(const MachineInstr &MI) const;
44
45  /// convertToISA - Convert the AMDIL MachineInstr to a supported SI
46  ///MachineInstr
47  virtual MachineInstr * convertToISA(MachineInstr & MI, MachineFunction &MF,
48                                        DebugLoc DL) const;
49
50  /// getISAOpcode - This function takes an AMDIL opcode as an argument and
51  /// returns an equivalent SI opcode.
52  virtual unsigned getISAOpcode(unsigned AMDILopcode) const;
53
54  virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
55                                        int64_t Imm) const;
56
57  virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;}
58
59  };
60
61} // End namespace llvm
62
63// These must be kept in sync with SIInstructions.td and also the
64// InstrEncodingInfo array in SIInstrInfo.cpp.
65//
66// NOTE: This enum is only used to identify the encoding type within LLVM,
67// the actual encoding type that is part of the instruction format is different
68namespace SIInstrEncodingType {
69  enum Encoding {
70    EXP = 0,
71    LDS = 1,
72    MIMG = 2,
73    MTBUF = 3,
74    MUBUF = 4,
75    SMRD = 5,
76    SOP1 = 6,
77    SOP2 = 7,
78    SOPC = 8,
79    SOPK = 9,
80    SOPP = 10,
81    VINTRP = 11,
82    VOP1 = 12,
83    VOP2 = 13,
84    VOP3 = 14,
85    VOPC = 15
86  };
87}
88
89#define SI_INSTR_FLAGS_ENCODING_MASK 0xf
90
91namespace SIInstrFlags {
92  enum Flags {
93    // First 4 bits are the instruction encoding
94    NEED_WAIT = 1 << 4
95  };
96}
97
98#endif //SIINSTRINFO_H
99