SIInstrInfo.td revision 05113fd2662eeb0d17fd1074001b7405eeeca43c 
1//===-- SIInstrInfo.td - SI Instruction Encodings ---------*- tablegen -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// SI DAG Profiles
12//===----------------------------------------------------------------------===//
13def SDTVCCBinaryOp : SDTypeProfile<1, 2, [
14  SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 2>
15]>;
16
17//===----------------------------------------------------------------------===//
18// SI DAG Nodes
19//===----------------------------------------------------------------------===//
20
21// and operation on 64-bit wide vcc
22def SIvcc_and : SDNode<"SIISD::VCC_AND", SDTVCCBinaryOp,
23  [SDNPCommutative, SDNPAssociative]
24>;
25
26// Special bitcast node for sharing VCC register between VALU and SALU
27def SIvcc_bitcast : SDNode<"SIISD::VCC_BITCAST",
28  SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>]>
29>;
30
31class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
32    AMDGPUInst<outs, ins, asm, pattern> {
33
34  field bits<4> EncodingType = 0;
35  field bits<1> NeedWait = 0;
36
37  let TSFlags{3-0} = EncodingType;
38  let TSFlags{4} = NeedWait;
39
40}
41
42class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
43    InstSI <outs, ins, asm, pattern> {
44
45  field bits<32> Inst;
46}
47
48class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
49    InstSI <outs, ins, asm, pattern> {
50
51  field bits<64> Inst;
52}
53
54class SIOperand <ValueType vt, dag opInfo>: Operand <vt> {
55  let EncoderMethod = "encodeOperand";
56  let MIOperandInfo = opInfo;
57}
58
59def IMM16bit : ImmLeaf <
60  i16,
61  [{return isInt<16>(Imm);}]
62>;
63
64def IMM8bit : ImmLeaf <
65  i32,
66  [{return (int32_t)Imm >= 0 && (int32_t)Imm <= 0xff;}]
67>;
68
69def IMM12bit : ImmLeaf <
70  i16,
71  [{return (int16_t)Imm >= 0 && (int16_t)Imm <= 0xfff;}]
72>;
73
74def IMM32bitIn64bit : ImmLeaf <
75  i64,
76  [{return isInt<32>(Imm);}]
77>;
78
79class GPR4Align <RegisterClass rc> : Operand <vAny> {
80  let EncoderMethod = "GPR4AlignEncode";
81  let MIOperandInfo = (ops rc:$reg); 
82}
83
84class GPR2Align <RegisterClass rc, ValueType vt> : Operand <vt> {
85  let EncoderMethod = "GPR2AlignEncode";
86  let MIOperandInfo = (ops rc:$reg);
87}
88
89def i32Literal : Operand <i32> {
90  let EncoderMethod = "i32LiteralEncode";
91}
92
93// i64Literal uses the same encoder method as i32 literal, because an
94// i64Literal is really a i32 literal with the top 32-bits all set to zero.
95def i64Literal : Operand <i64> {
96  let EncoderMethod = "i32LiteralEncode";
97}
98
99def SMRDmemrr : Operand<iPTR> {
100  let MIOperandInfo = (ops SReg_64, SReg_32);
101  let EncoderMethod = "GPR2AlignEncode";
102}
103
104def SMRDmemri : Operand<iPTR> {
105  let MIOperandInfo = (ops SReg_64, i32imm);
106  let EncoderMethod = "SMRDmemriEncode";
107}
108
109def ADDR_Reg     : ComplexPattern<i64, 2, "SelectADDRReg", [], []>;
110def ADDR_Offset8 : ComplexPattern<i64, 2, "SelectADDR8BitOffset", [], []>;
111
112def EXP : Enc64<
113  (outs),
114  (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
115       VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
116  "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
117  [] > {
118
119  bits<4> EN;
120  bits<6> TGT;
121  bits<1> COMPR;
122  bits<1> DONE;
123  bits<1> VM;
124  bits<8> VSRC0;
125  bits<8> VSRC1;
126  bits<8> VSRC2;
127  bits<8> VSRC3;
128
129  let Inst{3-0} = EN;
130  let Inst{9-4} = TGT;
131  let Inst{10} = COMPR;
132  let Inst{11} = DONE;
133  let Inst{12} = VM;
134  let Inst{31-26} = 0x3e;
135  let Inst{39-32} = VSRC0;
136  let Inst{47-40} = VSRC1;
137  let Inst{55-48} = VSRC2;
138  let Inst{63-56} = VSRC3;
139  let EncodingType = 0; //SIInstrEncodingType::EXP
140
141  let NeedWait = 1;
142  let usesCustomInserter = 1;
143}
144
145class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
146    Enc64 <outs, ins, asm, pattern> {
147
148  bits<8> VDATA;
149  bits<4> DMASK;
150  bits<1> UNORM;
151  bits<1> GLC;
152  bits<1> DA;
153  bits<1> R128;
154  bits<1> TFE;
155  bits<1> LWE;
156  bits<1> SLC;
157  bits<8> VADDR;
158  bits<5> SRSRC;
159  bits<5> SSAMP; 
160
161  let Inst{11-8} = DMASK;
162  let Inst{12} = UNORM;
163  let Inst{13} = GLC;
164  let Inst{14} = DA;
165  let Inst{15} = R128;
166  let Inst{16} = TFE;
167  let Inst{17} = LWE;
168  let Inst{24-18} = op;
169  let Inst{25} = SLC;
170  let Inst{31-26} = 0x3c;
171  let Inst{39-32} = VADDR;
172  let Inst{47-40} = VDATA;
173  let Inst{52-48} = SRSRC;
174  let Inst{57-53} = SSAMP;
175
176  let EncodingType = 2; //SIInstrEncodingType::MIMG
177
178  let NeedWait = 1;
179  let usesCustomInserter = 1;
180}
181
182class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
183    Enc64<outs, ins, asm, pattern> {
184
185  bits<8> VDATA;
186  bits<12> OFFSET;
187  bits<1> OFFEN;
188  bits<1> IDXEN;
189  bits<1> GLC;
190  bits<1> ADDR64;
191  bits<4> DFMT;
192  bits<3> NFMT;
193  bits<8> VADDR;
194  bits<5> SRSRC;
195  bits<1> SLC;
196  bits<1> TFE;
197  bits<8> SOFFSET;
198
199  let Inst{11-0} = OFFSET;
200  let Inst{12} = OFFEN;
201  let Inst{13} = IDXEN;
202  let Inst{14} = GLC;
203  let Inst{15} = ADDR64;
204  let Inst{18-16} = op;
205  let Inst{22-19} = DFMT;
206  let Inst{25-23} = NFMT;
207  let Inst{31-26} = 0x3a; //encoding
208  let Inst{39-32} = VADDR;
209  let Inst{47-40} = VDATA;
210  let Inst{52-48} = SRSRC;
211  let Inst{54} = SLC;
212  let Inst{55} = TFE;
213  let Inst{63-56} = SOFFSET;
214  let EncodingType = 3; //SIInstrEncodingType::MTBUF
215
216  let NeedWait = 1;
217  let usesCustomInserter = 1;
218  let neverHasSideEffects = 1;
219}
220
221class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
222    Enc64<outs, ins, asm, pattern> {
223
224  bits<8> VDATA;
225  bits<12> OFFSET;
226  bits<1> OFFEN;
227  bits<1> IDXEN;
228  bits<1> GLC;
229  bits<1> ADDR64;
230  bits<1> LDS;
231  bits<8> VADDR;
232  bits<5> SRSRC;
233  bits<1> SLC;
234  bits<1> TFE;
235  bits<8> SOFFSET;
236
237  let Inst{11-0} = OFFSET;
238  let Inst{12} = OFFEN;
239  let Inst{13} = IDXEN;
240  let Inst{14} = GLC;
241  let Inst{15} = ADDR64;
242  let Inst{16} = LDS;
243  let Inst{24-18} = op;
244  let Inst{31-26} = 0x38; //encoding
245  let Inst{39-32} = VADDR;
246  let Inst{47-40} = VDATA;
247  let Inst{52-48} = SRSRC;
248  let Inst{54} = SLC;
249  let Inst{55} = TFE;
250  let Inst{63-56} = SOFFSET;
251  let EncodingType = 4; //SIInstrEncodingType::MUBUF
252
253  let NeedWait = 1;
254  let usesCustomInserter = 1;
255  let neverHasSideEffects = 1;
256}
257
258class SMRD <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
259    Enc32<outs, ins, asm, pattern> {
260
261  bits<7> SDST;
262  bits<15> PTR;
263  bits<8> OFFSET = PTR{7-0};
264  bits<1> IMM    = PTR{8};
265  bits<6> SBASE  = PTR{14-9};
266  
267  let Inst{7-0} = OFFSET;
268  let Inst{8} = IMM;
269  let Inst{14-9} = SBASE;
270  let Inst{21-15} = SDST;
271  let Inst{26-22} = op;
272  let Inst{31-27} = 0x18; //encoding
273  let EncodingType = 5; //SIInstrEncodingType::SMRD
274
275  let NeedWait = 1;
276  let usesCustomInserter = 1;
277}
278
279class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
280    Enc32<outs, ins, asm, pattern> {
281
282  bits<7> SDST;
283  bits<8> SSRC0;
284
285  let Inst{7-0} = SSRC0;
286  let Inst{15-8} = op;
287  let Inst{22-16} = SDST;
288  let Inst{31-23} = 0x17d; //encoding;
289  let EncodingType = 6; //SIInstrEncodingType::SOP1
290}
291
292class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
293    Enc32 <outs, ins, asm, pattern> {
294  
295  bits<7> SDST;
296  bits<8> SSRC0;
297  bits<8> SSRC1;
298
299  let Inst{7-0} = SSRC0;
300  let Inst{15-8} = SSRC1;
301  let Inst{22-16} = SDST;
302  let Inst{29-23} = op;
303  let Inst{31-30} = 0x2; // encoding
304  let EncodingType = 7; // SIInstrEncodingType::SOP2  
305}
306
307class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
308  Enc32<outs, ins, asm, pattern> {
309
310  bits<8> SSRC0;
311  bits<8> SSRC1;
312
313  let Inst{7-0} = SSRC0;
314  let Inst{15-8} = SSRC1;
315  let Inst{22-16} = op;
316  let Inst{31-23} = 0x17e;
317  let EncodingType = 8; // SIInstrEncodingType::SOPC
318
319  let DisableEncoding = "$dst";
320}
321
322class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
323   Enc32 <outs, ins , asm, pattern> {
324
325  bits <7> SDST;
326  bits <16> SIMM16;
327  
328  let Inst{15-0} = SIMM16;
329  let Inst{22-16} = SDST;
330  let Inst{27-23} = op;
331  let Inst{31-28} = 0xb; //encoding
332  let EncodingType = 9; // SIInstrEncodingType::SOPK
333}
334
335class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> : Enc32 <
336  (outs),
337  ins,
338  asm,
339  pattern > {
340
341  bits <16> SIMM16;
342
343  let Inst{15-0} = SIMM16;
344  let Inst{22-16} = op;
345  let Inst{31-23} = 0x17f; // encoding
346  let EncodingType = 10; // SIInstrEncodingType::SOPP
347}
348    
349
350class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
351    Enc32 <outs, ins, asm, pattern> {
352
353  bits<8> VDST;
354  bits<8> VSRC;
355  bits<2> ATTRCHAN;
356  bits<6> ATTR;
357
358  let Inst{7-0} = VSRC;
359  let Inst{9-8} = ATTRCHAN;
360  let Inst{15-10} = ATTR;
361  let Inst{17-16} = op;
362  let Inst{25-18} = VDST;
363  let Inst{31-26} = 0x32; // encoding
364  let EncodingType = 11; // SIInstrEncodingType::VINTRP
365
366  let neverHasSideEffects = 1;
367}
368
369class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
370    Enc32 <outs, ins, asm, pattern> {
371
372  bits<8> VDST;
373  bits<9> SRC0;
374  
375  let Inst{8-0} = SRC0;
376  let Inst{16-9} = op;
377  let Inst{24-17} = VDST;
378  let Inst{31-25} = 0x3f; //encoding
379  
380  let EncodingType = 12; // SIInstrEncodingType::VOP1
381  let PostEncoderMethod = "VOPPostEncode";
382}
383
384class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
385    Enc32 <outs, ins, asm, pattern> {
386
387  bits<8> VDST;
388  bits<9> SRC0;
389  bits<8> VSRC1;
390  
391  let Inst{8-0} = SRC0;
392  let Inst{16-9} = VSRC1;
393  let Inst{24-17} = VDST;
394  let Inst{30-25} = op;
395  let Inst{31} = 0x0; //encoding
396  
397  let EncodingType = 13; // SIInstrEncodingType::VOP2
398  let PostEncoderMethod = "VOPPostEncode";
399}
400
401class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
402    Enc64 <outs, ins, asm, pattern> {
403
404  bits<8> VDST;
405  bits<9> SRC0;
406  bits<9> SRC1;
407  bits<9> SRC2;
408  bits<3> ABS; 
409  bits<1> CLAMP;
410  bits<2> OMOD;
411  bits<3> NEG;
412
413  let Inst{7-0} = VDST;
414  let Inst{10-8} = ABS;
415  let Inst{11} = CLAMP;
416  let Inst{25-17} = op;
417  let Inst{31-26} = 0x34; //encoding
418  let Inst{40-32} = SRC0;
419  let Inst{49-41} = SRC1;
420  let Inst{58-50} = SRC2;
421  let Inst{60-59} = OMOD;
422  let Inst{63-61} = NEG;
423  
424  let EncodingType = 14; // SIInstrEncodingType::VOP3
425  let PostEncoderMethod = "VOPPostEncode";
426}
427
428class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
429    Enc32 <(outs VCCReg:$dst), ins, asm, pattern> {
430
431  bits<9> SRC0;
432  bits<8> VSRC1;
433
434  let Inst{8-0} = SRC0;
435  let Inst{16-9} = VSRC1;
436  let Inst{24-17} = op;
437  let Inst{31-25} = 0x3e;
438 
439  let EncodingType = 15; //SIInstrEncodingType::VOPC
440  let PostEncoderMethod = "VOPPostEncode";
441  let DisableEncoding = "$dst";
442}
443
444class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
445  op,
446  (outs VReg_128:$vdata),
447  (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
448       i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_128:$vaddr,
449       GPR4Align<SReg_256>:$srsrc, GPR4Align<SReg_128>:$ssamp),
450  asm,
451  []
452>; 
453
454class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
455  op,
456  (outs regClass:$dst),
457  (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
458       i1imm:$lds, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc, i1imm:$slc,
459       i1imm:$tfe, SReg_32:$soffset),
460  asm,
461  []> {
462  let mayLoad = 1;
463}
464
465class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
466  op,
467  (outs regClass:$dst),
468  (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
469       i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc,
470       i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
471  asm,
472  []> {
473  let mayLoad = 1;
474}
475
476class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
477  op,
478  (outs),
479  (ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
480   i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
481   GPR4Align<SReg_128>:$srsrc, i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
482  asm,
483  []> {
484  let mayStore = 1;
485}
486
487multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass,
488			ValueType vt> {
489  def _IMM : SMRD <
490              op,
491              (outs dstClass:$dst),
492              (ins SMRDmemri:$src0),
493              asm,
494              [(set (vt dstClass:$dst), (constant_load ADDR_Offset8:$src0))]
495  >;
496
497  def _SGPR : SMRD <
498              op,
499              (outs dstClass:$dst),
500              (ins SMRDmemrr:$src0),
501              asm,
502              [(set (vt dstClass:$dst), (constant_load ADDR_Reg:$src0))]
503  >;
504}
505
506multiclass SMRD_32 <bits<5> op, string asm, RegisterClass dstClass> {
507  defm _F32 : SMRD_Helper <op, asm, dstClass, f32>;
508  defm _I32 : SMRD_Helper <op, asm, dstClass, i32>;
509}
510
511include "SIInstrFormats.td"
512include "SIInstructions.td"
513