SIRegisterInfo.cpp revision 228a6641ccddaf24a993f827af1e97379785985a 
168043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)//===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
268043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)//
368043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)//                     The LLVM Compiler Infrastructure
468043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)//
568043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)// This file is distributed under the University of Illinois Open Source
668043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)// License. See LICENSE.TXT for details.
768043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)//
868043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)//===----------------------------------------------------------------------===//
968043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)//
1068043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)// This file contains the SI implementation of the TargetRegisterInfo class.
1168043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)//
1268043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)//===----------------------------------------------------------------------===//
1368043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)
1468043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)
1568043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)#include "SIRegisterInfo.h"
1668043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)#include "AMDGPUTargetMachine.h"
175d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)
185d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)using namespace llvm;
1968043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)
2068043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)SIRegisterInfo::SIRegisterInfo(AMDGPUTargetMachine &tm,
2168043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)    const TargetInstrInfo &tii)
2268043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles): AMDGPURegisterInfo(tm, tii),
2368043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)  TM(tm),
2468043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)  TII(tii)
2568043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)  { }
2668043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)
2768043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const
2868043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles){
2968043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)  BitVector Reserved(getNumRegs());
3068043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)  return Reserved;
315d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)}
3268043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)
3368043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)unsigned SIRegisterInfo::getBinaryCode(unsigned reg) const
3468043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles){
3568043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)  switch (reg) {
3668043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)    case AMDGPU::M0: return 124;
37    case AMDGPU::SREG_LIT_0: return 128;
38    default: return getHWRegNum(reg);
39  }
40}
41
42const TargetRegisterClass *
43SIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const
44{
45  switch (rc->getID()) {
46  case AMDGPU::GPRF32RegClassID:
47    return &AMDGPU::VReg_32RegClass;
48  default: return rc;
49  }
50}
51
52const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
53                                                                   MVT VT) const
54{
55  switch(VT.SimpleTy) {
56    default:
57    case MVT::i32: return &AMDGPU::VReg_32RegClass;
58  }
59}
60#include "SIRegisterGetHWRegNum.inc"
61