1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Tom Stellard <thomas.stellard@amd.com>
24 *
25 */
26
27#ifndef RADEON_LLVM_H
28#define RADEON_LLVM_H
29
30#include <llvm-c/Core.h>
31#include "gallivm/lp_bld_init.h"
32#include "gallivm/lp_bld_tgsi.h"
33
34#define RADEON_LLVM_MAX_INPUTS 16 * 4
35#define RADEON_LLVM_MAX_OUTPUTS 16 * 4
36#define RADEON_LLVM_MAX_BRANCH_DEPTH 16
37#define RADEON_LLVM_MAX_LOOP_DEPTH 16
38
39#define RADEON_LLVM_MAX_SYSTEM_VALUES 4
40
41struct radeon_llvm_branch {
42	LLVMBasicBlockRef endif_block;
43	LLVMBasicBlockRef if_block;
44	LLVMBasicBlockRef else_block;
45	unsigned has_else;
46};
47
48struct radeon_llvm_loop {
49	LLVMBasicBlockRef loop_block;
50	LLVMBasicBlockRef endloop_block;
51};
52
53struct radeon_llvm_context {
54
55	struct lp_build_tgsi_soa_context soa;
56
57	/*=== Front end configuration ===*/
58
59	/* Special Intrinsics */
60
61	/** Write to an output register: float store_output(float, i32) */
62	const char * store_output_intr;
63
64	/** Swizzle a vector value: <4 x float> swizzle(<4 x float>, i32)
65	 * The swizzle is an unsigned integer that encodes a TGSI_SWIZZLE_* value
66	 * in 2-bits.
67	 * Swizzle{0-1} = X Channel
68	 * Swizzle{2-3} = Y Channel
69	 * Swizzle{4-5} = Z Channel
70	 * Swizzle{6-7} = W Channel
71	 */
72	const char * swizzle_intr;
73
74	/* Instructions that are not described by any of the TGSI opcodes. */
75
76	/** This function is responsible for initilizing the inputs array and will be
77	  * called once for each input declared in the TGSI shader.
78	  */
79	void (*load_input)(struct radeon_llvm_context *,
80			unsigned input_index,
81			const struct tgsi_full_declaration *decl);
82
83	void (*load_system_value)(struct radeon_llvm_context *,
84			unsigned index,
85			const struct tgsi_full_declaration *decl);
86
87	/** User data to use with the callbacks */
88	void * userdata;
89
90	/** This array contains the input values for the shader.  Typically these
91	  * values will be in the form of a target intrinsic that will inform the
92	  * backend how to load the actual inputs to the shader.
93	  */
94	LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS];
95	LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS][TGSI_NUM_CHANNELS];
96	unsigned output_reg_count;
97
98	LLVMValueRef system_values[RADEON_LLVM_MAX_SYSTEM_VALUES];
99
100	unsigned reserved_reg_count;
101	/*=== Private Members ===*/
102
103	struct radeon_llvm_branch branch[RADEON_LLVM_MAX_BRANCH_DEPTH];
104	struct radeon_llvm_loop loop[RADEON_LLVM_MAX_LOOP_DEPTH];
105
106	unsigned branch_depth;
107	unsigned loop_depth;
108
109
110	LLVMValueRef main_fn;
111
112	struct gallivm_state gallivm;
113};
114
115static inline LLVMValueRef bitcast(
116		struct lp_build_tgsi_context * bld_base,
117		enum tgsi_opcode_type type,
118		LLVMValueRef value
119)
120{
121	LLVMBuilderRef builder = bld_base->base.gallivm->builder;
122	LLVMContextRef ctx = bld_base->base.gallivm->context;
123	LLVMTypeRef dst_type;
124
125	switch (type) {
126	case TGSI_TYPE_UNSIGNED:
127	case TGSI_TYPE_SIGNED:
128		dst_type = LLVMInt32TypeInContext(ctx);
129		break;
130	case TGSI_TYPE_UNTYPED:
131	case TGSI_TYPE_FLOAT:
132		dst_type = LLVMFloatTypeInContext(ctx);
133		break;
134	default:
135		dst_type = 0;
136		break;
137	}
138
139	if (dst_type)
140		return LLVMBuildBitCast(builder, value, dst_type, "");
141	else
142		return value;
143}
144
145
146void radeon_llvm_context_init(struct radeon_llvm_context * ctx);
147
148void radeon_llvm_dispose(struct radeon_llvm_context * ctx);
149
150inline static struct radeon_llvm_context * radeon_llvm_context(
151	struct lp_build_tgsi_context * bld_base)
152{
153	return (struct radeon_llvm_context*)bld_base;
154}
155
156unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan);
157
158void radeon_llvm_finalize_module(struct radeon_llvm_context * ctx);
159
160LLVMValueRef
161build_intrinsic(LLVMBuilderRef builder,
162		const char *name,
163		LLVMTypeRef ret_type,
164		LLVMValueRef *args,
165		unsigned num_args,
166		LLVMAttribute attr);
167
168void
169build_tgsi_intrinsic_nomem(
170		const struct lp_build_tgsi_action * action,
171		struct lp_build_tgsi_context * bld_base,
172		struct lp_build_emit_data * emit_data);
173
174
175
176#endif /* RADEON_LLVM_H */
177