evergreen_hw_context.c revision 708337e62e86cfb2df893f0733bb7c5a4938fab6 
1/*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 *      Jerome Glisse
25 */
26#include "r600.h"
27#include "r600_hw_context_priv.h"
28#include "radeonsi_pipe.h"
29#include "sid.h"
30#include "util/u_memory.h"
31#include <errno.h>
32
33int si_context_init(struct r600_context *ctx)
34{
35	int r;
36
37	LIST_INITHEAD(&ctx->active_query_list);
38
39	ctx->cs = ctx->ws->cs_create(ctx->ws);
40
41	ctx->max_db = 8;
42	return 0;
43}
44
45static inline void evergreen_context_ps_partial_flush(struct r600_context *ctx)
46{
47	struct radeon_winsys_cs *cs = ctx->cs;
48
49	if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
50		return;
51
52	cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
53	cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
54
55	ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
56}
57
58void si_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
59{
60	struct radeon_winsys_cs *cs = ctx->cs;
61	unsigned ndwords = 7;
62	uint32_t *pm4;
63	uint64_t va;
64
65	if (draw->indices) {
66		ndwords = 12;
67	}
68	if (ctx->num_cs_dw_queries_suspend)
69		ndwords += 6;
70
71	/* when increasing ndwords, bump the max limit too */
72	assert(ndwords <= SI_MAX_DRAW_CS_DWORDS);
73
74	/* queries need some special values
75	 * (this is non-zero if any query is active) */
76	if (ctx->num_cs_dw_queries_suspend) {
77		pm4 = &cs->buf[cs->cdw];
78		pm4[0] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
79		pm4[1] = (R_028004_DB_COUNT_CONTROL - SI_CONTEXT_REG_OFFSET) >> 2;
80		pm4[2] = S_028004_PERFECT_ZPASS_COUNTS(1);
81		pm4[3] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
82		pm4[4] = (R_02800C_DB_RENDER_OVERRIDE - SI_CONTEXT_REG_OFFSET) >> 2;
83		pm4[5] = draw->db_render_override | S_02800C_NOOP_CULL_DISABLE(1);
84		cs->cdw += 6;
85		ndwords -= 6;
86	}
87
88	/* draw packet */
89	pm4 = &cs->buf[cs->cdw];
90	pm4[0] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing);
91	pm4[1] = draw->vgt_index_type;
92	pm4[2] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing);
93	pm4[3] = draw->vgt_num_instances;
94	if (draw->indices) {
95		va = r600_resource_va(&ctx->screen->screen, (void*)draw->indices);
96		va += draw->indices_bo_offset;
97		pm4[4] = PKT3(PKT3_DRAW_INDEX_2, 4, ctx->predicate_drawing);
98		pm4[5] = (draw->indices->b.b.width0 - draw->indices_bo_offset) /
99			ctx->index_buffer.index_size;
100		pm4[6] = va;
101		pm4[7] = (va >> 32UL) & 0xFF;
102		pm4[8] = draw->vgt_num_indices;
103		pm4[9] = draw->vgt_draw_initiator;
104		pm4[10] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
105		pm4[11] = r600_context_bo_reloc(ctx, draw->indices, RADEON_USAGE_READ);
106	} else {
107		pm4[4] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing);
108		pm4[5] = draw->vgt_num_indices;
109		pm4[6] = draw->vgt_draw_initiator;
110	}
111	cs->cdw += ndwords;
112}
113
114void evergreen_flush_vgt_streamout(struct r600_context *ctx)
115{
116	struct radeon_winsys_cs *cs = ctx->cs;
117
118	cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0);
119	cs->buf[cs->cdw++] = (R_0084FC_CP_STRMOUT_CNTL - SI_CONFIG_REG_OFFSET) >> 2;
120	cs->buf[cs->cdw++] = 0;
121
122	cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
123	cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
124
125	cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
126	cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
127	cs->buf[cs->cdw++] = R_0084FC_CP_STRMOUT_CNTL >> 2;  /* register */
128	cs->buf[cs->cdw++] = 0;
129	cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* reference value */
130	cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* mask */
131	cs->buf[cs->cdw++] = 4; /* poll interval */
132}
133
134void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
135{
136	struct radeon_winsys_cs *cs = ctx->cs;
137
138	if (buffer_enable_bit) {
139		cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
140		cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
141		cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(1);
142
143		cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
144		cs->buf[cs->cdw++] = (R_028B98_VGT_STRMOUT_BUFFER_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
145		cs->buf[cs->cdw++] = S_028B98_STREAM_0_BUFFER_EN(buffer_enable_bit);
146	} else {
147		cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
148		cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
149		cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(0);
150	}
151}
152