radeonsi_pm4.h revision 862df0885aa04ef68319382fc2df27a7b68fc0dd
1424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)/* 25821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) * Copyright 2012 Advanced Micro Devices, Inc. 35821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) * 45821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) * Permission is hereby granted, free of charge, to any person obtaining a 5424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) * copy of this software and associated documentation files (the "Software"), 65821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) * to deal in the Software without restriction, including without limitation 75821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) * on the rights to use, copy, modify, merge, publish, distribute, sub 85821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) * license, and/or sell copies of the Software, and to permit persons to whom 9a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) * the Software is furnished to do so, subject to the following conditions: 105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) * 115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) * The above copyright notice and this permission notice (including the next 125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) * paragraph) shall be included in all copies or substantial portions of the 135c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu * Software. 145c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu * 155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 165821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) * USE OR OTHER DEALINGS IN THE SOFTWARE. 225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) * 235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) * Authors: 24effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch * Christian König <christian.koenig@amd.com> 255c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu */ 265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 27a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)#ifndef RADEONSI_PM4_H 28a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)#define RADEONSI_PM4_H 29a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 30a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)#include "../../winsys/radeon/drm/radeon_winsys.h" 31424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) 32424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)#define SI_PM4_MAX_DW 128 33424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)#define SI_PM4_MAX_BO 32 345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 35424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)// forward defines 365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)struct r600_context; 375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)struct si_pm4_state 395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles){ 40effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch /* PKT3_SET_*_REG handling */ 41effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch unsigned last_opcode; 42effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch unsigned last_reg; 43effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch unsigned last_pm4; 445821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 45a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /* flush flags for SURFACE_SYNC */ 46a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) uint32_t cp_coher_cntl; 47a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 48a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /* commands for the DE */ 49a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) unsigned ndw; 50a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) uint32_t pm4[SI_PM4_MAX_DW]; 51a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 52a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /* BO's referenced by this state */ 53a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) unsigned nbo; 54a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) struct si_resource *bo[SI_PM4_MAX_BO]; 55effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch enum radeon_bo_usage bo_usage[SI_PM4_MAX_BO]; 56effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch}; 57effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch 58a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode); 595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw); 601e9bf3e0803691d0a228da41fc608347b6db4340Torne (Richard Coles)void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate); 615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val); 635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)void si_pm4_add_bo(struct si_pm4_state *state, 645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) struct si_resource *bo, 655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) enum radeon_bo_usage usage); 665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)void si_pm4_inval_shader_cache(struct si_pm4_state *state); 685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)void si_pm4_inval_texture_cache(struct si_pm4_state *state); 695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)void si_pm4_inval_vertex_cache(struct si_pm4_state *state); 705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)void si_pm4_inval_fb_cache(struct si_pm4_state *state, unsigned nr_cbufs); 715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)void si_pm4_inval_zsbuf_cache(struct si_pm4_state *state); 725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)void si_pm4_free_state(struct r600_context *rctx, 74 struct si_pm4_state *state, 75 unsigned idx); 76unsigned si_pm4_dirty_dw(struct r600_context *rctx); 77void si_pm4_emit_dirty(struct r600_context *rctx); 78void si_pm4_reset_emitted(struct r600_context *rctx); 79 80#endif 81