si_state.c revision 9aacd5cc67ccbc3984bce6a0b40768a6cec2ec2d
1/* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Christian König <christian.koenig@amd.com> 25 */ 26 27#include "util/u_memory.h" 28#include "util/u_framebuffer.h" 29#include "util/u_blitter.h" 30#include "util/u_pack_color.h" 31#include "tgsi/tgsi_parse.h" 32#include "radeonsi_pipe.h" 33#include "radeonsi_shader.h" 34#include "si_state.h" 35#include "sid.h" 36 37/* 38 * inferred framebuffer and blender state 39 */ 40static void si_update_fb_blend_state(struct r600_context *rctx) 41{ 42 struct si_pm4_state *pm4; 43 struct si_state_blend *blend = rctx->queued.named.blend; 44 uint32_t mask; 45 46 if (blend == NULL) 47 return; 48 49 pm4 = CALLOC_STRUCT(si_pm4_state); 50 if (pm4 == NULL) 51 return; 52 53 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1; 54 mask &= blend->cb_target_mask; 55 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask); 56 57 si_pm4_set_state(rctx, fb_blend, pm4); 58} 59 60/* 61 * Blender functions 62 */ 63 64static uint32_t si_translate_blend_function(int blend_func) 65{ 66 switch (blend_func) { 67 case PIPE_BLEND_ADD: 68 return V_028780_COMB_DST_PLUS_SRC; 69 case PIPE_BLEND_SUBTRACT: 70 return V_028780_COMB_SRC_MINUS_DST; 71 case PIPE_BLEND_REVERSE_SUBTRACT: 72 return V_028780_COMB_DST_MINUS_SRC; 73 case PIPE_BLEND_MIN: 74 return V_028780_COMB_MIN_DST_SRC; 75 case PIPE_BLEND_MAX: 76 return V_028780_COMB_MAX_DST_SRC; 77 default: 78 R600_ERR("Unknown blend function %d\n", blend_func); 79 assert(0); 80 break; 81 } 82 return 0; 83} 84 85static uint32_t si_translate_blend_factor(int blend_fact) 86{ 87 switch (blend_fact) { 88 case PIPE_BLENDFACTOR_ONE: 89 return V_028780_BLEND_ONE; 90 case PIPE_BLENDFACTOR_SRC_COLOR: 91 return V_028780_BLEND_SRC_COLOR; 92 case PIPE_BLENDFACTOR_SRC_ALPHA: 93 return V_028780_BLEND_SRC_ALPHA; 94 case PIPE_BLENDFACTOR_DST_ALPHA: 95 return V_028780_BLEND_DST_ALPHA; 96 case PIPE_BLENDFACTOR_DST_COLOR: 97 return V_028780_BLEND_DST_COLOR; 98 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: 99 return V_028780_BLEND_SRC_ALPHA_SATURATE; 100 case PIPE_BLENDFACTOR_CONST_COLOR: 101 return V_028780_BLEND_CONSTANT_COLOR; 102 case PIPE_BLENDFACTOR_CONST_ALPHA: 103 return V_028780_BLEND_CONSTANT_ALPHA; 104 case PIPE_BLENDFACTOR_ZERO: 105 return V_028780_BLEND_ZERO; 106 case PIPE_BLENDFACTOR_INV_SRC_COLOR: 107 return V_028780_BLEND_ONE_MINUS_SRC_COLOR; 108 case PIPE_BLENDFACTOR_INV_SRC_ALPHA: 109 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA; 110 case PIPE_BLENDFACTOR_INV_DST_ALPHA: 111 return V_028780_BLEND_ONE_MINUS_DST_ALPHA; 112 case PIPE_BLENDFACTOR_INV_DST_COLOR: 113 return V_028780_BLEND_ONE_MINUS_DST_COLOR; 114 case PIPE_BLENDFACTOR_INV_CONST_COLOR: 115 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR; 116 case PIPE_BLENDFACTOR_INV_CONST_ALPHA: 117 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA; 118 case PIPE_BLENDFACTOR_SRC1_COLOR: 119 return V_028780_BLEND_SRC1_COLOR; 120 case PIPE_BLENDFACTOR_SRC1_ALPHA: 121 return V_028780_BLEND_SRC1_ALPHA; 122 case PIPE_BLENDFACTOR_INV_SRC1_COLOR: 123 return V_028780_BLEND_INV_SRC1_COLOR; 124 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: 125 return V_028780_BLEND_INV_SRC1_ALPHA; 126 default: 127 R600_ERR("Bad blend factor %d not supported!\n", blend_fact); 128 assert(0); 129 break; 130 } 131 return 0; 132} 133 134static void *si_create_blend_state(struct pipe_context *ctx, 135 const struct pipe_blend_state *state) 136{ 137 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend); 138 struct si_pm4_state *pm4 = &blend->pm4; 139 140 uint32_t color_control; 141 142 if (blend == NULL) 143 return NULL; 144 145 color_control = S_028808_MODE(V_028808_CB_NORMAL); 146 if (state->logicop_enable) { 147 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4)); 148 } else { 149 color_control |= S_028808_ROP3(0xcc); 150 } 151 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control); 152 153 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0); 154 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0); 155 156 blend->cb_target_mask = 0; 157 for (int i = 0; i < 8; i++) { 158 /* state->rt entries > 0 only written if independent blending */ 159 const int j = state->independent_blend_enable ? i : 0; 160 161 unsigned eqRGB = state->rt[j].rgb_func; 162 unsigned srcRGB = state->rt[j].rgb_src_factor; 163 unsigned dstRGB = state->rt[j].rgb_dst_factor; 164 unsigned eqA = state->rt[j].alpha_func; 165 unsigned srcA = state->rt[j].alpha_src_factor; 166 unsigned dstA = state->rt[j].alpha_dst_factor; 167 168 unsigned blend_cntl = 0; 169 170 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */ 171 blend->cb_target_mask |= state->rt[j].colormask << (4 * i); 172 173 if (!state->rt[j].blend_enable) { 174 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); 175 continue; 176 } 177 178 blend_cntl |= S_028780_ENABLE(1); 179 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB)); 180 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB)); 181 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB)); 182 183 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 184 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1); 185 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA)); 186 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA)); 187 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA)); 188 } 189 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); 190 } 191 192 return blend; 193} 194 195static void si_bind_blend_state(struct pipe_context *ctx, void *state) 196{ 197 struct r600_context *rctx = (struct r600_context *)ctx; 198 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state); 199 si_update_fb_blend_state(rctx); 200} 201 202static void si_delete_blend_state(struct pipe_context *ctx, void *state) 203{ 204 struct r600_context *rctx = (struct r600_context *)ctx; 205 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state); 206} 207 208static void si_set_blend_color(struct pipe_context *ctx, 209 const struct pipe_blend_color *state) 210{ 211 struct r600_context *rctx = (struct r600_context *)ctx; 212 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 213 214 if (pm4 == NULL) 215 return; 216 217 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0])); 218 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1])); 219 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2])); 220 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3])); 221 222 si_pm4_set_state(rctx, blend_color, pm4); 223} 224 225/* 226 * Clipping, scissors and viewport 227 */ 228 229static void si_set_clip_state(struct pipe_context *ctx, 230 const struct pipe_clip_state *state) 231{ 232 struct r600_context *rctx = (struct r600_context *)ctx; 233 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 234 235 if (pm4 == NULL) 236 return; 237 238 for (int i = 0; i < 6; i++) { 239 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16, 240 fui(state->ucp[i][0])); 241 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16, 242 fui(state->ucp[i][1])); 243 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16, 244 fui(state->ucp[i][2])); 245 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16, 246 fui(state->ucp[i][3])); 247 } 248 249 si_pm4_set_state(rctx, clip, pm4); 250} 251 252static void si_set_scissor_state(struct pipe_context *ctx, 253 const struct pipe_scissor_state *state) 254{ 255 struct r600_context *rctx = (struct r600_context *)ctx; 256 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 257 uint32_t tl, br; 258 259 if (pm4 == NULL) 260 return; 261 262 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny); 263 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy); 264 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl); 265 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br); 266 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl); 267 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br); 268 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl); 269 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br); 270 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl); 271 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br); 272 273 si_pm4_set_state(rctx, scissor, pm4); 274} 275 276static void si_set_viewport_state(struct pipe_context *ctx, 277 const struct pipe_viewport_state *state) 278{ 279 struct r600_context *rctx = (struct r600_context *)ctx; 280 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport); 281 struct si_pm4_state *pm4 = &viewport->pm4; 282 283 if (viewport == NULL) 284 return; 285 286 viewport->viewport = *state; 287 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000); 288 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000); 289 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000); 290 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0])); 291 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0])); 292 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1])); 293 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1])); 294 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2])); 295 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2])); 296 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F); 297 298 si_pm4_set_state(rctx, viewport, viewport); 299} 300 301/* 302 * inferred state between framebuffer and rasterizer 303 */ 304static void si_update_fb_rs_state(struct r600_context *rctx) 305{ 306 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer; 307 struct si_pm4_state *pm4; 308 unsigned offset_db_fmt_cntl = 0, depth; 309 float offset_units; 310 311 if (!rs || !rctx->framebuffer.zsbuf) 312 return; 313 314 offset_units = rctx->queued.named.rasterizer->offset_units; 315 switch (rctx->framebuffer.zsbuf->texture->format) { 316 case PIPE_FORMAT_Z24X8_UNORM: 317 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 318 depth = -24; 319 offset_units *= 2.0f; 320 break; 321 case PIPE_FORMAT_Z32_FLOAT: 322 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 323 depth = -23; 324 offset_units *= 1.0f; 325 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1); 326 break; 327 case PIPE_FORMAT_Z16_UNORM: 328 depth = -16; 329 offset_units *= 4.0f; 330 break; 331 default: 332 return; 333 } 334 335 pm4 = CALLOC_STRUCT(si_pm4_state); 336 /* FIXME some of those reg can be computed with cso */ 337 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth); 338 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 339 fui(rctx->queued.named.rasterizer->offset_scale)); 340 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units)); 341 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 342 fui(rctx->queued.named.rasterizer->offset_scale)); 343 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units)); 344 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl); 345 346 si_pm4_set_state(rctx, fb_rs, pm4); 347} 348 349/* 350 * Rasterizer 351 */ 352 353static uint32_t si_translate_fill(uint32_t func) 354{ 355 switch(func) { 356 case PIPE_POLYGON_MODE_FILL: 357 return V_028814_X_DRAW_TRIANGLES; 358 case PIPE_POLYGON_MODE_LINE: 359 return V_028814_X_DRAW_LINES; 360 case PIPE_POLYGON_MODE_POINT: 361 return V_028814_X_DRAW_POINTS; 362 default: 363 assert(0); 364 return V_028814_X_DRAW_POINTS; 365 } 366} 367 368static void *si_create_rs_state(struct pipe_context *ctx, 369 const struct pipe_rasterizer_state *state) 370{ 371 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer); 372 struct si_pm4_state *pm4 = &rs->pm4; 373 unsigned tmp; 374 unsigned prov_vtx = 1, polygon_dual_mode; 375 unsigned clip_rule; 376 float psize_min, psize_max; 377 378 if (rs == NULL) { 379 return NULL; 380 } 381 382 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL || 383 state->fill_back != PIPE_POLYGON_MODE_FILL); 384 385 if (state->flatshade_first) 386 prov_vtx = 0; 387 388 rs->flatshade = state->flatshade; 389 rs->sprite_coord_enable = state->sprite_coord_enable; 390 rs->pa_sc_line_stipple = state->line_stipple_enable ? 391 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | 392 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0; 393 rs->pa_su_sc_mode_cntl = 394 S_028814_PROVOKING_VTX_LAST(prov_vtx) | 395 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) | 396 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) | 397 S_028814_FACE(!state->front_ccw) | 398 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | 399 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | 400 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) | 401 S_028814_POLY_MODE(polygon_dual_mode) | 402 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) | 403 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)); 404 rs->pa_cl_clip_cntl = 405 S_028810_PS_UCP_MODE(3) | 406 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) | 407 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) | 408 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); 409 rs->pa_cl_vs_out_cntl = 410 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) | 411 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex); 412 413 clip_rule = state->scissor ? 0xAAAA : 0xFFFF; 414 415 /* offset */ 416 rs->offset_units = state->offset_units; 417 rs->offset_scale = state->offset_scale * 12.0f; 418 419 /* XXX: Flat shading hangs the GPU */ 420 tmp = S_0286D4_FLAT_SHADE_ENA(0); 421 if (state->sprite_coord_enable) { 422 tmp |= S_0286D4_PNT_SPRITE_ENA(1) | 423 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) | 424 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) | 425 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) | 426 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1); 427 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { 428 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1); 429 } 430 } 431 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp); 432 433 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000); 434 /* point size 12.4 fixed point */ 435 tmp = (unsigned)(state->point_size * 8.0); 436 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); 437 438 if (state->point_size_per_vertex) { 439 psize_min = util_get_min_point_size(state); 440 psize_max = 8192; 441 } else { 442 /* Force the point size to be as if the vertex output was disabled. */ 443 psize_min = state->point_size; 444 psize_max = state->point_size; 445 } 446 /* Divide by two, because 0.5 = 1 pixel. */ 447 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX, 448 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) | 449 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2))); 450 451 tmp = (unsigned)state->line_width * 8; 452 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp)); 453 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0, 454 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable)); 455 456 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, 0x00000400); 457 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL, 458 S_028BE4_PIX_CENTER(state->gl_rasterization_rules)); 459 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000); 460 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000); 461 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000); 462 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000); 463 464 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp)); 465 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule); 466 467 return rs; 468} 469 470static void si_bind_rs_state(struct pipe_context *ctx, void *state) 471{ 472 struct r600_context *rctx = (struct r600_context *)ctx; 473 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state; 474 475 if (state == NULL) 476 return; 477 478 // TODO 479 rctx->sprite_coord_enable = rs->sprite_coord_enable; 480 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple; 481 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl; 482 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl; 483 rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl; 484 485 si_pm4_bind_state(rctx, rasterizer, rs); 486 si_update_fb_rs_state(rctx); 487} 488 489static void si_delete_rs_state(struct pipe_context *ctx, void *state) 490{ 491 struct r600_context *rctx = (struct r600_context *)ctx; 492 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state); 493} 494 495/* 496 * infeered state between dsa and stencil ref 497 */ 498static void si_update_dsa_stencil_ref(struct r600_context *rctx) 499{ 500 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 501 struct pipe_stencil_ref *ref = &rctx->stencil_ref; 502 struct si_state_dsa *dsa = rctx->queued.named.dsa; 503 504 if (pm4 == NULL) 505 return; 506 507 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK, 508 S_028430_STENCILTESTVAL(ref->ref_value[0]) | 509 S_028430_STENCILMASK(dsa->valuemask[0]) | 510 S_028430_STENCILWRITEMASK(dsa->writemask[0])); 511 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF, 512 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) | 513 S_028434_STENCILMASK_BF(dsa->valuemask[1]) | 514 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1])); 515 516 si_pm4_set_state(rctx, dsa_stencil_ref, pm4); 517} 518 519static void si_set_pipe_stencil_ref(struct pipe_context *ctx, 520 const struct pipe_stencil_ref *state) 521{ 522 struct r600_context *rctx = (struct r600_context *)ctx; 523 rctx->stencil_ref = *state; 524 si_update_dsa_stencil_ref(rctx); 525} 526 527 528/* 529 * DSA 530 */ 531 532static uint32_t si_translate_stencil_op(int s_op) 533{ 534 switch (s_op) { 535 case PIPE_STENCIL_OP_KEEP: 536 return V_02842C_STENCIL_KEEP; 537 case PIPE_STENCIL_OP_ZERO: 538 return V_02842C_STENCIL_ZERO; 539 case PIPE_STENCIL_OP_REPLACE: 540 return V_02842C_STENCIL_REPLACE_TEST; 541 case PIPE_STENCIL_OP_INCR: 542 return V_02842C_STENCIL_ADD_CLAMP; 543 case PIPE_STENCIL_OP_DECR: 544 return V_02842C_STENCIL_SUB_CLAMP; 545 case PIPE_STENCIL_OP_INCR_WRAP: 546 return V_02842C_STENCIL_ADD_WRAP; 547 case PIPE_STENCIL_OP_DECR_WRAP: 548 return V_02842C_STENCIL_SUB_WRAP; 549 case PIPE_STENCIL_OP_INVERT: 550 return V_02842C_STENCIL_INVERT; 551 default: 552 R600_ERR("Unknown stencil op %d", s_op); 553 assert(0); 554 break; 555 } 556 return 0; 557} 558 559static void *si_create_dsa_state(struct pipe_context *ctx, 560 const struct pipe_depth_stencil_alpha_state *state) 561{ 562 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa); 563 struct si_pm4_state *pm4 = &dsa->pm4; 564 unsigned db_depth_control, /* alpha_test_control, */ alpha_ref; 565 unsigned db_render_override, db_render_control; 566 uint32_t db_stencil_control = 0; 567 568 if (dsa == NULL) { 569 return NULL; 570 } 571 572 dsa->valuemask[0] = state->stencil[0].valuemask; 573 dsa->valuemask[1] = state->stencil[1].valuemask; 574 dsa->writemask[0] = state->stencil[0].writemask; 575 dsa->writemask[1] = state->stencil[1].writemask; 576 577 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | 578 S_028800_Z_WRITE_ENABLE(state->depth.writemask) | 579 S_028800_ZFUNC(state->depth.func); 580 581 /* stencil */ 582 if (state->stencil[0].enabled) { 583 db_depth_control |= S_028800_STENCIL_ENABLE(1); 584 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); 585 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op)); 586 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op)); 587 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op)); 588 589 if (state->stencil[1].enabled) { 590 db_depth_control |= S_028800_BACKFACE_ENABLE(1); 591 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); 592 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op)); 593 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op)); 594 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op)); 595 } 596 } 597 598 /* alpha */ 599 //alpha_test_control = 0; 600 alpha_ref = 0; 601 if (state->alpha.enabled) { 602 //alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func); 603 //alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1); 604 alpha_ref = fui(state->alpha.ref_value); 605 } 606 dsa->alpha_ref = alpha_ref; 607 608 /* misc */ 609 db_render_control = 0; 610 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) | 611 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | 612 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE); 613 /* TODO db_render_override depends on query */ 614 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000); 615 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000); 616 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000); 617 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000); 618 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control); 619 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control); 620 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control); 621 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override); 622 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control); 623 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0); 624 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0); 625 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0); 626 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00); 627 dsa->db_render_override = db_render_override; 628 629 return dsa; 630} 631 632static void si_bind_dsa_state(struct pipe_context *ctx, void *state) 633{ 634 struct r600_context *rctx = (struct r600_context *)ctx; 635 struct si_state_dsa *dsa = state; 636 637 if (state == NULL) 638 return; 639 640 si_pm4_bind_state(rctx, dsa, dsa); 641 si_update_dsa_stencil_ref(rctx); 642 643 // TODO 644 rctx->alpha_ref = dsa->alpha_ref; 645 rctx->alpha_ref_dirty = true; 646} 647 648static void si_delete_dsa_state(struct pipe_context *ctx, void *state) 649{ 650 struct r600_context *rctx = (struct r600_context *)ctx; 651 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state); 652} 653 654static void *si_create_db_flush_dsa(struct r600_context *rctx) 655{ 656 struct pipe_depth_stencil_alpha_state dsa; 657 struct si_state_dsa *state; 658 659 memset(&dsa, 0, sizeof(dsa)); 660 661 state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa); 662 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL, 663 S_028000_DEPTH_COPY(1) | 664 S_028000_STENCIL_COPY(1) | 665 S_028000_COPY_CENTROID(1)); 666 return state; 667} 668 669/* 670 * format translation 671 */ 672static uint32_t si_translate_colorformat(enum pipe_format format) 673{ 674 switch (format) { 675 /* 8-bit buffers. */ 676 case PIPE_FORMAT_A8_UNORM: 677 case PIPE_FORMAT_A8_UINT: 678 case PIPE_FORMAT_A8_SINT: 679 case PIPE_FORMAT_I8_UNORM: 680 case PIPE_FORMAT_I8_UINT: 681 case PIPE_FORMAT_I8_SINT: 682 case PIPE_FORMAT_L8_UNORM: 683 case PIPE_FORMAT_L8_UINT: 684 case PIPE_FORMAT_L8_SINT: 685 case PIPE_FORMAT_L8_SRGB: 686 case PIPE_FORMAT_R8_UNORM: 687 case PIPE_FORMAT_R8_SNORM: 688 case PIPE_FORMAT_R8_UINT: 689 case PIPE_FORMAT_R8_SINT: 690 return V_028C70_COLOR_8; 691 692 /* 16-bit buffers. */ 693 case PIPE_FORMAT_B5G6R5_UNORM: 694 return V_028C70_COLOR_5_6_5; 695 696 case PIPE_FORMAT_B5G5R5A1_UNORM: 697 case PIPE_FORMAT_B5G5R5X1_UNORM: 698 return V_028C70_COLOR_1_5_5_5; 699 700 case PIPE_FORMAT_B4G4R4A4_UNORM: 701 case PIPE_FORMAT_B4G4R4X4_UNORM: 702 return V_028C70_COLOR_4_4_4_4; 703 704 case PIPE_FORMAT_L8A8_UNORM: 705 case PIPE_FORMAT_L8A8_UINT: 706 case PIPE_FORMAT_L8A8_SINT: 707 case PIPE_FORMAT_L8A8_SRGB: 708 case PIPE_FORMAT_R8G8_UNORM: 709 case PIPE_FORMAT_R8G8_UINT: 710 case PIPE_FORMAT_R8G8_SINT: 711 return V_028C70_COLOR_8_8; 712 713 case PIPE_FORMAT_Z16_UNORM: 714 case PIPE_FORMAT_R16_UNORM: 715 case PIPE_FORMAT_R16_UINT: 716 case PIPE_FORMAT_R16_SINT: 717 case PIPE_FORMAT_R16_FLOAT: 718 case PIPE_FORMAT_R16G16_FLOAT: 719 return V_028C70_COLOR_16; 720 721 /* 32-bit buffers. */ 722 case PIPE_FORMAT_A8B8G8R8_SRGB: 723 case PIPE_FORMAT_A8B8G8R8_UNORM: 724 case PIPE_FORMAT_A8R8G8B8_UNORM: 725 case PIPE_FORMAT_B8G8R8A8_SRGB: 726 case PIPE_FORMAT_B8G8R8A8_UNORM: 727 case PIPE_FORMAT_B8G8R8X8_UNORM: 728 case PIPE_FORMAT_R8G8B8A8_SNORM: 729 case PIPE_FORMAT_R8G8B8A8_UNORM: 730 case PIPE_FORMAT_R8G8B8X8_UNORM: 731 case PIPE_FORMAT_R8SG8SB8UX8U_NORM: 732 case PIPE_FORMAT_X8B8G8R8_UNORM: 733 case PIPE_FORMAT_X8R8G8B8_UNORM: 734 case PIPE_FORMAT_R8G8B8_UNORM: 735 case PIPE_FORMAT_R8G8B8A8_SSCALED: 736 case PIPE_FORMAT_R8G8B8A8_USCALED: 737 case PIPE_FORMAT_R8G8B8A8_SINT: 738 case PIPE_FORMAT_R8G8B8A8_UINT: 739 return V_028C70_COLOR_8_8_8_8; 740 741 case PIPE_FORMAT_R10G10B10A2_UNORM: 742 case PIPE_FORMAT_R10G10B10X2_SNORM: 743 case PIPE_FORMAT_B10G10R10A2_UNORM: 744 case PIPE_FORMAT_B10G10R10A2_UINT: 745 case PIPE_FORMAT_R10SG10SB10SA2U_NORM: 746 return V_028C70_COLOR_2_10_10_10; 747 748 case PIPE_FORMAT_Z24X8_UNORM: 749 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 750 return V_028C70_COLOR_8_24; 751 752 case PIPE_FORMAT_X8Z24_UNORM: 753 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 754 return V_028C70_COLOR_24_8; 755 756 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 757 return V_028C70_COLOR_X24_8_32_FLOAT; 758 759 case PIPE_FORMAT_R32_FLOAT: 760 case PIPE_FORMAT_Z32_FLOAT: 761 return V_028C70_COLOR_32; 762 763 case PIPE_FORMAT_R16G16_SSCALED: 764 case PIPE_FORMAT_R16G16_UNORM: 765 case PIPE_FORMAT_R16G16_UINT: 766 case PIPE_FORMAT_R16G16_SINT: 767 return V_028C70_COLOR_16_16; 768 769 case PIPE_FORMAT_R11G11B10_FLOAT: 770 return V_028C70_COLOR_10_11_11; 771 772 /* 64-bit buffers. */ 773 case PIPE_FORMAT_R16G16B16_USCALED: 774 case PIPE_FORMAT_R16G16B16_SSCALED: 775 case PIPE_FORMAT_R16G16B16A16_UINT: 776 case PIPE_FORMAT_R16G16B16A16_SINT: 777 case PIPE_FORMAT_R16G16B16A16_USCALED: 778 case PIPE_FORMAT_R16G16B16A16_SSCALED: 779 case PIPE_FORMAT_R16G16B16A16_UNORM: 780 case PIPE_FORMAT_R16G16B16A16_SNORM: 781 case PIPE_FORMAT_R16G16B16_FLOAT: 782 case PIPE_FORMAT_R16G16B16A16_FLOAT: 783 return V_028C70_COLOR_16_16_16_16; 784 785 case PIPE_FORMAT_R32G32_FLOAT: 786 case PIPE_FORMAT_R32G32_USCALED: 787 case PIPE_FORMAT_R32G32_SSCALED: 788 case PIPE_FORMAT_R32G32_SINT: 789 case PIPE_FORMAT_R32G32_UINT: 790 return V_028C70_COLOR_32_32; 791 792 /* 128-bit buffers. */ 793 case PIPE_FORMAT_R32G32B32A32_SNORM: 794 case PIPE_FORMAT_R32G32B32A32_UNORM: 795 case PIPE_FORMAT_R32G32B32A32_SSCALED: 796 case PIPE_FORMAT_R32G32B32A32_USCALED: 797 case PIPE_FORMAT_R32G32B32A32_SINT: 798 case PIPE_FORMAT_R32G32B32A32_UINT: 799 case PIPE_FORMAT_R32G32B32A32_FLOAT: 800 return V_028C70_COLOR_32_32_32_32; 801 802 /* YUV buffers. */ 803 case PIPE_FORMAT_UYVY: 804 case PIPE_FORMAT_YUYV: 805 /* 96-bit buffers. */ 806 case PIPE_FORMAT_R32G32B32_FLOAT: 807 /* 8-bit buffers. */ 808 case PIPE_FORMAT_L4A4_UNORM: 809 case PIPE_FORMAT_R4A4_UNORM: 810 case PIPE_FORMAT_A4R4_UNORM: 811 default: 812 return ~0U; /* Unsupported. */ 813 } 814} 815 816static uint32_t si_translate_colorswap(enum pipe_format format) 817{ 818 switch (format) { 819 /* 8-bit buffers. */ 820 case PIPE_FORMAT_L4A4_UNORM: 821 case PIPE_FORMAT_A4R4_UNORM: 822 return V_028C70_SWAP_ALT; 823 824 case PIPE_FORMAT_A8_UNORM: 825 case PIPE_FORMAT_A8_UINT: 826 case PIPE_FORMAT_A8_SINT: 827 case PIPE_FORMAT_R4A4_UNORM: 828 return V_028C70_SWAP_ALT_REV; 829 case PIPE_FORMAT_I8_UNORM: 830 case PIPE_FORMAT_L8_UNORM: 831 case PIPE_FORMAT_I8_UINT: 832 case PIPE_FORMAT_I8_SINT: 833 case PIPE_FORMAT_L8_UINT: 834 case PIPE_FORMAT_L8_SINT: 835 case PIPE_FORMAT_L8_SRGB: 836 case PIPE_FORMAT_R8_UNORM: 837 case PIPE_FORMAT_R8_SNORM: 838 case PIPE_FORMAT_R8_UINT: 839 case PIPE_FORMAT_R8_SINT: 840 return V_028C70_SWAP_STD; 841 842 /* 16-bit buffers. */ 843 case PIPE_FORMAT_B5G6R5_UNORM: 844 return V_028C70_SWAP_STD_REV; 845 846 case PIPE_FORMAT_B5G5R5A1_UNORM: 847 case PIPE_FORMAT_B5G5R5X1_UNORM: 848 return V_028C70_SWAP_ALT; 849 850 case PIPE_FORMAT_B4G4R4A4_UNORM: 851 case PIPE_FORMAT_B4G4R4X4_UNORM: 852 return V_028C70_SWAP_ALT; 853 854 case PIPE_FORMAT_Z16_UNORM: 855 return V_028C70_SWAP_STD; 856 857 case PIPE_FORMAT_L8A8_UNORM: 858 case PIPE_FORMAT_L8A8_UINT: 859 case PIPE_FORMAT_L8A8_SINT: 860 case PIPE_FORMAT_L8A8_SRGB: 861 return V_028C70_SWAP_ALT; 862 case PIPE_FORMAT_R8G8_UNORM: 863 case PIPE_FORMAT_R8G8_UINT: 864 case PIPE_FORMAT_R8G8_SINT: 865 return V_028C70_SWAP_STD; 866 867 case PIPE_FORMAT_R16_UNORM: 868 case PIPE_FORMAT_R16_UINT: 869 case PIPE_FORMAT_R16_SINT: 870 case PIPE_FORMAT_R16_FLOAT: 871 return V_028C70_SWAP_STD; 872 873 /* 32-bit buffers. */ 874 case PIPE_FORMAT_A8B8G8R8_SRGB: 875 return V_028C70_SWAP_STD_REV; 876 case PIPE_FORMAT_B8G8R8A8_SRGB: 877 return V_028C70_SWAP_ALT; 878 879 case PIPE_FORMAT_B8G8R8A8_UNORM: 880 case PIPE_FORMAT_B8G8R8X8_UNORM: 881 return V_028C70_SWAP_ALT; 882 883 case PIPE_FORMAT_A8R8G8B8_UNORM: 884 case PIPE_FORMAT_X8R8G8B8_UNORM: 885 return V_028C70_SWAP_ALT_REV; 886 case PIPE_FORMAT_R8G8B8A8_SNORM: 887 case PIPE_FORMAT_R8G8B8A8_UNORM: 888 case PIPE_FORMAT_R8G8B8A8_SSCALED: 889 case PIPE_FORMAT_R8G8B8A8_USCALED: 890 case PIPE_FORMAT_R8G8B8A8_SINT: 891 case PIPE_FORMAT_R8G8B8A8_UINT: 892 case PIPE_FORMAT_R8G8B8X8_UNORM: 893 return V_028C70_SWAP_STD; 894 895 case PIPE_FORMAT_A8B8G8R8_UNORM: 896 case PIPE_FORMAT_X8B8G8R8_UNORM: 897 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */ 898 return V_028C70_SWAP_STD_REV; 899 900 case PIPE_FORMAT_Z24X8_UNORM: 901 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 902 return V_028C70_SWAP_STD; 903 904 case PIPE_FORMAT_X8Z24_UNORM: 905 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 906 return V_028C70_SWAP_STD; 907 908 case PIPE_FORMAT_R10G10B10A2_UNORM: 909 case PIPE_FORMAT_R10G10B10X2_SNORM: 910 case PIPE_FORMAT_R10SG10SB10SA2U_NORM: 911 return V_028C70_SWAP_STD; 912 913 case PIPE_FORMAT_B10G10R10A2_UNORM: 914 case PIPE_FORMAT_B10G10R10A2_UINT: 915 return V_028C70_SWAP_ALT; 916 917 case PIPE_FORMAT_R11G11B10_FLOAT: 918 case PIPE_FORMAT_R32_FLOAT: 919 case PIPE_FORMAT_R32_UINT: 920 case PIPE_FORMAT_R32_SINT: 921 case PIPE_FORMAT_Z32_FLOAT: 922 case PIPE_FORMAT_R16G16_FLOAT: 923 case PIPE_FORMAT_R16G16_UNORM: 924 case PIPE_FORMAT_R16G16_UINT: 925 case PIPE_FORMAT_R16G16_SINT: 926 return V_028C70_SWAP_STD; 927 928 /* 64-bit buffers. */ 929 case PIPE_FORMAT_R32G32_FLOAT: 930 case PIPE_FORMAT_R32G32_UINT: 931 case PIPE_FORMAT_R32G32_SINT: 932 case PIPE_FORMAT_R16G16B16A16_UNORM: 933 case PIPE_FORMAT_R16G16B16A16_SNORM: 934 case PIPE_FORMAT_R16G16B16A16_USCALED: 935 case PIPE_FORMAT_R16G16B16A16_SSCALED: 936 case PIPE_FORMAT_R16G16B16A16_UINT: 937 case PIPE_FORMAT_R16G16B16A16_SINT: 938 case PIPE_FORMAT_R16G16B16A16_FLOAT: 939 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 940 941 /* 128-bit buffers. */ 942 case PIPE_FORMAT_R32G32B32A32_FLOAT: 943 case PIPE_FORMAT_R32G32B32A32_SNORM: 944 case PIPE_FORMAT_R32G32B32A32_UNORM: 945 case PIPE_FORMAT_R32G32B32A32_SSCALED: 946 case PIPE_FORMAT_R32G32B32A32_USCALED: 947 case PIPE_FORMAT_R32G32B32A32_SINT: 948 case PIPE_FORMAT_R32G32B32A32_UINT: 949 return V_028C70_SWAP_STD; 950 default: 951 R600_ERR("unsupported colorswap format %d\n", format); 952 return ~0U; 953 } 954 return ~0U; 955} 956 957static uint32_t si_colorformat_endian_swap(uint32_t colorformat) 958{ 959 if (R600_BIG_ENDIAN) { 960 switch(colorformat) { 961 /* 8-bit buffers. */ 962 case V_028C70_COLOR_8: 963 return V_028C70_ENDIAN_NONE; 964 965 /* 16-bit buffers. */ 966 case V_028C70_COLOR_5_6_5: 967 case V_028C70_COLOR_1_5_5_5: 968 case V_028C70_COLOR_4_4_4_4: 969 case V_028C70_COLOR_16: 970 case V_028C70_COLOR_8_8: 971 return V_028C70_ENDIAN_8IN16; 972 973 /* 32-bit buffers. */ 974 case V_028C70_COLOR_8_8_8_8: 975 case V_028C70_COLOR_2_10_10_10: 976 case V_028C70_COLOR_8_24: 977 case V_028C70_COLOR_24_8: 978 case V_028C70_COLOR_16_16: 979 return V_028C70_ENDIAN_8IN32; 980 981 /* 64-bit buffers. */ 982 case V_028C70_COLOR_16_16_16_16: 983 return V_028C70_ENDIAN_8IN16; 984 985 case V_028C70_COLOR_32_32: 986 return V_028C70_ENDIAN_8IN32; 987 988 /* 128-bit buffers. */ 989 case V_028C70_COLOR_32_32_32_32: 990 return V_028C70_ENDIAN_8IN32; 991 default: 992 return V_028C70_ENDIAN_NONE; /* Unsupported. */ 993 } 994 } else { 995 return V_028C70_ENDIAN_NONE; 996 } 997} 998 999static uint32_t si_translate_dbformat(enum pipe_format format) 1000{ 1001 switch (format) { 1002 case PIPE_FORMAT_Z16_UNORM: 1003 return V_028040_Z_16; 1004 case PIPE_FORMAT_Z24X8_UNORM: 1005 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 1006 return V_028040_Z_24; /* XXX no longer supported on SI */ 1007 case PIPE_FORMAT_Z32_FLOAT: 1008 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 1009 return V_028040_Z_32_FLOAT; 1010 default: 1011 return ~0U; 1012 } 1013} 1014 1015/* 1016 * Texture translation 1017 */ 1018 1019static uint32_t si_translate_texformat(struct pipe_screen *screen, 1020 enum pipe_format format, 1021 const struct util_format_description *desc, 1022 int first_non_void) 1023{ 1024 boolean uniform = TRUE; 1025 int i; 1026 1027 /* Colorspace (return non-RGB formats directly). */ 1028 switch (desc->colorspace) { 1029 /* Depth stencil formats */ 1030 case UTIL_FORMAT_COLORSPACE_ZS: 1031 switch (format) { 1032 case PIPE_FORMAT_Z16_UNORM: 1033 return V_008F14_IMG_DATA_FORMAT_16; 1034 case PIPE_FORMAT_X24S8_UINT: 1035 case PIPE_FORMAT_Z24X8_UNORM: 1036 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 1037 return V_008F14_IMG_DATA_FORMAT_24_8; 1038 case PIPE_FORMAT_S8X24_UINT: 1039 case PIPE_FORMAT_X8Z24_UNORM: 1040 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 1041 return V_008F14_IMG_DATA_FORMAT_8_24; 1042 case PIPE_FORMAT_S8_UINT: 1043 return V_008F14_IMG_DATA_FORMAT_8; 1044 case PIPE_FORMAT_Z32_FLOAT: 1045 return V_008F14_IMG_DATA_FORMAT_32; 1046 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 1047 return V_008F14_IMG_DATA_FORMAT_X24_8_32; 1048 default: 1049 goto out_unknown; 1050 } 1051 1052 case UTIL_FORMAT_COLORSPACE_YUV: 1053 goto out_unknown; /* TODO */ 1054 1055 case UTIL_FORMAT_COLORSPACE_SRGB: 1056 break; 1057 1058 default: 1059 break; 1060 } 1061 1062 /* TODO compressed formats */ 1063 1064 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) { 1065 return V_008F14_IMG_DATA_FORMAT_5_9_9_9; 1066 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) { 1067 return V_008F14_IMG_DATA_FORMAT_10_11_11; 1068 } 1069 1070 /* R8G8Bx_SNORM - TODO CxV8U8 */ 1071 1072 /* See whether the components are of the same size. */ 1073 for (i = 1; i < desc->nr_channels; i++) { 1074 uniform = uniform && desc->channel[0].size == desc->channel[i].size; 1075 } 1076 1077 /* Non-uniform formats. */ 1078 if (!uniform) { 1079 switch(desc->nr_channels) { 1080 case 3: 1081 if (desc->channel[0].size == 5 && 1082 desc->channel[1].size == 6 && 1083 desc->channel[2].size == 5) { 1084 return V_008F14_IMG_DATA_FORMAT_5_6_5; 1085 } 1086 goto out_unknown; 1087 case 4: 1088 if (desc->channel[0].size == 5 && 1089 desc->channel[1].size == 5 && 1090 desc->channel[2].size == 5 && 1091 desc->channel[3].size == 1) { 1092 return V_008F14_IMG_DATA_FORMAT_1_5_5_5; 1093 } 1094 if (desc->channel[0].size == 10 && 1095 desc->channel[1].size == 10 && 1096 desc->channel[2].size == 10 && 1097 desc->channel[3].size == 2) { 1098 return V_008F14_IMG_DATA_FORMAT_2_10_10_10; 1099 } 1100 goto out_unknown; 1101 } 1102 goto out_unknown; 1103 } 1104 1105 if (first_non_void < 0 || first_non_void > 3) 1106 goto out_unknown; 1107 1108 /* uniform formats */ 1109 switch (desc->channel[first_non_void].size) { 1110 case 4: 1111 switch (desc->nr_channels) { 1112 case 2: 1113 return V_008F14_IMG_DATA_FORMAT_4_4; 1114 case 4: 1115 return V_008F14_IMG_DATA_FORMAT_4_4_4_4; 1116 } 1117 break; 1118 case 8: 1119 switch (desc->nr_channels) { 1120 case 1: 1121 return V_008F14_IMG_DATA_FORMAT_8; 1122 case 2: 1123 return V_008F14_IMG_DATA_FORMAT_8_8; 1124 case 4: 1125 return V_008F14_IMG_DATA_FORMAT_8_8_8_8; 1126 } 1127 break; 1128 case 16: 1129 switch (desc->nr_channels) { 1130 case 1: 1131 return V_008F14_IMG_DATA_FORMAT_16; 1132 case 2: 1133 return V_008F14_IMG_DATA_FORMAT_16_16; 1134 case 4: 1135 return V_008F14_IMG_DATA_FORMAT_16_16_16_16; 1136 } 1137 break; 1138 case 32: 1139 switch (desc->nr_channels) { 1140 case 1: 1141 return V_008F14_IMG_DATA_FORMAT_32; 1142 case 2: 1143 return V_008F14_IMG_DATA_FORMAT_32_32; 1144 case 3: 1145 return V_008F14_IMG_DATA_FORMAT_32_32_32; 1146 case 4: 1147 return V_008F14_IMG_DATA_FORMAT_32_32_32_32; 1148 } 1149 } 1150 1151out_unknown: 1152 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */ 1153 return ~0; 1154} 1155 1156static unsigned si_tex_wrap(unsigned wrap) 1157{ 1158 switch (wrap) { 1159 default: 1160 case PIPE_TEX_WRAP_REPEAT: 1161 return V_008F30_SQ_TEX_WRAP; 1162 case PIPE_TEX_WRAP_CLAMP: 1163 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER; 1164 case PIPE_TEX_WRAP_CLAMP_TO_EDGE: 1165 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL; 1166 case PIPE_TEX_WRAP_CLAMP_TO_BORDER: 1167 return V_008F30_SQ_TEX_CLAMP_BORDER; 1168 case PIPE_TEX_WRAP_MIRROR_REPEAT: 1169 return V_008F30_SQ_TEX_MIRROR; 1170 case PIPE_TEX_WRAP_MIRROR_CLAMP: 1171 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER; 1172 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: 1173 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL; 1174 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: 1175 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER; 1176 } 1177} 1178 1179static unsigned si_tex_filter(unsigned filter) 1180{ 1181 switch (filter) { 1182 default: 1183 case PIPE_TEX_FILTER_NEAREST: 1184 return V_008F38_SQ_TEX_XY_FILTER_POINT; 1185 case PIPE_TEX_FILTER_LINEAR: 1186 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR; 1187 } 1188} 1189 1190static unsigned si_tex_mipfilter(unsigned filter) 1191{ 1192 switch (filter) { 1193 case PIPE_TEX_MIPFILTER_NEAREST: 1194 return V_008F38_SQ_TEX_Z_FILTER_POINT; 1195 case PIPE_TEX_MIPFILTER_LINEAR: 1196 return V_008F38_SQ_TEX_Z_FILTER_LINEAR; 1197 default: 1198 case PIPE_TEX_MIPFILTER_NONE: 1199 return V_008F38_SQ_TEX_Z_FILTER_NONE; 1200 } 1201} 1202 1203static unsigned si_tex_compare(unsigned compare) 1204{ 1205 switch (compare) { 1206 default: 1207 case PIPE_FUNC_NEVER: 1208 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER; 1209 case PIPE_FUNC_LESS: 1210 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS; 1211 case PIPE_FUNC_EQUAL: 1212 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL; 1213 case PIPE_FUNC_LEQUAL: 1214 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL; 1215 case PIPE_FUNC_GREATER: 1216 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER; 1217 case PIPE_FUNC_NOTEQUAL: 1218 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL; 1219 case PIPE_FUNC_GEQUAL: 1220 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL; 1221 case PIPE_FUNC_ALWAYS: 1222 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS; 1223 } 1224} 1225 1226static unsigned si_tex_dim(unsigned dim) 1227{ 1228 switch (dim) { 1229 default: 1230 case PIPE_TEXTURE_1D: 1231 return V_008F1C_SQ_RSRC_IMG_1D; 1232 case PIPE_TEXTURE_1D_ARRAY: 1233 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY; 1234 case PIPE_TEXTURE_2D: 1235 case PIPE_TEXTURE_RECT: 1236 return V_008F1C_SQ_RSRC_IMG_2D; 1237 case PIPE_TEXTURE_2D_ARRAY: 1238 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY; 1239 case PIPE_TEXTURE_3D: 1240 return V_008F1C_SQ_RSRC_IMG_3D; 1241 case PIPE_TEXTURE_CUBE: 1242 return V_008F1C_SQ_RSRC_IMG_CUBE; 1243 } 1244} 1245 1246/* 1247 * Format support testing 1248 */ 1249 1250static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format) 1251{ 1252 return si_translate_texformat(screen, format, util_format_description(format), 1253 util_format_get_first_non_void_channel(format)) != ~0U; 1254} 1255 1256static uint32_t si_translate_vertexformat(struct pipe_screen *screen, 1257 enum pipe_format format, 1258 const struct util_format_description *desc, 1259 int first_non_void) 1260{ 1261 unsigned type = desc->channel[first_non_void].type; 1262 int i; 1263 1264 if (type == UTIL_FORMAT_TYPE_FIXED) 1265 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1266 1267 /* See whether the components are of the same size. */ 1268 for (i = 0; i < desc->nr_channels; i++) { 1269 if (desc->channel[first_non_void].size != desc->channel[i].size) 1270 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1271 } 1272 1273 switch (desc->channel[first_non_void].size) { 1274 case 8: 1275 switch (desc->nr_channels) { 1276 case 1: 1277 return V_008F0C_BUF_DATA_FORMAT_8; 1278 case 2: 1279 return V_008F0C_BUF_DATA_FORMAT_8_8; 1280 case 3: 1281 case 4: 1282 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8; 1283 } 1284 break; 1285 case 16: 1286 switch (desc->nr_channels) { 1287 case 1: 1288 return V_008F0C_BUF_DATA_FORMAT_16; 1289 case 2: 1290 return V_008F0C_BUF_DATA_FORMAT_16_16; 1291 case 3: 1292 case 4: 1293 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16; 1294 } 1295 break; 1296 case 32: 1297 if (type != UTIL_FORMAT_TYPE_FLOAT) 1298 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1299 1300 switch (desc->nr_channels) { 1301 case 1: 1302 return V_008F0C_BUF_DATA_FORMAT_32; 1303 case 2: 1304 return V_008F0C_BUF_DATA_FORMAT_32_32; 1305 case 3: 1306 return V_008F0C_BUF_DATA_FORMAT_32_32_32; 1307 case 4: 1308 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32; 1309 } 1310 break; 1311 } 1312 1313 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1314} 1315 1316static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format) 1317{ 1318 const struct util_format_description *desc; 1319 int first_non_void; 1320 unsigned data_format; 1321 1322 desc = util_format_description(format); 1323 first_non_void = util_format_get_first_non_void_channel(format); 1324 data_format = si_translate_vertexformat(screen, format, desc, first_non_void); 1325 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID; 1326} 1327 1328static bool si_is_colorbuffer_format_supported(enum pipe_format format) 1329{ 1330 return si_translate_colorformat(format) != ~0U && 1331 si_translate_colorswap(format) != ~0U; 1332} 1333 1334static bool si_is_zs_format_supported(enum pipe_format format) 1335{ 1336 return si_translate_dbformat(format) != ~0U; 1337} 1338 1339bool si_is_format_supported(struct pipe_screen *screen, 1340 enum pipe_format format, 1341 enum pipe_texture_target target, 1342 unsigned sample_count, 1343 unsigned usage) 1344{ 1345 unsigned retval = 0; 1346 1347 if (target >= PIPE_MAX_TEXTURE_TYPES) { 1348 R600_ERR("r600: unsupported texture type %d\n", target); 1349 return FALSE; 1350 } 1351 1352 if (!util_format_is_supported(format, usage)) 1353 return FALSE; 1354 1355 /* Multisample */ 1356 if (sample_count > 1) 1357 return FALSE; 1358 1359 if ((usage & PIPE_BIND_SAMPLER_VIEW) && 1360 si_is_sampler_format_supported(screen, format)) { 1361 retval |= PIPE_BIND_SAMPLER_VIEW; 1362 } 1363 1364 if ((usage & (PIPE_BIND_RENDER_TARGET | 1365 PIPE_BIND_DISPLAY_TARGET | 1366 PIPE_BIND_SCANOUT | 1367 PIPE_BIND_SHARED)) && 1368 si_is_colorbuffer_format_supported(format)) { 1369 retval |= usage & 1370 (PIPE_BIND_RENDER_TARGET | 1371 PIPE_BIND_DISPLAY_TARGET | 1372 PIPE_BIND_SCANOUT | 1373 PIPE_BIND_SHARED); 1374 } 1375 1376 if ((usage & PIPE_BIND_DEPTH_STENCIL) && 1377 si_is_zs_format_supported(format)) { 1378 retval |= PIPE_BIND_DEPTH_STENCIL; 1379 } 1380 1381 if ((usage & PIPE_BIND_VERTEX_BUFFER) && 1382 si_is_vertex_format_supported(screen, format)) { 1383 retval |= PIPE_BIND_VERTEX_BUFFER; 1384 } 1385 1386 if (usage & PIPE_BIND_TRANSFER_READ) 1387 retval |= PIPE_BIND_TRANSFER_READ; 1388 if (usage & PIPE_BIND_TRANSFER_WRITE) 1389 retval |= PIPE_BIND_TRANSFER_WRITE; 1390 1391 return retval == usage; 1392} 1393 1394/* 1395 * framebuffer handling 1396 */ 1397 1398static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4, 1399 const struct pipe_framebuffer_state *state, int cb) 1400{ 1401 struct r600_resource_texture *rtex; 1402 struct r600_surface *surf; 1403 unsigned level = state->cbufs[cb]->u.tex.level; 1404 unsigned pitch, slice; 1405 unsigned color_info, color_attrib; 1406 unsigned format, swap, ntype, endian; 1407 uint64_t offset; 1408 unsigned blocksize; 1409 const struct util_format_description *desc; 1410 int i; 1411 unsigned blend_clamp = 0, blend_bypass = 0; 1412 1413 surf = (struct r600_surface *)state->cbufs[cb]; 1414 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture; 1415 blocksize = util_format_get_blocksize(rtex->real_format); 1416 1417 if (rtex->depth) 1418 rctx->have_depth_fb = TRUE; 1419 1420 if (rtex->depth && !rtex->is_flushing_texture) { 1421 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE); 1422 rtex = rtex->flushed_depth_texture; 1423 } 1424 1425 offset = rtex->surface.level[level].offset; 1426 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { 1427 offset += rtex->surface.level[level].slice_size * 1428 state->cbufs[cb]->u.tex.first_layer; 1429 } 1430 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1; 1431 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1432 if (slice) { 1433 slice = slice - 1; 1434 } 1435 1436 color_attrib = S_028C74_TILE_MODE_INDEX(8); 1437 switch (rtex->surface.level[level].mode) { 1438 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1439 color_attrib = S_028C74_TILE_MODE_INDEX(8); 1440 break; 1441 case RADEON_SURF_MODE_1D: 1442 color_attrib = S_028C74_TILE_MODE_INDEX(9); 1443 break; 1444 case RADEON_SURF_MODE_2D: 1445 if (rtex->resource.b.b.bind & PIPE_BIND_SCANOUT) { 1446 switch (blocksize) { 1447 case 1: 1448 color_attrib = S_028C74_TILE_MODE_INDEX(10); 1449 break; 1450 case 2: 1451 color_attrib = S_028C74_TILE_MODE_INDEX(11); 1452 break; 1453 case 4: 1454 color_attrib = S_028C74_TILE_MODE_INDEX(12); 1455 break; 1456 } 1457 break; 1458 } else switch (blocksize) { 1459 case 1: 1460 color_attrib = S_028C74_TILE_MODE_INDEX(14); 1461 break; 1462 case 2: 1463 color_attrib = S_028C74_TILE_MODE_INDEX(15); 1464 break; 1465 case 4: 1466 color_attrib = S_028C74_TILE_MODE_INDEX(16); 1467 break; 1468 case 8: 1469 color_attrib = S_028C74_TILE_MODE_INDEX(17); 1470 break; 1471 default: 1472 color_attrib = S_028C74_TILE_MODE_INDEX(13); 1473 } 1474 break; 1475 } 1476 1477 desc = util_format_description(surf->base.format); 1478 for (i = 0; i < 4; i++) { 1479 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 1480 break; 1481 } 1482 } 1483 if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) { 1484 ntype = V_028C70_NUMBER_FLOAT; 1485 } else { 1486 ntype = V_028C70_NUMBER_UNORM; 1487 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) 1488 ntype = V_028C70_NUMBER_SRGB; 1489 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 1490 if (desc->channel[i].normalized) 1491 ntype = V_028C70_NUMBER_SNORM; 1492 else if (desc->channel[i].pure_integer) 1493 ntype = V_028C70_NUMBER_SINT; 1494 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) { 1495 if (desc->channel[i].normalized) 1496 ntype = V_028C70_NUMBER_UNORM; 1497 else if (desc->channel[i].pure_integer) 1498 ntype = V_028C70_NUMBER_UINT; 1499 } 1500 } 1501 1502 format = si_translate_colorformat(surf->base.format); 1503 swap = si_translate_colorswap(surf->base.format); 1504 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) { 1505 endian = V_028C70_ENDIAN_NONE; 1506 } else { 1507 endian = si_colorformat_endian_swap(format); 1508 } 1509 1510 /* blend clamp should be set for all NORM/SRGB types */ 1511 if (ntype == V_028C70_NUMBER_UNORM || 1512 ntype == V_028C70_NUMBER_SNORM || 1513 ntype == V_028C70_NUMBER_SRGB) 1514 blend_clamp = 1; 1515 1516 /* set blend bypass according to docs if SINT/UINT or 1517 8/24 COLOR variants */ 1518 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT || 1519 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 || 1520 format == V_028C70_COLOR_X24_8_32_FLOAT) { 1521 blend_clamp = 0; 1522 blend_bypass = 1; 1523 } 1524 1525 color_info = S_028C70_FORMAT(format) | 1526 S_028C70_COMP_SWAP(swap) | 1527 S_028C70_BLEND_CLAMP(blend_clamp) | 1528 S_028C70_BLEND_BYPASS(blend_bypass) | 1529 S_028C70_NUMBER_TYPE(ntype) | 1530 S_028C70_ENDIAN(endian); 1531 1532 rctx->alpha_ref_dirty = true; 1533 1534 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture); 1535 offset >>= 8; 1536 1537 /* FIXME handle enabling of CB beyond BASE8 which has different offset */ 1538 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE); 1539 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset); 1540 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch)); 1541 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice)); 1542 1543 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { 1544 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000); 1545 } else { 1546 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 1547 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) | 1548 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer)); 1549 } 1550 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info); 1551 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib); 1552} 1553 1554static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4, 1555 const struct pipe_framebuffer_state *state) 1556{ 1557 struct r600_resource_texture *rtex; 1558 struct r600_surface *surf; 1559 unsigned level, pitch, slice, format; 1560 uint32_t z_info, s_info; 1561 uint64_t z_offs, s_offs; 1562 1563 if (state->zsbuf == NULL) { 1564 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0); 1565 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0); 1566 return; 1567 } 1568 1569 surf = (struct r600_surface *)state->zsbuf; 1570 level = surf->base.u.tex.level; 1571 rtex = (struct r600_resource_texture*)surf->base.texture; 1572 1573 format = si_translate_dbformat(rtex->real_format); 1574 1575 z_offs = r600_resource_va(rctx->context.screen, surf->base.texture); 1576 z_offs += rtex->surface.level[level].offset; 1577 1578 s_offs = r600_resource_va(rctx->context.screen, surf->base.texture); 1579 s_offs += rtex->surface.stencil_offset; 1580 z_offs += rtex->surface.level[level].offset / 4; 1581 1582 z_offs >>= 8; 1583 s_offs >>= 8; 1584 1585 pitch = (rtex->surface.level[level].nblk_x / 8) - 1; 1586 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1587 if (slice) { 1588 slice = slice - 1; 1589 } 1590 1591 z_info = S_028040_FORMAT(format); 1592 s_info = S_028044_FORMAT(1); 1593 1594 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_1D) { 1595 z_info |= S_028040_TILE_MODE_INDEX(4); 1596 s_info |= S_028044_TILE_MODE_INDEX(4); 1597 1598 } else if (rtex->surface.level[level].mode == RADEON_SURF_MODE_2D) { 1599 switch (format) { 1600 case V_028040_Z_16: 1601 z_info |= S_028040_TILE_MODE_INDEX(5); 1602 s_info |= S_028044_TILE_MODE_INDEX(5); 1603 break; 1604 case V_028040_Z_24: 1605 case V_028040_Z_32_FLOAT: 1606 z_info |= S_028040_TILE_MODE_INDEX(6); 1607 s_info |= S_028044_TILE_MODE_INDEX(6); 1608 break; 1609 default: 1610 z_info |= S_028040_TILE_MODE_INDEX(7); 1611 s_info |= S_028044_TILE_MODE_INDEX(7); 1612 } 1613 1614 } else { 1615 R600_ERR("Invalid DB tiling mode %d!\n", 1616 rtex->surface.level[level].mode); 1617 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0); 1618 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0); 1619 return; 1620 } 1621 1622 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW, 1623 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) | 1624 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer)); 1625 1626 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 0x1); 1627 if (format != ~0U) { 1628 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info); 1629 1630 } else { 1631 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0); 1632 } 1633 1634 if (rtex->surface.flags & RADEON_SURF_SBUFFER) { 1635 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info); 1636 } else { 1637 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0); 1638 } 1639 1640 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE); 1641 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs); 1642 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs); 1643 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs); 1644 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs); 1645 1646 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch)); 1647 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice)); 1648} 1649 1650static void si_set_framebuffer_state(struct pipe_context *ctx, 1651 const struct pipe_framebuffer_state *state) 1652{ 1653 struct r600_context *rctx = (struct r600_context *)ctx; 1654 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 1655 uint32_t shader_mask, tl, br; 1656 int tl_x, tl_y, br_x, br_y; 1657 1658 if (pm4 == NULL) 1659 return; 1660 1661 si_pm4_inval_fb_cache(pm4, state->nr_cbufs); 1662 1663 if (state->zsbuf) 1664 si_pm4_inval_zsbuf_cache(pm4); 1665 1666 util_copy_framebuffer_state(&rctx->framebuffer, state); 1667 1668 /* build states */ 1669 rctx->have_depth_fb = 0; 1670 for (int i = 0; i < state->nr_cbufs; i++) { 1671 si_cb(rctx, pm4, state, i); 1672 } 1673 si_db(rctx, pm4, state); 1674 1675 shader_mask = 0; 1676 for (int i = 0; i < state->nr_cbufs; i++) { 1677 shader_mask |= 0xf << (i * 4); 1678 } 1679 tl_x = 0; 1680 tl_y = 0; 1681 br_x = state->width; 1682 br_y = state->height; 1683#if 0 /* These shouldn't be necessary on SI, see PA_SC_ENHANCE register */ 1684 /* EG hw workaround */ 1685 if (br_x == 0) 1686 tl_x = 1; 1687 if (br_y == 0) 1688 tl_y = 1; 1689 /* cayman hw workaround */ 1690 if (rctx->chip_class == CAYMAN) { 1691 if (br_x == 1 && br_y == 1) 1692 br_x = 2; 1693 } 1694#endif 1695 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y); 1696 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y); 1697 1698 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl); 1699 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br); 1700 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl); 1701 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br); 1702 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl); 1703 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br); 1704 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl); 1705 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br); 1706 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000); 1707 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); 1708 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader_mask); 1709 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000); 1710 1711 si_pm4_set_state(rctx, framebuffer, pm4); 1712 si_update_fb_rs_state(rctx); 1713 si_update_fb_blend_state(rctx); 1714} 1715 1716/* 1717 * shaders 1718 */ 1719 1720static void *si_create_shader_state(struct pipe_context *ctx, 1721 const struct pipe_shader_state *state) 1722{ 1723 struct si_pipe_shader *shader = CALLOC_STRUCT(si_pipe_shader); 1724 1725 shader->tokens = tgsi_dup_tokens(state->tokens); 1726 shader->so = state->stream_output; 1727 1728 return shader; 1729} 1730 1731static void si_bind_vs_shader(struct pipe_context *ctx, void *state) 1732{ 1733 struct r600_context *rctx = (struct r600_context *)ctx; 1734 struct si_pipe_shader *shader = state; 1735 1736 if (rctx->vs_shader == state) 1737 return; 1738 1739 rctx->shader_dirty = true; 1740 rctx->vs_shader = shader; 1741 1742 if (shader) { 1743 si_pm4_bind_state(rctx, vs, shader->pm4); 1744 } 1745} 1746 1747static void si_bind_ps_shader(struct pipe_context *ctx, void *state) 1748{ 1749 struct r600_context *rctx = (struct r600_context *)ctx; 1750 struct si_pipe_shader *shader = state; 1751 1752 if (rctx->ps_shader == state) 1753 return; 1754 1755 rctx->shader_dirty = true; 1756 rctx->ps_shader = shader; 1757 1758 if (shader) { 1759 si_pm4_bind_state(rctx, ps, shader->pm4); 1760 } 1761} 1762 1763static void si_delete_vs_shader(struct pipe_context *ctx, void *state) 1764{ 1765 struct r600_context *rctx = (struct r600_context *)ctx; 1766 struct si_pipe_shader *shader = (struct si_pipe_shader *)state; 1767 1768 if (rctx->vs_shader == shader) { 1769 rctx->vs_shader = NULL; 1770 } 1771 1772 si_pm4_delete_state(rctx, vs, shader->pm4); 1773 free(shader->tokens); 1774 si_pipe_shader_destroy(ctx, shader); 1775 free(shader); 1776} 1777 1778static void si_delete_ps_shader(struct pipe_context *ctx, void *state) 1779{ 1780 struct r600_context *rctx = (struct r600_context *)ctx; 1781 struct si_pipe_shader *shader = (struct si_pipe_shader *)state; 1782 1783 if (rctx->ps_shader == shader) { 1784 rctx->ps_shader = NULL; 1785 } 1786 1787 si_pm4_delete_state(rctx, ps, shader->pm4); 1788 free(shader->tokens); 1789 si_pipe_shader_destroy(ctx, shader); 1790 free(shader); 1791} 1792 1793/* 1794 * Samplers 1795 */ 1796 1797static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx, 1798 struct pipe_resource *texture, 1799 const struct pipe_sampler_view *state) 1800{ 1801 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view); 1802 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture; 1803 const struct util_format_description *desc = util_format_description(state->format); 1804 unsigned blocksize = util_format_get_blocksize(tmp->real_format); 1805 unsigned format, num_format, /*endian,*/ tiling_index; 1806 uint32_t pitch = 0; 1807 unsigned char state_swizzle[4], swizzle[4]; 1808 unsigned height, depth, width, offset_level, last_level; 1809 int first_non_void; 1810 uint64_t va; 1811 1812 if (view == NULL) 1813 return NULL; 1814 1815 /* initialize base object */ 1816 view->base = *state; 1817 view->base.texture = NULL; 1818 pipe_reference(NULL, &texture->reference); 1819 view->base.texture = texture; 1820 view->base.reference.count = 1; 1821 view->base.context = ctx; 1822 1823 state_swizzle[0] = state->swizzle_r; 1824 state_swizzle[1] = state->swizzle_g; 1825 state_swizzle[2] = state->swizzle_b; 1826 state_swizzle[3] = state->swizzle_a; 1827 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle); 1828 1829 first_non_void = util_format_get_first_non_void_channel(state->format); 1830 switch (desc->channel[first_non_void].type) { 1831 case UTIL_FORMAT_TYPE_FLOAT: 1832 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT; 1833 break; 1834 case UTIL_FORMAT_TYPE_SIGNED: 1835 num_format = V_008F14_IMG_NUM_FORMAT_SNORM; 1836 break; 1837 case UTIL_FORMAT_TYPE_UNSIGNED: 1838 default: 1839 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 1840 } 1841 1842 format = si_translate_texformat(ctx->screen, state->format, desc, first_non_void); 1843 if (format == ~0) { 1844 format = 0; 1845 } 1846 1847 if (tmp->depth && !tmp->is_flushing_texture) { 1848 r600_texture_depth_flush(ctx, texture, TRUE); 1849 tmp = tmp->flushed_depth_texture; 1850 } 1851 1852 /* not supported any more */ 1853 //endian = si_colorformat_endian_swap(format); 1854 1855 offset_level = state->u.tex.first_level; 1856 last_level = state->u.tex.last_level - offset_level; 1857 width = tmp->surface.level[offset_level].npix_x; 1858 height = tmp->surface.level[offset_level].npix_y; 1859 depth = tmp->surface.level[offset_level].npix_z; 1860 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format); 1861 1862 if (texture->target == PIPE_TEXTURE_1D_ARRAY) { 1863 height = 1; 1864 depth = texture->array_size; 1865 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) { 1866 depth = texture->array_size; 1867 } 1868 1869 tiling_index = 8; 1870 switch (tmp->surface.level[state->u.tex.first_level].mode) { 1871 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1872 tiling_index = 8; 1873 break; 1874 case RADEON_SURF_MODE_1D: 1875 tiling_index = 9; 1876 break; 1877 case RADEON_SURF_MODE_2D: 1878 if (tmp->resource.b.b.bind & PIPE_BIND_SCANOUT) { 1879 switch (blocksize) { 1880 case 1: 1881 tiling_index = 10; 1882 break; 1883 case 2: 1884 tiling_index = 11; 1885 break; 1886 case 4: 1887 tiling_index = 12; 1888 break; 1889 } 1890 break; 1891 } else switch (blocksize) { 1892 case 1: 1893 tiling_index = 14; 1894 break; 1895 case 2: 1896 tiling_index = 15; 1897 break; 1898 case 4: 1899 tiling_index = 16; 1900 break; 1901 case 8: 1902 tiling_index = 17; 1903 break; 1904 default: 1905 tiling_index = 13; 1906 } 1907 break; 1908 } 1909 1910 va = r600_resource_va(ctx->screen, texture); 1911 va += tmp->surface.level[offset_level].offset; 1912 view->state[0] = va >> 8; 1913 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) | 1914 S_008F14_DATA_FORMAT(format) | 1915 S_008F14_NUM_FORMAT(num_format)); 1916 view->state[2] = (S_008F18_WIDTH(width - 1) | 1917 S_008F18_HEIGHT(height - 1)); 1918 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) | 1919 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) | 1920 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) | 1921 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) | 1922 S_008F1C_BASE_LEVEL(offset_level) | 1923 S_008F1C_LAST_LEVEL(last_level) | 1924 S_008F1C_TILING_INDEX(tiling_index) | 1925 S_008F1C_TYPE(si_tex_dim(texture->target))); 1926 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1)); 1927 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) | 1928 S_008F24_LAST_ARRAY(state->u.tex.last_layer)); 1929 view->state[6] = 0; 1930 view->state[7] = 0; 1931 1932 return &view->base; 1933} 1934 1935static void si_sampler_view_destroy(struct pipe_context *ctx, 1936 struct pipe_sampler_view *state) 1937{ 1938 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state; 1939 1940 pipe_resource_reference(&state->texture, NULL); 1941 FREE(resource); 1942} 1943 1944static void *si_create_sampler_state(struct pipe_context *ctx, 1945 const struct pipe_sampler_state *state) 1946{ 1947 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state); 1948 union util_color uc; 1949 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0; 1950 unsigned border_color_type; 1951 1952 if (rstate == NULL) { 1953 return NULL; 1954 } 1955 1956 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 1957 switch (uc.ui) { 1958 case 0x000000FF: 1959 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK; 1960 break; 1961 case 0x00000000: 1962 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK; 1963 break; 1964 case 0xFFFFFFFF: 1965 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE; 1966 break; 1967 default: /* Use border color pointer */ 1968 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER; 1969 } 1970 1971 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) | 1972 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) | 1973 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) | 1974 (state->max_anisotropy & 0x7) << 9 | /* XXX */ 1975 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) | 1976 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) | 1977 aniso_flag_offset << 16 | /* XXX */ 1978 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map)); 1979 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) | 1980 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8))); 1981 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) | 1982 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) | 1983 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) | 1984 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter))); 1985 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type); 1986 1987#if 0 1988 if (border_color_type == 3) { 1989 si_pm4_set_reg(pm4, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0])); 1990 si_pm4_set_reg(pm4, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1])); 1991 si_pm4_set_reg(pm4, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2])); 1992 si_pm4_set_reg(pm4, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3])); 1993 } 1994#endif 1995 return rstate; 1996} 1997 1998static void si_set_vs_sampler_view(struct pipe_context *ctx, unsigned count, 1999 struct pipe_sampler_view **views) 2000{ 2001 assert(count == 0); 2002} 2003 2004static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count, 2005 struct pipe_sampler_view **views) 2006{ 2007 struct r600_context *rctx = (struct r600_context *)ctx; 2008 struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views; 2009 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 2010 int i, j; 2011 int has_depth = 0; 2012 2013 if (!count) 2014 goto out; 2015 2016 si_pm4_inval_texture_cache(pm4); 2017 2018 si_pm4_sh_data_begin(pm4); 2019 for (i = 0; i < count; i++) { 2020 pipe_sampler_view_reference( 2021 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i], 2022 views[i]); 2023 2024 if (views[i]) { 2025 struct r600_resource_texture *tex = (void *)resource[i]->base.texture; 2026 2027 si_pm4_add_bo(pm4, &tex->resource, RADEON_USAGE_READ); 2028 2029 for (j = 0; j < Elements(resource[i]->state); ++j) { 2030 si_pm4_sh_data_add(pm4, resource[i]->state[j]); 2031 } 2032 } 2033 } 2034 2035 for (i = count; i < NUM_TEX_UNITS; i++) { 2036 if (rctx->ps_samplers.views[i]) 2037 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL); 2038 } 2039 2040 si_pm4_sh_data_end(pm4, R_00B040_SPI_SHADER_USER_DATA_PS_4); 2041 2042out: 2043 si_pm4_set_state(rctx, ps_sampler_views, pm4); 2044 rctx->have_depth_texture = has_depth; 2045 rctx->ps_samplers.n_views = count; 2046} 2047 2048static void si_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states) 2049{ 2050 assert(count == 0); 2051} 2052 2053static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states) 2054{ 2055 struct r600_context *rctx = (struct r600_context *)ctx; 2056 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states; 2057 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 2058 int i, j; 2059 2060 if (!count) 2061 goto out; 2062 2063 si_pm4_inval_texture_cache(pm4); 2064 2065 si_pm4_sh_data_begin(pm4); 2066 for (i = 0; i < count; i++) { 2067 for (j = 0; j < Elements(rstates[i]->val); ++j) { 2068 si_pm4_sh_data_add(pm4, rstates[i]->val[j]); 2069 } 2070 } 2071 si_pm4_sh_data_end(pm4, R_00B038_SPI_SHADER_USER_DATA_PS_2); 2072 2073 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count); 2074 2075out: 2076 si_pm4_set_state(rctx, ps_sampler, pm4); 2077 rctx->ps_samplers.n_samplers = count; 2078} 2079 2080static void si_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask) 2081{ 2082} 2083 2084static void si_delete_sampler_state(struct pipe_context *ctx, void *state) 2085{ 2086 free(state); 2087} 2088 2089/* 2090 * Constants 2091 */ 2092static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 2093 struct pipe_constant_buffer *cb) 2094{ 2095 struct r600_context *rctx = (struct r600_context *)ctx; 2096 struct si_resource *rbuffer = cb ? si_resource(cb->buffer) : NULL; 2097 struct si_pm4_state *pm4; 2098 uint64_t va_offset; 2099 uint32_t offset; 2100 2101 /* Note that the state tracker can unbind constant buffers by 2102 * passing NULL here. 2103 */ 2104 if (cb == NULL) 2105 return; 2106 2107 pm4 = CALLOC_STRUCT(si_pm4_state); 2108 si_pm4_inval_shader_cache(pm4); 2109 2110 if (cb->user_buffer) 2111 r600_upload_const_buffer(rctx, &rbuffer, cb->user_buffer, cb->buffer_size, &offset); 2112 else 2113 offset = 0; 2114 va_offset = r600_resource_va(ctx->screen, (void*)rbuffer); 2115 va_offset += offset; 2116 2117 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ); 2118 2119 switch (shader) { 2120 case PIPE_SHADER_VERTEX: 2121 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, va_offset); 2122 si_pm4_set_reg(pm4, R_00B134_SPI_SHADER_USER_DATA_VS_1, va_offset >> 32); 2123 si_pm4_set_state(rctx, vs_const, pm4); 2124 break; 2125 2126 case PIPE_SHADER_FRAGMENT: 2127 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0, va_offset); 2128 si_pm4_set_reg(pm4, R_00B034_SPI_SHADER_USER_DATA_PS_1, va_offset >> 32); 2129 si_pm4_set_state(rctx, ps_const, pm4); 2130 break; 2131 2132 default: 2133 R600_ERR("unsupported %d\n", shader); 2134 } 2135 2136 if (cb->buffer != &rbuffer->b.b) 2137 si_resource_reference(&rbuffer, NULL); 2138} 2139 2140/* 2141 * Vertex elements & buffers 2142 */ 2143 2144static void *si_create_vertex_elements(struct pipe_context *ctx, 2145 unsigned count, 2146 const struct pipe_vertex_element *elements) 2147{ 2148 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element); 2149 int i; 2150 2151 assert(count < PIPE_MAX_ATTRIBS); 2152 if (!v) 2153 return NULL; 2154 2155 v->count = count; 2156 for (i = 0; i < count; ++i) { 2157 const struct util_format_description *desc; 2158 unsigned data_format, num_format; 2159 int first_non_void; 2160 2161 desc = util_format_description(elements[i].src_format); 2162 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format); 2163 data_format = si_translate_vertexformat(ctx->screen, elements[i].src_format, 2164 desc, first_non_void); 2165 2166 switch (desc->channel[first_non_void].type) { 2167 case UTIL_FORMAT_TYPE_FIXED: 2168 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */ 2169 break; 2170 case UTIL_FORMAT_TYPE_SIGNED: 2171 num_format = V_008F0C_BUF_NUM_FORMAT_SNORM; 2172 break; 2173 case UTIL_FORMAT_TYPE_UNSIGNED: 2174 num_format = V_008F0C_BUF_NUM_FORMAT_UNORM; 2175 break; 2176 case UTIL_FORMAT_TYPE_FLOAT: 2177 default: 2178 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT; 2179 } 2180 2181 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) | 2182 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) | 2183 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) | 2184 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) | 2185 S_008F0C_NUM_FORMAT(num_format) | 2186 S_008F0C_DATA_FORMAT(data_format); 2187 } 2188 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count); 2189 2190 return v; 2191} 2192 2193static void si_bind_vertex_elements(struct pipe_context *ctx, void *state) 2194{ 2195 struct r600_context *rctx = (struct r600_context *)ctx; 2196 struct si_vertex_element *v = (struct si_vertex_element*)state; 2197 2198 rctx->vertex_elements = v; 2199} 2200 2201static void si_delete_vertex_element(struct pipe_context *ctx, void *state) 2202{ 2203 struct r600_context *rctx = (struct r600_context *)ctx; 2204 2205 if (rctx->vertex_elements == state) 2206 rctx->vertex_elements = NULL; 2207 FREE(state); 2208} 2209 2210static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 2211 const struct pipe_vertex_buffer *buffers) 2212{ 2213 struct r600_context *rctx = (struct r600_context *)ctx; 2214 2215 util_copy_vertex_buffers(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, count); 2216} 2217 2218static void si_set_index_buffer(struct pipe_context *ctx, 2219 const struct pipe_index_buffer *ib) 2220{ 2221 struct r600_context *rctx = (struct r600_context *)ctx; 2222 2223 if (ib) { 2224 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer); 2225 memcpy(&rctx->index_buffer, ib, sizeof(*ib)); 2226 } else { 2227 pipe_resource_reference(&rctx->index_buffer.buffer, NULL); 2228 } 2229} 2230 2231/* 2232 * Misc 2233 */ 2234static void si_set_polygon_stipple(struct pipe_context *ctx, 2235 const struct pipe_poly_stipple *state) 2236{ 2237} 2238 2239static void si_texture_barrier(struct pipe_context *ctx) 2240{ 2241 struct r600_context *rctx = (struct r600_context *)ctx; 2242 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 2243 2244 si_pm4_inval_texture_cache(pm4); 2245 si_pm4_inval_fb_cache(pm4, rctx->framebuffer.nr_cbufs); 2246 si_pm4_set_state(rctx, texture_barrier, pm4); 2247} 2248 2249void si_init_state_functions(struct r600_context *rctx) 2250{ 2251 rctx->context.create_blend_state = si_create_blend_state; 2252 rctx->context.bind_blend_state = si_bind_blend_state; 2253 rctx->context.delete_blend_state = si_delete_blend_state; 2254 rctx->context.set_blend_color = si_set_blend_color; 2255 2256 rctx->context.create_rasterizer_state = si_create_rs_state; 2257 rctx->context.bind_rasterizer_state = si_bind_rs_state; 2258 rctx->context.delete_rasterizer_state = si_delete_rs_state; 2259 2260 rctx->context.create_depth_stencil_alpha_state = si_create_dsa_state; 2261 rctx->context.bind_depth_stencil_alpha_state = si_bind_dsa_state; 2262 rctx->context.delete_depth_stencil_alpha_state = si_delete_dsa_state; 2263 rctx->custom_dsa_flush = si_create_db_flush_dsa(rctx); 2264 2265 rctx->context.set_clip_state = si_set_clip_state; 2266 rctx->context.set_scissor_state = si_set_scissor_state; 2267 rctx->context.set_viewport_state = si_set_viewport_state; 2268 rctx->context.set_stencil_ref = si_set_pipe_stencil_ref; 2269 2270 rctx->context.set_framebuffer_state = si_set_framebuffer_state; 2271 2272 rctx->context.create_vs_state = si_create_shader_state; 2273 rctx->context.create_fs_state = si_create_shader_state; 2274 rctx->context.bind_vs_state = si_bind_vs_shader; 2275 rctx->context.bind_fs_state = si_bind_ps_shader; 2276 rctx->context.delete_vs_state = si_delete_vs_shader; 2277 rctx->context.delete_fs_state = si_delete_ps_shader; 2278 2279 rctx->context.create_sampler_state = si_create_sampler_state; 2280 rctx->context.bind_vertex_sampler_states = si_bind_vs_sampler; 2281 rctx->context.bind_fragment_sampler_states = si_bind_ps_sampler; 2282 rctx->context.delete_sampler_state = si_delete_sampler_state; 2283 2284 rctx->context.create_sampler_view = si_create_sampler_view; 2285 rctx->context.set_vertex_sampler_views = si_set_vs_sampler_view; 2286 rctx->context.set_fragment_sampler_views = si_set_ps_sampler_view; 2287 rctx->context.sampler_view_destroy = si_sampler_view_destroy; 2288 2289 rctx->context.set_sample_mask = si_set_sample_mask; 2290 2291 rctx->context.set_constant_buffer = si_set_constant_buffer; 2292 2293 rctx->context.create_vertex_elements_state = si_create_vertex_elements; 2294 rctx->context.bind_vertex_elements_state = si_bind_vertex_elements; 2295 rctx->context.delete_vertex_elements_state = si_delete_vertex_element; 2296 rctx->context.set_vertex_buffers = si_set_vertex_buffers; 2297 rctx->context.set_index_buffer = si_set_index_buffer; 2298 2299 rctx->context.create_stream_output_target = si_create_so_target; 2300 rctx->context.stream_output_target_destroy = si_so_target_destroy; 2301 rctx->context.set_stream_output_targets = si_set_so_targets; 2302 2303 rctx->context.texture_barrier = si_texture_barrier; 2304 rctx->context.set_polygon_stipple = si_set_polygon_stipple; 2305 2306 rctx->context.draw_vbo = si_draw_vbo; 2307} 2308 2309void si_init_config(struct r600_context *rctx) 2310{ 2311 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 2312 2313 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL); 2314 si_pm4_cmd_add(pm4, 0x80000000); 2315 si_pm4_cmd_add(pm4, 0x80000000); 2316 si_pm4_cmd_end(pm4, false); 2317 2318 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0); 2319 2320 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0); 2321 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0); 2322 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0); 2323 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0); 2324 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0); 2325 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0); 2326 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0); 2327 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0); 2328 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0); 2329 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0); 2330 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0); 2331 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0); 2332 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0); 2333 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0); 2334 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0); 2335 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0); 2336 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0); 2337 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM, 2338 S_028AA8_SWITCH_ON_EOP(1) | 2339 S_028AA8_PARTIAL_VS_WAVE_ON(1) | 2340 S_028AA8_PRIMGROUP_SIZE(63)); 2341 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000); 2342 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0); 2343 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1); 2344 2345 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0); 2346 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210); 2347 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98); 2348 2349 si_pm4_set_reg(pm4, R_028804_DB_EQAA, 0x110000); 2350 2351 si_pm4_set_state(rctx, init, pm4); 2352} 2353