si_state_draw.c revision 303f4b7dcddee384d6f1dc1027cbdee840a38d7d
1/* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Christian König <christian.koenig@amd.com> 25 */ 26 27#include "util/u_memory.h" 28#include "util/u_framebuffer.h" 29#include "util/u_blitter.h" 30#include "tgsi/tgsi_parse.h" 31#include "radeonsi_pipe.h" 32#include "radeonsi_shader.h" 33#include "si_state.h" 34#include "sid.h" 35 36/* 37 * Shaders 38 */ 39 40static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader) 41{ 42 struct r600_context *rctx = (struct r600_context *)ctx; 43 struct si_pm4_state *pm4; 44 unsigned num_sgprs, num_user_sgprs; 45 unsigned nparams, i; 46 uint64_t va; 47 48 if (si_pipe_shader_create(ctx, shader)) 49 return; 50 51 si_pm4_delete_state(rctx, vs, shader->pm4); 52 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state); 53 54 si_pm4_inval_shader_cache(pm4); 55 56 /* Certain attributes (position, psize, etc.) don't count as params. 57 * VS is required to export at least one param and r600_shader_from_tgsi() 58 * takes care of adding a dummy export. 59 */ 60 for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) { 61 if (shader->shader.output[i].name != TGSI_SEMANTIC_POSITION) 62 nparams++; 63 } 64 if (nparams < 1) 65 nparams = 1; 66 67 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG, 68 S_0286C4_VS_EXPORT_COUNT(nparams - 1)); 69 70 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT, 71 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) | 72 S_02870C_POS1_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) | 73 S_02870C_POS2_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) | 74 S_02870C_POS3_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE)); 75 76 va = r600_resource_va(ctx->screen, (void *)shader->bo); 77 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ); 78 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8); 79 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40); 80 81 num_user_sgprs = 8; 82 num_sgprs = shader->num_sgprs; 83 if (num_user_sgprs > num_sgprs) 84 num_sgprs = num_user_sgprs; 85 /* Last 2 reserved SGPRs are used for VCC */ 86 num_sgprs += 2; 87 assert(num_sgprs <= 104); 88 89 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, 90 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) | 91 S_00B128_SGPRS((num_sgprs - 1) / 8)); 92 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, 93 S_00B12C_USER_SGPR(num_user_sgprs)); 94 95 si_pm4_bind_state(rctx, vs, shader->pm4); 96} 97 98static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader) 99{ 100 struct r600_context *rctx = (struct r600_context *)ctx; 101 struct si_pm4_state *pm4; 102 unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control; 103 unsigned num_sgprs, num_user_sgprs; 104 int ninterp = 0; 105 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE; 106 unsigned spi_baryc_cntl; 107 uint64_t va; 108 109 if (si_pipe_shader_create(ctx, shader)) 110 return; 111 112 si_pm4_delete_state(rctx, ps, shader->pm4); 113 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state); 114 115 si_pm4_inval_shader_cache(pm4); 116 117 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); 118 for (i = 0; i < shader->shader.ninput; i++) { 119 ninterp++; 120 /* XXX: Flat shading hangs the GPU */ 121 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_CONSTANT || 122 (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_COLOR && 123 rctx->queued.named.rasterizer->flatshade)) 124 have_linear = TRUE; 125 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_LINEAR) 126 have_linear = TRUE; 127 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) 128 have_perspective = TRUE; 129 if (shader->shader.input[i].centroid) 130 have_centroid = TRUE; 131 } 132 133 for (i = 0; i < shader->shader.noutput; i++) { 134 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION) 135 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1); 136 if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL) 137 db_shader_control |= 0; // XXX OP_VAL or TEST_VAL? 138 } 139 if (shader->shader.uses_kill) 140 db_shader_control |= S_02880C_KILL_ENABLE(1); 141 142 exports_ps = 0; 143 num_cout = 0; 144 for (i = 0; i < shader->shader.noutput; i++) { 145 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION || 146 shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL) 147 exports_ps |= 1; 148 else if (shader->shader.output[i].name == TGSI_SEMANTIC_COLOR) { 149 if (shader->shader.fs_write_all) 150 num_cout = shader->shader.nr_cbufs; 151 else 152 num_cout++; 153 } 154 } 155 if (!exports_ps) { 156 /* always at least export 1 component per pixel */ 157 exports_ps = 2; 158 } 159 160 spi_ps_in_control = S_0286D8_NUM_INTERP(ninterp); 161 162 spi_baryc_cntl = 0; 163 if (have_perspective) 164 spi_baryc_cntl |= have_centroid ? 165 S_0286E0_PERSP_CENTROID_CNTL(1) : S_0286E0_PERSP_CENTER_CNTL(1); 166 if (have_linear) 167 spi_baryc_cntl |= have_centroid ? 168 S_0286E0_LINEAR_CENTROID_CNTL(1) : S_0286E0_LINEAR_CENTER_CNTL(1); 169 170 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl); 171 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, shader->spi_ps_input_ena); 172 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, shader->spi_ps_input_ena); 173 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control); 174 175 /* XXX: Depends on Z buffer format? */ 176 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, 0); 177 178 /* XXX: Depends on color buffer format? */ 179 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, 180 S_028714_COL0_EXPORT_FORMAT(V_028714_SPI_SHADER_32_ABGR)); 181 182 va = r600_resource_va(ctx->screen, (void *)shader->bo); 183 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ); 184 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8); 185 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40); 186 187 num_user_sgprs = 6; 188 num_sgprs = shader->num_sgprs; 189 if (num_user_sgprs > num_sgprs) 190 num_sgprs = num_user_sgprs; 191 /* Last 2 reserved SGPRs are used for VCC */ 192 num_sgprs += 2; 193 assert(num_sgprs <= 104); 194 195 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, 196 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) | 197 S_00B028_SGPRS((num_sgprs - 1) / 8)); 198 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 199 S_00B02C_USER_SGPR(num_user_sgprs)); 200 201 si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control); 202 203 shader->sprite_coord_enable = rctx->sprite_coord_enable; 204 si_pm4_bind_state(rctx, ps, shader->pm4); 205} 206 207/* 208 * Drawing 209 */ 210 211static unsigned si_conv_pipe_prim(unsigned pprim) 212{ 213 static const unsigned prim_conv[] = { 214 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST, 215 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST, 216 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP, 217 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP, 218 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST, 219 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP, 220 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN, 221 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST, 222 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP, 223 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON, 224 [PIPE_PRIM_LINES_ADJACENCY] = ~0, 225 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = ~0, 226 [PIPE_PRIM_TRIANGLES_ADJACENCY] = ~0, 227 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = ~0 228 }; 229 unsigned result = prim_conv[pprim]; 230 if (result == ~0) { 231 R600_ERR("unsupported primitive type %d\n", pprim); 232 } 233 return result; 234} 235 236static bool si_update_draw_info_state(struct r600_context *rctx, 237 const struct pipe_draw_info *info) 238{ 239 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 240 unsigned prim = si_conv_pipe_prim(info->mode); 241 unsigned ls_mask = 0; 242 243 if (pm4 == NULL) 244 return false; 245 246 if (prim == ~0) { 247 FREE(pm4); 248 return false; 249 } 250 251 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim); 252 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0); 253 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0); 254 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, info->index_bias); 255 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index); 256 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart); 257#if 0 258 si_pm4_set_reg(pm4, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0); 259 si_pm4_set_reg(pm4, R_03CFF4_SQ_VTX_START_INST_LOC, info->start_instance); 260#endif 261 262 if (prim == V_008958_DI_PT_LINELIST) 263 ls_mask = 1; 264 else if (prim == V_008958_DI_PT_LINESTRIP) 265 ls_mask = 2; 266 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE, 267 S_028A0C_AUTO_RESET_CNTL(ls_mask) | 268 rctx->pa_sc_line_stipple); 269 270 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) { 271 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, 272 S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl); 273 } else { 274 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl); 275 } 276 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL, 277 prim == PIPE_PRIM_POINTS ? rctx->pa_cl_vs_out_cntl : 0 278 /*| (rctx->rasterizer->clip_plane_enable & 279 rctx->vs_shader->shader.clip_dist_write)*/); 280 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL, rctx->pa_cl_clip_cntl 281 /*| (rctx->vs_shader->shader.clip_dist_write || 282 rctx->vs_shader->shader.vs_prohibit_ucps ? 283 0 : rctx->rasterizer->clip_plane_enable & 0x3F)*/); 284 285 si_pm4_set_state(rctx, draw_info, pm4); 286 return true; 287} 288 289static void si_update_alpha_ref(struct r600_context *rctx) 290{ 291#if 0 292 unsigned alpha_ref; 293 struct r600_pipe_state rstate; 294 295 alpha_ref = rctx->alpha_ref; 296 rstate.nregs = 0; 297 if (rctx->export_16bpc) 298 alpha_ref &= ~0x1FFF; 299 si_pm4_set_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref); 300 301 si_pm4_set_state(rctx, TODO, pm4); 302 rctx->alpha_ref_dirty = false; 303#endif 304} 305 306static void si_update_spi_map(struct r600_context *rctx) 307{ 308 struct si_shader *ps = &rctx->ps_shader->shader; 309 struct si_shader *vs = &rctx->vs_shader->shader; 310 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 311 unsigned i, j, tmp; 312 313 for (i = 0; i < ps->ninput; i++) { 314 tmp = 0; 315 316#if 0 317 /* XXX: Flat shading hangs the GPU */ 318 if (ps->input[i].name == TGSI_SEMANTIC_POSITION || 319 ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT || 320 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR && 321 rctx->rasterizer && rctx->rasterizer->flatshade)) { 322 tmp |= S_028644_FLAT_SHADE(1); 323 } 324#endif 325 326 if (ps->input[i].name == TGSI_SEMANTIC_GENERIC && 327 rctx->sprite_coord_enable & (1 << ps->input[i].sid)) { 328 tmp |= S_028644_PT_SPRITE_TEX(1); 329 } 330 331 for (j = 0; j < vs->noutput; j++) { 332 if (ps->input[i].name == vs->output[j].name && 333 ps->input[i].sid == vs->output[j].sid) { 334 tmp |= S_028644_OFFSET(vs->output[j].param_offset); 335 break; 336 } 337 } 338 339 if (j == vs->noutput) { 340 /* No corresponding output found, load defaults into input */ 341 tmp |= S_028644_OFFSET(0x20); 342 } 343 344 si_pm4_set_reg(pm4, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp); 345 } 346 347 si_pm4_set_state(rctx, spi, pm4); 348} 349 350static void si_update_derived_state(struct r600_context *rctx) 351{ 352 struct pipe_context * ctx = (struct pipe_context*)rctx; 353 354 if (!rctx->blitter->running) { 355 if (rctx->have_depth_fb || rctx->have_depth_texture) 356 r600_flush_depth_textures(rctx); 357 } 358 359 if ((rctx->ps_shader->shader.fs_write_all && 360 (rctx->ps_shader->shader.nr_cbufs != rctx->framebuffer.nr_cbufs)) || 361 (rctx->sprite_coord_enable && 362 (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable))) { 363 si_pipe_shader_destroy(&rctx->context, rctx->ps_shader); 364 } 365 366 if (rctx->alpha_ref_dirty) { 367 si_update_alpha_ref(rctx); 368 } 369 370 if (!rctx->vs_shader->bo) { 371 si_pipe_shader_vs(ctx, rctx->vs_shader); 372 } 373 374 if (!rctx->ps_shader->bo) { 375 si_pipe_shader_ps(ctx, rctx->ps_shader); 376 } 377 if (!rctx->ps_shader->bo) { 378 if (!rctx->dummy_pixel_shader->bo) 379 si_pipe_shader_ps(ctx, rctx->dummy_pixel_shader); 380 381 if (rctx->dummy_pixel_shader->pm4) 382 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4); 383 } 384 385 if (rctx->shader_dirty) { 386 si_update_spi_map(rctx); 387 rctx->shader_dirty = false; 388 } 389} 390 391static void si_vertex_buffer_update(struct r600_context *rctx) 392{ 393 struct pipe_context *ctx = &rctx->context; 394 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 395 bool bound[PIPE_MAX_ATTRIBS] = {}; 396 struct si_resource *t_list_buffer; 397 unsigned i, count; 398 uint32_t *ptr; 399 uint64_t va; 400 401 si_pm4_inval_vertex_cache(pm4); 402 403 /* bind vertex buffer once */ 404 count = rctx->vertex_elements->count; 405 assert(count <= 256 / 4); 406 407 t_list_buffer = si_resource_create_custom(ctx->screen, PIPE_USAGE_IMMUTABLE, 408 4 * 4 * count); 409 if (t_list_buffer == NULL) { 410 FREE(pm4); 411 return; 412 } 413 si_pm4_add_bo(pm4, t_list_buffer, RADEON_USAGE_READ); 414 415 ptr = (uint32_t*)rctx->ws->buffer_map(t_list_buffer->cs_buf, 416 rctx->cs, 417 PIPE_TRANSFER_WRITE); 418 419 for (i = 0 ; i < count; i++, ptr += 4) { 420 struct pipe_vertex_element *ve = &rctx->vertex_elements->elements[i]; 421 struct pipe_vertex_buffer *vb; 422 struct si_resource *rbuffer; 423 unsigned offset; 424 425 if (ve->vertex_buffer_index >= rctx->nr_vertex_buffers) 426 continue; 427 428 vb = &rctx->vertex_buffer[ve->vertex_buffer_index]; 429 rbuffer = (struct si_resource*)vb->buffer; 430 if (rbuffer == NULL) 431 continue; 432 433 offset = 0; 434 offset += vb->buffer_offset; 435 offset += ve->src_offset; 436 437 va = r600_resource_va(ctx->screen, (void*)rbuffer); 438 va += offset; 439 440 /* Fill in T# buffer resource description */ 441 ptr[0] = va & 0xFFFFFFFF; 442 ptr[1] = (S_008F04_BASE_ADDRESS_HI(va >> 32) | 443 S_008F04_STRIDE(vb->stride)); 444 if (vb->stride > 0) 445 ptr[2] = (vb->buffer->width0 - offset) / vb->stride; 446 else 447 ptr[2] = vb->buffer->width0 - offset; 448 ptr[3] = rctx->vertex_elements->rsrc_word3[i]; 449 450 if (!bound[ve->vertex_buffer_index]) { 451 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ); 452 bound[ve->vertex_buffer_index] = true; 453 } 454 } 455 456 va = r600_resource_va(ctx->screen, (void*)t_list_buffer); 457 si_pm4_set_reg(pm4, R_00B148_SPI_SHADER_USER_DATA_VS_6, va); 458 si_pm4_set_reg(pm4, R_00B14C_SPI_SHADER_USER_DATA_VS_7, va >> 32); 459 si_pm4_set_state(rctx, vertex_buffers, pm4); 460} 461 462void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) 463{ 464 struct r600_context *rctx = (struct r600_context *)ctx; 465 struct si_state_dsa *dsa = rctx->queued.named.dsa; 466 struct pipe_draw_info info = *dinfo; 467 struct r600_draw rdraw = {}; 468 struct pipe_index_buffer ib = {}; 469 struct r600_atom *state = NULL, *next_state = NULL; 470 471 if ((!info.count && (info.indexed || !info.count_from_stream_output)) || 472 (info.indexed && !rctx->index_buffer.buffer)) { 473 return; 474 } 475 476 if (!rctx->ps_shader || !rctx->vs_shader) 477 return; 478 479 si_update_derived_state(rctx); 480 si_vertex_buffer_update(rctx); 481 482 rdraw.vgt_num_indices = info.count; 483 rdraw.vgt_num_instances = info.instance_count; 484 485 if (info.indexed) { 486 /* Initialize the index buffer struct. */ 487 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer); 488 ib.index_size = rctx->index_buffer.index_size; 489 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size; 490 491 /* Translate or upload, if needed. */ 492 r600_translate_index_buffer(rctx, &ib, info.count); 493 494 if (ib.user_buffer) { 495 r600_upload_index_buffer(rctx, &ib, info.count); 496 } 497 498 /* Initialize the r600_draw struct with index buffer info. */ 499 if (ib.index_size == 4) { 500 rdraw.vgt_index_type = V_028A7C_VGT_INDEX_32 | 501 (R600_BIG_ENDIAN ? V_028A7C_VGT_DMA_SWAP_32_BIT : 0); 502 } else { 503 rdraw.vgt_index_type = V_028A7C_VGT_INDEX_16 | 504 (R600_BIG_ENDIAN ? V_028A7C_VGT_DMA_SWAP_16_BIT : 0); 505 } 506 rdraw.indices = (struct si_resource*)ib.buffer; 507 rdraw.indices_bo_offset = ib.offset; 508 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_DMA; 509 } else { 510 info.index_bias = info.start; 511 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX; 512 if (info.count_from_stream_output) { 513 rdraw.vgt_draw_initiator |= S_0287F0_USE_OPAQUE(1); 514 515 r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output); 516 } 517 } 518 519 rctx->vs_shader_so_strides = rctx->vs_shader->so_strides; 520 521 if (!si_update_draw_info_state(rctx, &info)) 522 return; 523 524 rdraw.db_render_override = dsa->db_render_override; 525 rdraw.db_render_control = dsa->db_render_control; 526 527 /* Emit states. */ 528 rctx->pm4_dirty_cdwords += si_pm4_dirty_dw(rctx); 529 530 r600_need_cs_space(rctx, 0, TRUE); 531 532 LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) { 533 r600_emit_atom(rctx, state); 534 } 535 si_pm4_emit_dirty(rctx); 536 rctx->pm4_dirty_cdwords = 0; 537 538#if 0 539 /* Enable stream out if needed. */ 540 if (rctx->streamout_start) { 541 r600_context_streamout_begin(rctx); 542 rctx->streamout_start = FALSE; 543 } 544#endif 545 546 si_context_draw(rctx, &rdraw); 547 548 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY; 549 550 if (rctx->framebuffer.zsbuf) 551 { 552 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture; 553 ((struct r600_resource_texture *)tex)->dirty_db = TRUE; 554 } 555 556 pipe_resource_reference(&ib.buffer, NULL); 557} 558