si_state_draw.c revision d1e40b3d40b2e90ad4f275565f1ae27fe6f964cc
1/* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Christian König <christian.koenig@amd.com> 25 */ 26 27#include "util/u_memory.h" 28#include "util/u_framebuffer.h" 29#include "util/u_blitter.h" 30#include "tgsi/tgsi_parse.h" 31#include "radeonsi_pipe.h" 32#include "radeonsi_shader.h" 33#include "si_state.h" 34#include "sid.h" 35 36/* 37 * Shaders 38 */ 39 40static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader) 41{ 42 struct r600_context *rctx = (struct r600_context *)ctx; 43 struct si_pm4_state *pm4; 44 unsigned num_sgprs, num_user_sgprs; 45 unsigned nparams, i; 46 uint64_t va; 47 48 if (si_pipe_shader_create(ctx, shader)) 49 return; 50 51 si_pm4_delete_state(rctx, vs, shader->pm4); 52 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state); 53 54 si_pm4_inval_shader_cache(pm4); 55 56 /* Certain attributes (position, psize, etc.) don't count as params. 57 * VS is required to export at least one param and r600_shader_from_tgsi() 58 * takes care of adding a dummy export. 59 */ 60 for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) { 61 if (shader->shader.output[i].name != TGSI_SEMANTIC_POSITION) 62 nparams++; 63 } 64 if (nparams < 1) 65 nparams = 1; 66 67 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG, 68 S_0286C4_VS_EXPORT_COUNT(nparams - 1)); 69 70 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT, 71 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) | 72 S_02870C_POS1_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) | 73 S_02870C_POS2_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) | 74 S_02870C_POS3_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE)); 75 76 va = r600_resource_va(ctx->screen, (void *)shader->bo); 77 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ); 78 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8); 79 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40); 80 81 num_user_sgprs = 8; 82 num_sgprs = shader->num_sgprs; 83 if (num_user_sgprs > num_sgprs) 84 num_sgprs = num_user_sgprs; 85 /* Last 2 reserved SGPRs are used for VCC */ 86 num_sgprs += 2; 87 assert(num_sgprs <= 104); 88 89 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, 90 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) | 91 S_00B128_SGPRS((num_sgprs - 1) / 8)); 92 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, 93 S_00B12C_USER_SGPR(num_user_sgprs)); 94 95 si_pm4_bind_state(rctx, vs, shader->pm4); 96} 97 98static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader) 99{ 100 struct r600_context *rctx = (struct r600_context *)ctx; 101 struct si_pm4_state *pm4; 102 unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control; 103 unsigned num_sgprs, num_user_sgprs; 104 int ninterp = 0; 105 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE; 106 unsigned spi_baryc_cntl, spi_ps_input_ena; 107 uint64_t va; 108 109 if (si_pipe_shader_create(ctx, shader)) 110 return; 111 112 si_pm4_delete_state(rctx, ps, shader->pm4); 113 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state); 114 115 si_pm4_inval_shader_cache(pm4); 116 117 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); 118 for (i = 0; i < shader->shader.ninput; i++) { 119 ninterp++; 120 /* XXX: Flat shading hangs the GPU */ 121 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_CONSTANT || 122 (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_COLOR && 123 rctx->queued.named.rasterizer->flatshade)) 124 have_linear = TRUE; 125 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_LINEAR) 126 have_linear = TRUE; 127 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) 128 have_perspective = TRUE; 129 if (shader->shader.input[i].centroid) 130 have_centroid = TRUE; 131 } 132 133 for (i = 0; i < shader->shader.noutput; i++) { 134 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION) 135 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1); 136 if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL) 137 db_shader_control |= 0; // XXX OP_VAL or TEST_VAL? 138 } 139 if (shader->shader.uses_kill) 140 db_shader_control |= S_02880C_KILL_ENABLE(1); 141 142 exports_ps = 0; 143 num_cout = 0; 144 for (i = 0; i < shader->shader.noutput; i++) { 145 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION || 146 shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL) 147 exports_ps |= 1; 148 else if (shader->shader.output[i].name == TGSI_SEMANTIC_COLOR) { 149 if (shader->shader.fs_write_all) 150 num_cout = shader->shader.nr_cbufs; 151 else 152 num_cout++; 153 } 154 } 155 if (!exports_ps) { 156 /* always at least export 1 component per pixel */ 157 exports_ps = 2; 158 } 159 160 spi_ps_in_control = S_0286D8_NUM_INTERP(ninterp); 161 162 spi_baryc_cntl = 0; 163 if (have_perspective) 164 spi_baryc_cntl |= have_centroid ? 165 S_0286E0_PERSP_CENTROID_CNTL(1) : S_0286E0_PERSP_CENTER_CNTL(1); 166 if (have_linear) 167 spi_baryc_cntl |= have_centroid ? 168 S_0286E0_LINEAR_CENTROID_CNTL(1) : S_0286E0_LINEAR_CENTER_CNTL(1); 169 170 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl); 171 spi_ps_input_ena = shader->spi_ps_input_ena; 172 /* we need to enable at least one of them, otherwise we hang the GPU */ 173 if (!spi_ps_input_ena & (C_0286CC_PERSP_SAMPLE_ENA | 174 C_0286CC_PERSP_CENTROID_ENA | 175 C_0286CC_PERSP_PULL_MODEL_ENA | 176 C_0286CC_LINEAR_SAMPLE_ENA | 177 C_0286CC_LINEAR_CENTER_ENA | 178 C_0286CC_LINEAR_CENTROID_ENA | 179 C_0286CC_LINE_STIPPLE_TEX_ENA)) { 180 spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1); 181 } 182 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena); 183 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena); 184 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control); 185 186 /* XXX: Depends on Z buffer format? */ 187 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, 0); 188 189 /* XXX: Depends on color buffer format? */ 190 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, 191 S_028714_COL0_EXPORT_FORMAT(V_028714_SPI_SHADER_32_ABGR)); 192 193 va = r600_resource_va(ctx->screen, (void *)shader->bo); 194 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ); 195 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8); 196 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40); 197 198 num_user_sgprs = 6; 199 num_sgprs = shader->num_sgprs; 200 if (num_user_sgprs > num_sgprs) 201 num_sgprs = num_user_sgprs; 202 /* Last 2 reserved SGPRs are used for VCC */ 203 num_sgprs += 2; 204 assert(num_sgprs <= 104); 205 206 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, 207 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) | 208 S_00B028_SGPRS((num_sgprs - 1) / 8)); 209 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 210 S_00B02C_USER_SGPR(num_user_sgprs)); 211 212 si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control); 213 214 shader->sprite_coord_enable = rctx->sprite_coord_enable; 215 si_pm4_bind_state(rctx, ps, shader->pm4); 216} 217 218/* 219 * Drawing 220 */ 221 222static unsigned si_conv_pipe_prim(unsigned pprim) 223{ 224 static const unsigned prim_conv[] = { 225 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST, 226 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST, 227 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP, 228 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP, 229 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST, 230 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP, 231 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN, 232 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST, 233 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP, 234 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON, 235 [PIPE_PRIM_LINES_ADJACENCY] = ~0, 236 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = ~0, 237 [PIPE_PRIM_TRIANGLES_ADJACENCY] = ~0, 238 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = ~0 239 }; 240 unsigned result = prim_conv[pprim]; 241 if (result == ~0) { 242 R600_ERR("unsupported primitive type %d\n", pprim); 243 } 244 return result; 245} 246 247static bool si_update_draw_info_state(struct r600_context *rctx, 248 const struct pipe_draw_info *info) 249{ 250 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 251 unsigned prim = si_conv_pipe_prim(info->mode); 252 unsigned ls_mask = 0; 253 254 if (pm4 == NULL) 255 return false; 256 257 if (prim == ~0) { 258 FREE(pm4); 259 return false; 260 } 261 262 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim); 263 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0); 264 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0); 265 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 266 info->indexed ? info->index_bias : info->start); 267 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index); 268 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart); 269#if 0 270 si_pm4_set_reg(pm4, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0); 271 si_pm4_set_reg(pm4, R_03CFF4_SQ_VTX_START_INST_LOC, info->start_instance); 272#endif 273 274 if (prim == V_008958_DI_PT_LINELIST) 275 ls_mask = 1; 276 else if (prim == V_008958_DI_PT_LINESTRIP) 277 ls_mask = 2; 278 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE, 279 S_028A0C_AUTO_RESET_CNTL(ls_mask) | 280 rctx->pa_sc_line_stipple); 281 282 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) { 283 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, 284 S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl); 285 } else { 286 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl); 287 } 288 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL, 289 prim == PIPE_PRIM_POINTS ? rctx->pa_cl_vs_out_cntl : 0 290 /*| (rctx->rasterizer->clip_plane_enable & 291 rctx->vs_shader->shader.clip_dist_write)*/); 292 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL, rctx->pa_cl_clip_cntl 293 /*| (rctx->vs_shader->shader.clip_dist_write || 294 rctx->vs_shader->shader.vs_prohibit_ucps ? 295 0 : rctx->rasterizer->clip_plane_enable & 0x3F)*/); 296 297 si_pm4_set_state(rctx, draw_info, pm4); 298 return true; 299} 300 301static void si_update_alpha_ref(struct r600_context *rctx) 302{ 303#if 0 304 unsigned alpha_ref; 305 struct r600_pipe_state rstate; 306 307 alpha_ref = rctx->alpha_ref; 308 rstate.nregs = 0; 309 if (rctx->export_16bpc) 310 alpha_ref &= ~0x1FFF; 311 si_pm4_set_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref); 312 313 si_pm4_set_state(rctx, TODO, pm4); 314 rctx->alpha_ref_dirty = false; 315#endif 316} 317 318static void si_update_spi_map(struct r600_context *rctx) 319{ 320 struct si_shader *ps = &rctx->ps_shader->current->shader; 321 struct si_shader *vs = &rctx->vs_shader->current->shader; 322 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 323 unsigned i, j, tmp; 324 325 for (i = 0; i < ps->ninput; i++) { 326 tmp = 0; 327 328#if 0 329 /* XXX: Flat shading hangs the GPU */ 330 if (ps->input[i].name == TGSI_SEMANTIC_POSITION || 331 ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT || 332 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR && 333 rctx->rasterizer && rctx->rasterizer->flatshade)) { 334 tmp |= S_028644_FLAT_SHADE(1); 335 } 336#endif 337 338 if (ps->input[i].name == TGSI_SEMANTIC_GENERIC && 339 rctx->sprite_coord_enable & (1 << ps->input[i].sid)) { 340 tmp |= S_028644_PT_SPRITE_TEX(1); 341 } 342 343 for (j = 0; j < vs->noutput; j++) { 344 if (ps->input[i].name == vs->output[j].name && 345 ps->input[i].sid == vs->output[j].sid) { 346 tmp |= S_028644_OFFSET(vs->output[j].param_offset); 347 break; 348 } 349 } 350 351 if (j == vs->noutput) { 352 /* No corresponding output found, load defaults into input */ 353 tmp |= S_028644_OFFSET(0x20); 354 } 355 356 si_pm4_set_reg(pm4, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp); 357 } 358 359 si_pm4_set_state(rctx, spi, pm4); 360} 361 362static void si_update_derived_state(struct r600_context *rctx) 363{ 364 struct pipe_context * ctx = (struct pipe_context*)rctx; 365 unsigned ps_dirty = 0; 366 367 if (!rctx->blitter->running) { 368 if (rctx->have_depth_fb || rctx->have_depth_texture) 369 si_flush_depth_textures(rctx); 370 } 371 372 si_shader_select(ctx, rctx->ps_shader, &ps_dirty); 373 374 if (rctx->alpha_ref_dirty) { 375 si_update_alpha_ref(rctx); 376 } 377 378 if (!rctx->vs_shader->current->pm4) { 379 si_pipe_shader_vs(ctx, rctx->vs_shader->current); 380 } 381 382 if (!rctx->ps_shader->current->pm4) { 383 si_pipe_shader_ps(ctx, rctx->ps_shader->current); 384 ps_dirty = 0; 385 } 386 if (!rctx->ps_shader->current->bo) { 387 if (!rctx->dummy_pixel_shader->pm4) 388 si_pipe_shader_ps(ctx, rctx->dummy_pixel_shader); 389 else 390 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4); 391 392 ps_dirty = 0; 393 } 394 395 if (ps_dirty) { 396 si_pm4_bind_state(rctx, ps, rctx->ps_shader->current->pm4); 397 rctx->shader_dirty = true; 398 } 399 400 if (rctx->shader_dirty) { 401 si_update_spi_map(rctx); 402 rctx->shader_dirty = false; 403 } 404} 405 406static void si_vertex_buffer_update(struct r600_context *rctx) 407{ 408 struct pipe_context *ctx = &rctx->context; 409 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 410 bool bound[PIPE_MAX_ATTRIBS] = {}; 411 unsigned i, count; 412 uint64_t va; 413 414 si_pm4_inval_vertex_cache(pm4); 415 416 /* bind vertex buffer once */ 417 count = rctx->vertex_elements->count; 418 assert(count <= 256 / 4); 419 420 si_pm4_sh_data_begin(pm4); 421 for (i = 0 ; i < count; i++) { 422 struct pipe_vertex_element *ve = &rctx->vertex_elements->elements[i]; 423 struct pipe_vertex_buffer *vb; 424 struct si_resource *rbuffer; 425 unsigned offset; 426 427 if (ve->vertex_buffer_index >= rctx->nr_vertex_buffers) 428 continue; 429 430 vb = &rctx->vertex_buffer[ve->vertex_buffer_index]; 431 rbuffer = (struct si_resource*)vb->buffer; 432 if (rbuffer == NULL) 433 continue; 434 435 offset = 0; 436 offset += vb->buffer_offset; 437 offset += ve->src_offset; 438 439 va = r600_resource_va(ctx->screen, (void*)rbuffer); 440 va += offset; 441 442 /* Fill in T# buffer resource description */ 443 si_pm4_sh_data_add(pm4, va & 0xFFFFFFFF); 444 si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) | 445 S_008F04_STRIDE(vb->stride))); 446 si_pm4_sh_data_add(pm4, (vb->buffer->width0 - offset) / 447 MAX2(vb->stride, 1)); 448 si_pm4_sh_data_add(pm4, rctx->vertex_elements->rsrc_word3[i]); 449 450 if (!bound[ve->vertex_buffer_index]) { 451 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ); 452 bound[ve->vertex_buffer_index] = true; 453 } 454 } 455 si_pm4_sh_data_end(pm4, R_00B148_SPI_SHADER_USER_DATA_VS_6); 456 si_pm4_set_state(rctx, vertex_buffers, pm4); 457} 458 459static void si_state_draw(struct r600_context *rctx, 460 const struct pipe_draw_info *info, 461 const struct pipe_index_buffer *ib) 462{ 463 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 464 465 /* queries need some special values 466 * (this is non-zero if any query is active) */ 467 if (rctx->num_cs_dw_queries_suspend) { 468 struct si_state_dsa *dsa = rctx->queued.named.dsa; 469 470 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL, 471 S_028004_PERFECT_ZPASS_COUNTS(1)); 472 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 473 dsa->db_render_override | 474 S_02800C_NOOP_CULL_DISABLE(1)); 475 } 476 477 /* draw packet */ 478 si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE); 479 if (ib->index_size == 4) { 480 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (R600_BIG_ENDIAN ? 481 V_028A7C_VGT_DMA_SWAP_32_BIT : 0)); 482 } else { 483 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (R600_BIG_ENDIAN ? 484 V_028A7C_VGT_DMA_SWAP_16_BIT : 0)); 485 } 486 si_pm4_cmd_end(pm4, rctx->predicate_drawing); 487 488 si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES); 489 si_pm4_cmd_add(pm4, info->instance_count); 490 si_pm4_cmd_end(pm4, rctx->predicate_drawing); 491 492 if (info->indexed) { 493 uint64_t va; 494 va = r600_resource_va(&rctx->screen->screen, ib->buffer); 495 va += ib->offset; 496 497 si_pm4_add_bo(pm4, (struct si_resource *)ib->buffer, RADEON_USAGE_READ); 498 si_pm4_cmd_begin(pm4, PKT3_DRAW_INDEX_2); 499 si_pm4_cmd_add(pm4, (ib->buffer->width0 - ib->offset) / 500 rctx->index_buffer.index_size); 501 si_pm4_cmd_add(pm4, va); 502 si_pm4_cmd_add(pm4, (va >> 32UL) & 0xFF); 503 si_pm4_cmd_add(pm4, info->count); 504 si_pm4_cmd_add(pm4, V_0287F0_DI_SRC_SEL_DMA); 505 si_pm4_cmd_end(pm4, rctx->predicate_drawing); 506 } else { 507 si_pm4_cmd_begin(pm4, PKT3_DRAW_INDEX_AUTO); 508 si_pm4_cmd_add(pm4, info->count); 509 si_pm4_cmd_add(pm4, V_0287F0_DI_SRC_SEL_AUTO_INDEX | 510 (info->count_from_stream_output ? 511 S_0287F0_USE_OPAQUE(1) : 0)); 512 si_pm4_cmd_end(pm4, rctx->predicate_drawing); 513 } 514 si_pm4_set_state(rctx, draw, pm4); 515} 516 517void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) 518{ 519 struct r600_context *rctx = (struct r600_context *)ctx; 520 struct pipe_index_buffer ib = {}; 521 uint32_t cp_coher_cntl; 522 523 if ((!info->count && (info->indexed || !info->count_from_stream_output)) || 524 (info->indexed && !rctx->index_buffer.buffer)) { 525 return; 526 } 527 528 if (!rctx->ps_shader || !rctx->vs_shader) 529 return; 530 531 si_update_derived_state(rctx); 532 si_vertex_buffer_update(rctx); 533 534 if (info->indexed) { 535 /* Initialize the index buffer struct. */ 536 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer); 537 ib.index_size = rctx->index_buffer.index_size; 538 ib.offset = rctx->index_buffer.offset + info->start * ib.index_size; 539 540 /* Translate or upload, if needed. */ 541 r600_translate_index_buffer(rctx, &ib, info->count); 542 543 if (ib.user_buffer) { 544 r600_upload_index_buffer(rctx, &ib, info->count); 545 } 546 547 } else if (info->count_from_stream_output) { 548 r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info->count_from_stream_output); 549 } 550 551 rctx->vs_shader_so_strides = rctx->vs_shader->current->so_strides; 552 553 if (!si_update_draw_info_state(rctx, info)) 554 return; 555 556 si_state_draw(rctx, info, &ib); 557 558 cp_coher_cntl = si_pm4_sync_flags(rctx); 559 if (cp_coher_cntl) { 560 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 561 si_cmd_surface_sync(pm4, cp_coher_cntl); 562 si_pm4_set_state(rctx, sync, pm4); 563 } 564 565 /* Emit states. */ 566 rctx->pm4_dirty_cdwords += si_pm4_dirty_dw(rctx); 567 568 si_need_cs_space(rctx, 0, TRUE); 569 570 si_pm4_emit_dirty(rctx); 571 rctx->pm4_dirty_cdwords = 0; 572 573#if 0 574 /* Enable stream out if needed. */ 575 if (rctx->streamout_start) { 576 r600_context_streamout_begin(rctx); 577 rctx->streamout_start = FALSE; 578 } 579#endif 580 581 582 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY; 583 584 if (rctx->framebuffer.zsbuf) 585 { 586 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture; 587 ((struct r600_resource_texture *)tex)->dirty_db = TRUE; 588 } 589 590 pipe_resource_reference(&ib.buffer, NULL); 591} 592