radeon_drm_bo.c revision 206d07625c9fd69c7d00a8722bd7390c5215bfe2
1/* 2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com> 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 */ 26 27#define _FILE_OFFSET_BITS 64 28#include "radeon_drm_cs.h" 29 30#include "util/u_hash_table.h" 31#include "util/u_memory.h" 32#include "util/u_simple_list.h" 33#include "util/u_double_list.h" 34#include "os/os_thread.h" 35#include "os/os_mman.h" 36 37#include "state_tracker/drm_driver.h" 38 39#include <sys/ioctl.h> 40#include <xf86drm.h> 41#include <errno.h> 42 43/* 44 * this are copy from radeon_drm, once an updated libdrm is released 45 * we should bump configure.ac requirement for it and remove the following 46 * field 47 */ 48#define RADEON_BO_FLAGS_MACRO_TILE 1 49#define RADEON_BO_FLAGS_MICRO_TILE 2 50#define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20 51 52#ifndef DRM_RADEON_GEM_WAIT 53#define DRM_RADEON_GEM_WAIT 0x2b 54 55#define RADEON_GEM_NO_WAIT 0x1 56#define RADEON_GEM_USAGE_READ 0x2 57#define RADEON_GEM_USAGE_WRITE 0x4 58 59struct drm_radeon_gem_wait { 60 uint32_t handle; 61 uint32_t flags; /* one of RADEON_GEM_* */ 62}; 63 64#endif 65 66#ifndef RADEON_VA_MAP 67 68#define RADEON_VA_MAP 1 69#define RADEON_VA_UNMAP 2 70 71#define RADEON_VA_RESULT_OK 0 72#define RADEON_VA_RESULT_ERROR 1 73#define RADEON_VA_RESULT_VA_EXIST 2 74 75#define RADEON_VM_PAGE_VALID (1 << 0) 76#define RADEON_VM_PAGE_READABLE (1 << 1) 77#define RADEON_VM_PAGE_WRITEABLE (1 << 2) 78#define RADEON_VM_PAGE_SYSTEM (1 << 3) 79#define RADEON_VM_PAGE_SNOOPED (1 << 4) 80 81struct drm_radeon_gem_va { 82 uint32_t handle; 83 uint32_t operation; 84 uint32_t vm_id; 85 uint32_t flags; 86 uint64_t offset; 87}; 88 89#define DRM_RADEON_GEM_VA 0x2b 90#endif 91 92 93 94extern const struct pb_vtbl radeon_bo_vtbl; 95 96 97static INLINE struct radeon_bo *radeon_bo(struct pb_buffer *bo) 98{ 99 assert(bo->vtbl == &radeon_bo_vtbl); 100 return (struct radeon_bo *)bo; 101} 102 103struct radeon_bo_va_hole { 104 struct list_head list; 105 uint64_t offset; 106 uint64_t size; 107}; 108 109struct radeon_bomgr { 110 /* Base class. */ 111 struct pb_manager base; 112 113 /* Winsys. */ 114 struct radeon_drm_winsys *rws; 115 116 /* List of buffer handles and its mutex. */ 117 struct util_hash_table *bo_handles; 118 pipe_mutex bo_handles_mutex; 119 pipe_mutex bo_va_mutex; 120 121 /* is virtual address supported */ 122 bool va; 123 uint64_t va_offset; 124 struct list_head va_holes; 125}; 126 127static INLINE struct radeon_bomgr *radeon_bomgr(struct pb_manager *mgr) 128{ 129 return (struct radeon_bomgr *)mgr; 130} 131 132static struct radeon_bo *get_radeon_bo(struct pb_buffer *_buf) 133{ 134 struct radeon_bo *bo = NULL; 135 136 if (_buf->vtbl == &radeon_bo_vtbl) { 137 bo = radeon_bo(_buf); 138 } else { 139 struct pb_buffer *base_buf; 140 pb_size offset; 141 pb_get_base_buffer(_buf, &base_buf, &offset); 142 143 if (base_buf->vtbl == &radeon_bo_vtbl) 144 bo = radeon_bo(base_buf); 145 } 146 147 return bo; 148} 149 150static void radeon_bo_wait(struct pb_buffer *_buf, enum radeon_bo_usage usage) 151{ 152 struct radeon_bo *bo = get_radeon_bo(_buf); 153 154 while (p_atomic_read(&bo->num_active_ioctls)) { 155 sched_yield(); 156 } 157 158 /* XXX use this when it's ready */ 159 /*if (bo->rws->info.drm_minor >= 12) { 160 struct drm_radeon_gem_wait args = {}; 161 args.handle = bo->handle; 162 args.flags = usage; 163 while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT, 164 &args, sizeof(args)) == -EBUSY); 165 } else*/ { 166 struct drm_radeon_gem_wait_idle args; 167 memset(&args, 0, sizeof(args)); 168 args.handle = bo->handle; 169 while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT_IDLE, 170 &args, sizeof(args)) == -EBUSY); 171 } 172} 173 174static boolean radeon_bo_is_busy(struct pb_buffer *_buf, 175 enum radeon_bo_usage usage) 176{ 177 struct radeon_bo *bo = get_radeon_bo(_buf); 178 179 if (p_atomic_read(&bo->num_active_ioctls)) { 180 return TRUE; 181 } 182 183 /* XXX use this when it's ready */ 184 /*if (bo->rws->info.drm_minor >= 12) { 185 struct drm_radeon_gem_wait args = {}; 186 args.handle = bo->handle; 187 args.flags = usage | RADEON_GEM_NO_WAIT; 188 return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT, 189 &args, sizeof(args)) != 0; 190 } else*/ { 191 struct drm_radeon_gem_busy args; 192 memset(&args, 0, sizeof(args)); 193 args.handle = bo->handle; 194 return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_BUSY, 195 &args, sizeof(args)) != 0; 196 } 197} 198 199static uint64_t radeon_bomgr_find_va(struct radeon_bomgr *mgr, uint64_t size, uint64_t alignment) 200{ 201 struct radeon_bo_va_hole *hole, *n; 202 uint64_t offset = 0, waste = 0; 203 204 pipe_mutex_lock(mgr->bo_va_mutex); 205 /* first look for a hole */ 206 LIST_FOR_EACH_ENTRY_SAFE(hole, n, &mgr->va_holes, list) { 207 offset = hole->offset; 208 waste = 0; 209 if (alignment) { 210 waste = offset % alignment; 211 waste = waste ? alignment - waste : 0; 212 } 213 offset += waste; 214 if (offset >= (hole->offset + hole->size)) { 215 continue; 216 } 217 if (!waste && hole->size == size) { 218 offset = hole->offset; 219 list_del(&hole->list); 220 FREE(hole); 221 pipe_mutex_unlock(mgr->bo_va_mutex); 222 return offset; 223 } 224 if ((hole->size - waste) >= size) { 225 if (waste) { 226 n = CALLOC_STRUCT(radeon_bo_va_hole); 227 n->size = waste; 228 n->offset = hole->offset; 229 list_add(&n->list, &hole->list); 230 } 231 hole->size -= (size + waste); 232 hole->offset += size + waste; 233 pipe_mutex_unlock(mgr->bo_va_mutex); 234 return offset; 235 } 236 } 237 238 offset = mgr->va_offset; 239 waste = 0; 240 if (alignment) { 241 waste = offset % alignment; 242 waste = waste ? alignment - waste : 0; 243 } 244 offset += waste; 245 mgr->va_offset += size + waste; 246 pipe_mutex_unlock(mgr->bo_va_mutex); 247 return offset; 248} 249 250static void radeon_bomgr_force_va(struct radeon_bomgr *mgr, uint64_t va, uint64_t size) 251{ 252 pipe_mutex_lock(mgr->bo_va_mutex); 253 if (va >= mgr->va_offset) { 254 if (va > mgr->va_offset) { 255 struct radeon_bo_va_hole *hole; 256 hole = CALLOC_STRUCT(radeon_bo_va_hole); 257 if (hole) { 258 hole->size = va - mgr->va_offset; 259 hole->offset = mgr->va_offset; 260 list_add(&hole->list, &mgr->va_holes); 261 } 262 } 263 mgr->va_offset = va + size; 264 } else { 265 struct radeon_bo_va_hole *hole, *n; 266 uint64_t stmp, etmp; 267 268 /* free all holes that fall into the range 269 * NOTE that we might lose virtual address space 270 */ 271 LIST_FOR_EACH_ENTRY_SAFE(hole, n, &mgr->va_holes, list) { 272 stmp = hole->offset; 273 etmp = stmp + hole->size; 274 if (va >= stmp && va < etmp) { 275 list_del(&hole->list); 276 FREE(hole); 277 } 278 } 279 } 280 pipe_mutex_unlock(mgr->bo_va_mutex); 281} 282 283static void radeon_bomgr_free_va(struct radeon_bomgr *mgr, uint64_t va, uint64_t size) 284{ 285 pipe_mutex_lock(mgr->bo_va_mutex); 286 if ((va + size) == mgr->va_offset) { 287 mgr->va_offset = va; 288 } else { 289 struct radeon_bo_va_hole *hole, *next; 290 291 hole = container_of(&mgr->va_holes, hole, list); 292 LIST_FOR_EACH_ENTRY(next, &mgr->va_holes, list) { 293 if (next->offset < va) 294 break; 295 hole = next; 296 } 297 298 if (&hole->list != &mgr->va_holes) { 299 /* Grow upper hole if it's adjacent */ 300 if (hole->offset == (va + size)) { 301 hole->offset = va; 302 hole->size += size; 303 /* Merge lower hole if it's adjacent */ 304 if (next != hole && &next->list != &mgr->va_holes && 305 (next->offset + next->size) == va) { 306 next->size += hole->size; 307 list_del(&hole->list); 308 FREE(hole); 309 } 310 goto out; 311 } 312 } 313 314 /* Grow lower hole if it's adjacent */ 315 if (next != hole && &next->list != &mgr->va_holes && 316 (next->offset + next->size) == va) { 317 next->size += size; 318 goto out; 319 } 320 321 /* FIXME on allocation failure we just lose virtual address space 322 * maybe print a warning 323 */ 324 next = CALLOC_STRUCT(radeon_bo_va_hole); 325 if (next) { 326 next->size = size; 327 next->offset = va; 328 list_add(&next->list, &hole->list); 329 } 330 } 331out: 332 pipe_mutex_unlock(mgr->bo_va_mutex); 333} 334 335static void radeon_bo_destroy(struct pb_buffer *_buf) 336{ 337 struct radeon_bo *bo = radeon_bo(_buf); 338 struct radeon_bomgr *mgr = bo->mgr; 339 struct drm_gem_close args; 340 341 memset(&args, 0, sizeof(args)); 342 343 if (bo->name) { 344 pipe_mutex_lock(bo->mgr->bo_handles_mutex); 345 util_hash_table_remove(bo->mgr->bo_handles, 346 (void*)(uintptr_t)bo->name); 347 pipe_mutex_unlock(bo->mgr->bo_handles_mutex); 348 } 349 350 if (bo->ptr) 351 os_munmap(bo->ptr, bo->base.size); 352 353 /* Close object. */ 354 args.handle = bo->handle; 355 drmIoctl(bo->rws->fd, DRM_IOCTL_GEM_CLOSE, &args); 356 357 if (mgr->va) { 358 radeon_bomgr_free_va(mgr, bo->va, bo->va_size); 359 } 360 361 pipe_mutex_destroy(bo->map_mutex); 362 FREE(bo); 363} 364 365static void *radeon_bo_map(struct radeon_winsys_cs_handle *buf, 366 struct radeon_winsys_cs *rcs, 367 enum pipe_transfer_usage usage) 368{ 369 struct radeon_bo *bo = (struct radeon_bo*)buf; 370 struct radeon_drm_cs *cs = (struct radeon_drm_cs*)rcs; 371 struct drm_radeon_gem_mmap args = {0}; 372 void *ptr; 373 374 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */ 375 if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) { 376 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */ 377 if (usage & PIPE_TRANSFER_DONTBLOCK) { 378 if (!(usage & PIPE_TRANSFER_WRITE)) { 379 /* Mapping for read. 380 * 381 * Since we are mapping for read, we don't need to wait 382 * if the GPU is using the buffer for read too 383 * (neither one is changing it). 384 * 385 * Only check whether the buffer is being used for write. */ 386 if (radeon_bo_is_referenced_by_cs_for_write(cs, bo)) { 387 cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC); 388 return NULL; 389 } 390 391 if (radeon_bo_is_busy((struct pb_buffer*)bo, 392 RADEON_USAGE_WRITE)) { 393 return NULL; 394 } 395 } else { 396 if (radeon_bo_is_referenced_by_cs(cs, bo)) { 397 cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC); 398 return NULL; 399 } 400 401 if (radeon_bo_is_busy((struct pb_buffer*)bo, 402 RADEON_USAGE_READWRITE)) { 403 return NULL; 404 } 405 } 406 } else { 407 if (!(usage & PIPE_TRANSFER_WRITE)) { 408 /* Mapping for read. 409 * 410 * Since we are mapping for read, we don't need to wait 411 * if the GPU is using the buffer for read too 412 * (neither one is changing it). 413 * 414 * Only check whether the buffer is being used for write. */ 415 if (radeon_bo_is_referenced_by_cs_for_write(cs, bo)) { 416 cs->flush_cs(cs->flush_data, 0); 417 } 418 radeon_bo_wait((struct pb_buffer*)bo, 419 RADEON_USAGE_WRITE); 420 } else { 421 /* Mapping for write. */ 422 if (radeon_bo_is_referenced_by_cs(cs, bo)) { 423 cs->flush_cs(cs->flush_data, 0); 424 } else { 425 /* Try to avoid busy-waiting in radeon_bo_wait. */ 426 if (p_atomic_read(&bo->num_active_ioctls)) 427 radeon_drm_cs_sync_flush(cs); 428 } 429 430 radeon_bo_wait((struct pb_buffer*)bo, RADEON_USAGE_READWRITE); 431 } 432 } 433 } 434 435 /* Return the pointer if it's already mapped. */ 436 if (bo->ptr) 437 return bo->ptr; 438 439 /* Map the buffer. */ 440 pipe_mutex_lock(bo->map_mutex); 441 /* Return the pointer if it's already mapped (in case of a race). */ 442 if (bo->ptr) { 443 pipe_mutex_unlock(bo->map_mutex); 444 return bo->ptr; 445 } 446 args.handle = bo->handle; 447 args.offset = 0; 448 args.size = (uint64_t)bo->base.size; 449 if (drmCommandWriteRead(bo->rws->fd, 450 DRM_RADEON_GEM_MMAP, 451 &args, 452 sizeof(args))) { 453 pipe_mutex_unlock(bo->map_mutex); 454 fprintf(stderr, "radeon: gem_mmap failed: %p 0x%08X\n", 455 bo, bo->handle); 456 return NULL; 457 } 458 459 ptr = os_mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, 460 bo->rws->fd, args.addr_ptr); 461 if (ptr == MAP_FAILED) { 462 pipe_mutex_unlock(bo->map_mutex); 463 fprintf(stderr, "radeon: mmap failed, errno: %i\n", errno); 464 return NULL; 465 } 466 bo->ptr = ptr; 467 pipe_mutex_unlock(bo->map_mutex); 468 469 return bo->ptr; 470} 471 472static void radeon_bo_unmap(struct radeon_winsys_cs_handle *_buf) 473{ 474 /* NOP */ 475} 476 477static void radeon_bo_get_base_buffer(struct pb_buffer *buf, 478 struct pb_buffer **base_buf, 479 unsigned *offset) 480{ 481 *base_buf = buf; 482 *offset = 0; 483} 484 485static enum pipe_error radeon_bo_validate(struct pb_buffer *_buf, 486 struct pb_validate *vl, 487 unsigned flags) 488{ 489 /* Always pinned */ 490 return PIPE_OK; 491} 492 493static void radeon_bo_fence(struct pb_buffer *buf, 494 struct pipe_fence_handle *fence) 495{ 496} 497 498const struct pb_vtbl radeon_bo_vtbl = { 499 radeon_bo_destroy, 500 NULL, /* never called */ 501 NULL, /* never called */ 502 radeon_bo_validate, 503 radeon_bo_fence, 504 radeon_bo_get_base_buffer, 505}; 506 507static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr, 508 pb_size size, 509 const struct pb_desc *desc) 510{ 511 struct radeon_bomgr *mgr = radeon_bomgr(_mgr); 512 struct radeon_drm_winsys *rws = mgr->rws; 513 struct radeon_bo *bo; 514 struct drm_radeon_gem_create args; 515 struct radeon_bo_desc *rdesc = (struct radeon_bo_desc*)desc; 516 int r; 517 518 memset(&args, 0, sizeof(args)); 519 520 assert(rdesc->initial_domains); 521 assert((rdesc->initial_domains & 522 ~(RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) == 0); 523 524 args.size = size; 525 args.alignment = desc->alignment; 526 args.initial_domain = rdesc->initial_domains; 527 528 if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE, 529 &args, sizeof(args))) { 530 fprintf(stderr, "radeon: Failed to allocate a buffer:\n"); 531 fprintf(stderr, "radeon: size : %d bytes\n", size); 532 fprintf(stderr, "radeon: alignment : %d bytes\n", desc->alignment); 533 fprintf(stderr, "radeon: domains : %d\n", args.initial_domain); 534 return NULL; 535 } 536 537 bo = CALLOC_STRUCT(radeon_bo); 538 if (!bo) 539 return NULL; 540 541 pipe_reference_init(&bo->base.reference, 1); 542 bo->base.alignment = desc->alignment; 543 bo->base.usage = desc->usage; 544 bo->base.size = size; 545 bo->base.vtbl = &radeon_bo_vtbl; 546 bo->mgr = mgr; 547 bo->rws = mgr->rws; 548 bo->handle = args.handle; 549 bo->va = 0; 550 pipe_mutex_init(bo->map_mutex); 551 552 if (mgr->va) { 553 struct drm_radeon_gem_va va; 554 555 bo->va_size = align(size, 4096); 556 bo->va = radeon_bomgr_find_va(mgr, bo->va_size, desc->alignment); 557 558 va.handle = bo->handle; 559 va.vm_id = 0; 560 va.operation = RADEON_VA_MAP; 561 va.flags = RADEON_VM_PAGE_READABLE | 562 RADEON_VM_PAGE_WRITEABLE | 563 RADEON_VM_PAGE_SNOOPED; 564 va.offset = bo->va; 565 r = drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_VA, &va, sizeof(va)); 566 if (r && va.operation == RADEON_VA_RESULT_ERROR) { 567 fprintf(stderr, "radeon: Failed to allocate a buffer:\n"); 568 fprintf(stderr, "radeon: size : %d bytes\n", size); 569 fprintf(stderr, "radeon: alignment : %d bytes\n", desc->alignment); 570 fprintf(stderr, "radeon: domains : %d\n", args.initial_domain); 571 radeon_bo_destroy(&bo->base); 572 return NULL; 573 } 574 if (va.operation == RADEON_VA_RESULT_VA_EXIST) { 575 radeon_bomgr_free_va(mgr, bo->va, bo->va_size); 576 bo->va = va.offset; 577 radeon_bomgr_force_va(mgr, bo->va, bo->va_size); 578 } 579 } 580 581 return &bo->base; 582} 583 584static void radeon_bomgr_flush(struct pb_manager *mgr) 585{ 586 /* NOP */ 587} 588 589/* This is for the cache bufmgr. */ 590static boolean radeon_bomgr_is_buffer_busy(struct pb_manager *_mgr, 591 struct pb_buffer *_buf) 592{ 593 struct radeon_bo *bo = radeon_bo(_buf); 594 595 if (radeon_bo_is_referenced_by_any_cs(bo)) { 596 return TRUE; 597 } 598 599 if (radeon_bo_is_busy((struct pb_buffer*)bo, RADEON_USAGE_READWRITE)) { 600 return TRUE; 601 } 602 603 return FALSE; 604} 605 606static void radeon_bomgr_destroy(struct pb_manager *_mgr) 607{ 608 struct radeon_bomgr *mgr = radeon_bomgr(_mgr); 609 util_hash_table_destroy(mgr->bo_handles); 610 pipe_mutex_destroy(mgr->bo_handles_mutex); 611 pipe_mutex_destroy(mgr->bo_va_mutex); 612 FREE(mgr); 613} 614 615#define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x))) 616 617static unsigned handle_hash(void *key) 618{ 619 return PTR_TO_UINT(key); 620} 621 622static int handle_compare(void *key1, void *key2) 623{ 624 return PTR_TO_UINT(key1) != PTR_TO_UINT(key2); 625} 626 627struct pb_manager *radeon_bomgr_create(struct radeon_drm_winsys *rws) 628{ 629 struct radeon_bomgr *mgr; 630 631 mgr = CALLOC_STRUCT(radeon_bomgr); 632 if (!mgr) 633 return NULL; 634 635 mgr->base.destroy = radeon_bomgr_destroy; 636 mgr->base.create_buffer = radeon_bomgr_create_bo; 637 mgr->base.flush = radeon_bomgr_flush; 638 mgr->base.is_buffer_busy = radeon_bomgr_is_buffer_busy; 639 640 mgr->rws = rws; 641 mgr->bo_handles = util_hash_table_create(handle_hash, handle_compare); 642 pipe_mutex_init(mgr->bo_handles_mutex); 643 pipe_mutex_init(mgr->bo_va_mutex); 644 645 mgr->va = rws->info.r600_virtual_address; 646 mgr->va_offset = rws->info.r600_va_start; 647 list_inithead(&mgr->va_holes); 648 649 return &mgr->base; 650} 651 652static unsigned eg_tile_split(unsigned tile_split) 653{ 654 switch (tile_split) { 655 case 0: tile_split = 64; break; 656 case 1: tile_split = 128; break; 657 case 2: tile_split = 256; break; 658 case 3: tile_split = 512; break; 659 default: 660 case 4: tile_split = 1024; break; 661 case 5: tile_split = 2048; break; 662 case 6: tile_split = 4096; break; 663 } 664 return tile_split; 665} 666 667static unsigned eg_tile_split_rev(unsigned eg_tile_split) 668{ 669 switch (eg_tile_split) { 670 case 64: return 0; 671 case 128: return 1; 672 case 256: return 2; 673 case 512: return 3; 674 default: 675 case 1024: return 4; 676 case 2048: return 5; 677 case 4096: return 6; 678 } 679} 680 681static void radeon_bo_get_tiling(struct pb_buffer *_buf, 682 enum radeon_bo_layout *microtiled, 683 enum radeon_bo_layout *macrotiled, 684 unsigned *bankw, unsigned *bankh, 685 unsigned *tile_split, 686 unsigned *stencil_tile_split, 687 unsigned *mtilea) 688{ 689 struct radeon_bo *bo = get_radeon_bo(_buf); 690 struct drm_radeon_gem_set_tiling args; 691 692 memset(&args, 0, sizeof(args)); 693 694 args.handle = bo->handle; 695 696 drmCommandWriteRead(bo->rws->fd, 697 DRM_RADEON_GEM_GET_TILING, 698 &args, 699 sizeof(args)); 700 701 *microtiled = RADEON_LAYOUT_LINEAR; 702 *macrotiled = RADEON_LAYOUT_LINEAR; 703 if (args.tiling_flags & RADEON_BO_FLAGS_MICRO_TILE) 704 *microtiled = RADEON_LAYOUT_TILED; 705 706 if (args.tiling_flags & RADEON_BO_FLAGS_MACRO_TILE) 707 *macrotiled = RADEON_LAYOUT_TILED; 708 if (bankw && tile_split && stencil_tile_split && mtilea && tile_split) { 709 *bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; 710 *bankh = (args.tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; 711 *tile_split = (args.tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; 712 *stencil_tile_split = (args.tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; 713 *mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; 714 *tile_split = eg_tile_split(*tile_split); 715 } 716} 717 718static void radeon_bo_set_tiling(struct pb_buffer *_buf, 719 struct radeon_winsys_cs *rcs, 720 enum radeon_bo_layout microtiled, 721 enum radeon_bo_layout macrotiled, 722 unsigned bankw, unsigned bankh, 723 unsigned tile_split, 724 unsigned stencil_tile_split, 725 unsigned mtilea, 726 uint32_t pitch) 727{ 728 struct radeon_bo *bo = get_radeon_bo(_buf); 729 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); 730 struct drm_radeon_gem_set_tiling args; 731 732 memset(&args, 0, sizeof(args)); 733 734 /* Tiling determines how DRM treats the buffer data. 735 * We must flush CS when changing it if the buffer is referenced. */ 736 if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) { 737 cs->flush_cs(cs->flush_data, 0); 738 } 739 740 while (p_atomic_read(&bo->num_active_ioctls)) { 741 sched_yield(); 742 } 743 744 if (microtiled == RADEON_LAYOUT_TILED) 745 args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE; 746 else if (microtiled == RADEON_LAYOUT_SQUARETILED) 747 args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE_SQUARE; 748 749 if (macrotiled == RADEON_LAYOUT_TILED) 750 args.tiling_flags |= RADEON_BO_FLAGS_MACRO_TILE; 751 752 args.tiling_flags |= (bankw & RADEON_TILING_EG_BANKW_MASK) << 753 RADEON_TILING_EG_BANKW_SHIFT; 754 args.tiling_flags |= (bankh & RADEON_TILING_EG_BANKH_MASK) << 755 RADEON_TILING_EG_BANKH_SHIFT; 756 if (tile_split) { 757 args.tiling_flags |= (eg_tile_split_rev(tile_split) & 758 RADEON_TILING_EG_TILE_SPLIT_MASK) << 759 RADEON_TILING_EG_TILE_SPLIT_SHIFT; 760 } 761 args.tiling_flags |= (stencil_tile_split & 762 RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK) << 763 RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT; 764 args.tiling_flags |= (mtilea & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK) << 765 RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT; 766 767 args.handle = bo->handle; 768 args.pitch = pitch; 769 770 drmCommandWriteRead(bo->rws->fd, 771 DRM_RADEON_GEM_SET_TILING, 772 &args, 773 sizeof(args)); 774} 775 776static struct radeon_winsys_cs_handle *radeon_drm_get_cs_handle( 777 struct pb_buffer *_buf) 778{ 779 /* return radeon_bo. */ 780 return (struct radeon_winsys_cs_handle*)get_radeon_bo(_buf); 781} 782 783static struct pb_buffer * 784radeon_winsys_bo_create(struct radeon_winsys *rws, 785 unsigned size, 786 unsigned alignment, 787 unsigned bind, 788 enum radeon_bo_domain domain) 789{ 790 struct radeon_drm_winsys *ws = radeon_drm_winsys(rws); 791 struct radeon_bo_desc desc; 792 struct pb_manager *provider; 793 struct pb_buffer *buffer; 794 795 memset(&desc, 0, sizeof(desc)); 796 desc.base.alignment = alignment; 797 798 /* Additional criteria for the cache manager. */ 799 desc.base.usage = domain; 800 desc.initial_domains = domain; 801 802 /* Assign a buffer manager. */ 803 if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER | 804 PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_CUSTOM)) 805 provider = ws->cman; 806 else 807 provider = ws->kman; 808 809 buffer = provider->create_buffer(provider, size, &desc.base); 810 if (!buffer) 811 return NULL; 812 813 return (struct pb_buffer*)buffer; 814} 815 816static struct pb_buffer *radeon_winsys_bo_from_handle(struct radeon_winsys *rws, 817 struct winsys_handle *whandle, 818 unsigned *stride) 819{ 820 struct radeon_drm_winsys *ws = radeon_drm_winsys(rws); 821 struct radeon_bo *bo; 822 struct radeon_bomgr *mgr = radeon_bomgr(ws->kman); 823 struct drm_gem_open open_arg = {}; 824 int r; 825 826 memset(&open_arg, 0, sizeof(open_arg)); 827 828 /* We must maintain a list of pairs <handle, bo>, so that we always return 829 * the same BO for one particular handle. If we didn't do that and created 830 * more than one BO for the same handle and then relocated them in a CS, 831 * we would hit a deadlock in the kernel. 832 * 833 * The list of pairs is guarded by a mutex, of course. */ 834 pipe_mutex_lock(mgr->bo_handles_mutex); 835 836 /* First check if there already is an existing bo for the handle. */ 837 bo = util_hash_table_get(mgr->bo_handles, (void*)(uintptr_t)whandle->handle); 838 if (bo) { 839 /* Increase the refcount. */ 840 struct pb_buffer *b = NULL; 841 pb_reference(&b, &bo->base); 842 goto done; 843 } 844 845 /* There isn't, create a new one. */ 846 bo = CALLOC_STRUCT(radeon_bo); 847 if (!bo) { 848 goto fail; 849 } 850 851 /* Open the BO. */ 852 open_arg.name = whandle->handle; 853 if (drmIoctl(ws->fd, DRM_IOCTL_GEM_OPEN, &open_arg)) { 854 FREE(bo); 855 goto fail; 856 } 857 bo->handle = open_arg.handle; 858 bo->name = whandle->handle; 859 860 /* Initialize it. */ 861 pipe_reference_init(&bo->base.reference, 1); 862 bo->base.alignment = 0; 863 bo->base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ; 864 bo->base.size = open_arg.size; 865 bo->base.vtbl = &radeon_bo_vtbl; 866 bo->mgr = mgr; 867 bo->rws = mgr->rws; 868 bo->va = 0; 869 pipe_mutex_init(bo->map_mutex); 870 871 util_hash_table_set(mgr->bo_handles, (void*)(uintptr_t)whandle->handle, bo); 872 873done: 874 pipe_mutex_unlock(mgr->bo_handles_mutex); 875 876 if (stride) 877 *stride = whandle->stride; 878 879 if (mgr->va) { 880 struct drm_radeon_gem_va va; 881 882 bo->va_size = ((bo->base.size + 4095) & ~4095); 883 bo->va = radeon_bomgr_find_va(mgr, bo->va_size, 1 << 20); 884 885 va.handle = bo->handle; 886 va.operation = RADEON_VA_MAP; 887 va.vm_id = 0; 888 va.offset = bo->va; 889 va.flags = RADEON_VM_PAGE_READABLE | 890 RADEON_VM_PAGE_WRITEABLE | 891 RADEON_VM_PAGE_SNOOPED; 892 va.offset = bo->va; 893 r = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_VA, &va, sizeof(va)); 894 if (r && va.operation == RADEON_VA_RESULT_ERROR) { 895 fprintf(stderr, "radeon: Failed to assign virtual address space\n"); 896 radeon_bo_destroy(&bo->base); 897 return NULL; 898 } 899 if (va.operation == RADEON_VA_RESULT_VA_EXIST) { 900 radeon_bomgr_free_va(mgr, bo->va, bo->va_size); 901 bo->va = va.offset; 902 radeon_bomgr_force_va(mgr, bo->va, bo->va_size); 903 } 904 } 905 906 return (struct pb_buffer*)bo; 907 908fail: 909 pipe_mutex_unlock(mgr->bo_handles_mutex); 910 return NULL; 911} 912 913static boolean radeon_winsys_bo_get_handle(struct pb_buffer *buffer, 914 unsigned stride, 915 struct winsys_handle *whandle) 916{ 917 struct drm_gem_flink flink; 918 struct radeon_bo *bo = get_radeon_bo(buffer); 919 920 memset(&flink, 0, sizeof(flink)); 921 922 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) { 923 if (!bo->flinked) { 924 flink.handle = bo->handle; 925 926 if (ioctl(bo->rws->fd, DRM_IOCTL_GEM_FLINK, &flink)) { 927 return FALSE; 928 } 929 930 bo->flinked = TRUE; 931 bo->flink = flink.name; 932 } 933 whandle->handle = bo->flink; 934 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) { 935 whandle->handle = bo->handle; 936 } 937 938 whandle->stride = stride; 939 return TRUE; 940} 941 942static uint64_t radeon_winsys_bo_va(struct radeon_winsys_cs_handle *buf) 943{ 944 return ((struct radeon_bo*)buf)->va; 945} 946 947void radeon_bomgr_init_functions(struct radeon_drm_winsys *ws) 948{ 949 ws->base.buffer_get_cs_handle = radeon_drm_get_cs_handle; 950 ws->base.buffer_set_tiling = radeon_bo_set_tiling; 951 ws->base.buffer_get_tiling = radeon_bo_get_tiling; 952 ws->base.buffer_map = radeon_bo_map; 953 ws->base.buffer_unmap = radeon_bo_unmap; 954 ws->base.buffer_wait = radeon_bo_wait; 955 ws->base.buffer_is_busy = radeon_bo_is_busy; 956 ws->base.buffer_create = radeon_winsys_bo_create; 957 ws->base.buffer_from_handle = radeon_winsys_bo_from_handle; 958 ws->base.buffer_get_handle = radeon_winsys_bo_get_handle; 959 ws->base.buffer_get_virtual_address = radeon_winsys_bo_va; 960} 961