radeon_drm_bo.c revision 6ccab620a0e7364ab6c0d902b3ddf58ee988f7fa 
1#define _FILE_OFFSET_BITS 64
2#include "radeon_drm_cs.h"
3
4#include "util/u_hash_table.h"
5#include "util/u_memory.h"
6#include "util/u_simple_list.h"
7#include "os/os_thread.h"
8
9#include "state_tracker/drm_driver.h"
10
11#include <sys/ioctl.h>
12#include <sys/mman.h>
13#include <xf86drm.h>
14#include <errno.h>
15
16#define RADEON_BO_FLAGS_MACRO_TILE  1
17#define RADEON_BO_FLAGS_MICRO_TILE  2
18#define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20
19
20extern const struct pb_vtbl radeon_bo_vtbl;
21
22
23static INLINE struct radeon_bo *radeon_bo(struct pb_buffer *bo)
24{
25    assert(bo->vtbl == &radeon_bo_vtbl);
26    return (struct radeon_bo *)bo;
27}
28
29struct radeon_bomgr {
30    /* Base class. */
31    struct pb_manager base;
32
33    /* Winsys. */
34    struct radeon_drm_winsys *rws;
35
36    /* List of buffer handles and its mutex. */
37    struct util_hash_table *bo_handles;
38    pipe_mutex bo_handles_mutex;
39};
40
41static INLINE struct radeon_bomgr *radeon_bomgr(struct pb_manager *mgr)
42{
43    return (struct radeon_bomgr *)mgr;
44}
45
46static struct radeon_bo *get_radeon_bo(struct pb_buffer *_buf)
47{
48    struct radeon_bo *bo = NULL;
49
50    if (_buf->vtbl == &radeon_bo_vtbl) {
51        bo = radeon_bo(_buf);
52    } else {
53	struct pb_buffer *base_buf;
54	pb_size offset;
55	pb_get_base_buffer(_buf, &base_buf, &offset);
56
57        if (base_buf->vtbl == &radeon_bo_vtbl)
58            bo = radeon_bo(base_buf);
59    }
60
61    return bo;
62}
63
64void radeon_bo_unref(struct radeon_bo *bo)
65{
66    struct drm_gem_close args = {};
67
68    if (!p_atomic_dec_zero(&bo->cref))
69        return;
70
71    if (bo->name) {
72        pipe_mutex_lock(bo->mgr->bo_handles_mutex);
73        util_hash_table_remove(bo->mgr->bo_handles,
74			       (void*)(uintptr_t)bo->name);
75        pipe_mutex_unlock(bo->mgr->bo_handles_mutex);
76    }
77
78    if (bo->ptr)
79        munmap(bo->ptr, bo->size);
80
81    /* Close object. */
82    args.handle = bo->handle;
83    drmIoctl(bo->mgr->rws->fd, DRM_IOCTL_GEM_CLOSE, &args);
84    FREE(bo);
85}
86
87static void radeon_bo_wait(struct r300_winsys_bo *_buf)
88{
89    struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf));
90    struct drm_radeon_gem_wait_idle args = {};
91
92    args.handle = bo->handle;
93    while (drmCommandWriteRead(bo->mgr->rws->fd, DRM_RADEON_GEM_WAIT_IDLE,
94                               &args, sizeof(args)) == -EBUSY);
95}
96
97static boolean radeon_bo_is_busy(struct r300_winsys_bo *_buf)
98{
99    struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf));
100    struct drm_radeon_gem_busy args = {};
101
102    args.handle = bo->handle;
103    return drmCommandWriteRead(bo->mgr->rws->fd, DRM_RADEON_GEM_BUSY,
104                               &args, sizeof(args)) != 0;
105}
106
107static void radeon_bo_destroy(struct pb_buffer *_buf)
108{
109    struct radeon_bo *bo = radeon_bo(_buf);
110
111    radeon_bo_unref(bo);
112}
113
114static unsigned get_pb_usage_from_transfer_flags(enum pipe_transfer_usage usage)
115{
116    unsigned res = 0;
117
118    if (usage & PIPE_TRANSFER_READ)
119        res |= PB_USAGE_CPU_READ;
120
121    if (usage & PIPE_TRANSFER_WRITE)
122        res |= PB_USAGE_CPU_WRITE;
123
124    if (usage & PIPE_TRANSFER_DONTBLOCK)
125        res |= PB_USAGE_DONTBLOCK;
126
127    if (usage & PIPE_TRANSFER_UNSYNCHRONIZED)
128        res |= PB_USAGE_UNSYNCHRONIZED;
129
130    return res;
131}
132
133static void *radeon_bo_map_internal(struct pb_buffer *_buf,
134                                    unsigned flags, void *flush_ctx)
135{
136    struct radeon_bo *bo = radeon_bo(_buf);
137    struct radeon_drm_cs *cs = flush_ctx;
138    struct drm_radeon_gem_mmap args = {};
139
140    if (flags & PB_USAGE_DONTBLOCK) {
141        /* Note how we use radeon_bo_is_referenced_by_cs here. There are
142         * basically two places this map function can be called from:
143         * - pb_map
144         * - create_buffer (in the buffer reuse case)
145         *
146         * Since pb managers are per-winsys managers, not per-context managers,
147         * and we shouldn't reuse buffers if they are in-use in any context,
148         * we simply ask: is this buffer referenced by *any* CS?
149         *
150         * The problem with buffer_create is that it comes from pipe_screen,
151         * so we have no CS to look at, though luckily the following code
152         * is sufficient to tell whether the buffer is in use. */
153        if (_buf->base.usage & RADEON_PB_USAGE_CACHE) {
154            if (radeon_bo_is_referenced_by_any_cs(bo))
155		return NULL;
156	}
157
158        if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) {
159            cs->flush_cs(cs->flush_data);
160            return NULL; /* It's very unlikely that the buffer is not busy. */
161        }
162
163        if (radeon_bo_is_busy((struct r300_winsys_bo*)bo)) {
164            return NULL;
165        }
166    }
167
168    /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
169    if (!(flags & PB_USAGE_UNSYNCHRONIZED)) {
170        if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) {
171            cs->flush_cs(cs->flush_data);
172        }
173
174        radeon_bo_wait((struct r300_winsys_bo*)bo);
175    }
176
177    /* Map buffer if it's not already mapped. */
178    /* XXX We may get a race in bo->ptr. */
179    if (!bo->ptr) {
180        void *ptr;
181
182        args.handle = bo->handle;
183        args.offset = 0;
184        args.size = (uint64_t)bo->size;
185        if (drmCommandWriteRead(bo->mgr->rws->fd,
186                                DRM_RADEON_GEM_MMAP,
187                                &args,
188                                sizeof(args))) {
189            fprintf(stderr, "radeon: gem_mmap failed: %p 0x%08X\n",
190                    bo, bo->handle);
191            return NULL;
192        }
193        ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED,
194                   bo->mgr->rws->fd, args.addr_ptr);
195        if (ptr == MAP_FAILED) {
196            fprintf(stderr, "radeon: mmap failed, errno: %i\n", errno);
197            return NULL;
198        }
199        bo->ptr = ptr;
200    }
201
202    return bo->ptr;
203}
204
205static void radeon_bo_unmap_internal(struct pb_buffer *_buf)
206{
207    /* NOP */
208}
209
210static void radeon_bo_get_base_buffer(struct pb_buffer *buf,
211				      struct pb_buffer **base_buf,
212				      unsigned *offset)
213{
214    *base_buf = buf;
215    *offset = 0;
216}
217
218static enum pipe_error radeon_bo_validate(struct pb_buffer *_buf,
219					  struct pb_validate *vl,
220					  unsigned flags)
221{
222    /* Always pinned */
223    return PIPE_OK;
224}
225
226static void radeon_bo_fence(struct pb_buffer *buf,
227                            struct pipe_fence_handle *fence)
228{
229}
230
231const struct pb_vtbl radeon_bo_vtbl = {
232    radeon_bo_destroy,
233    radeon_bo_map_internal,
234    radeon_bo_unmap_internal,
235    radeon_bo_validate,
236    radeon_bo_fence,
237    radeon_bo_get_base_buffer,
238};
239
240static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr,
241						pb_size size,
242						const struct pb_desc *desc)
243{
244    struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
245    struct radeon_drm_winsys *rws = mgr->rws;
246    struct radeon_bo *bo;
247    struct drm_radeon_gem_create args = {};
248
249    args.size = size;
250    args.alignment = desc->alignment;
251    args.initial_domain =
252        (desc->usage & RADEON_PB_USAGE_DOMAIN_GTT  ?
253         RADEON_GEM_DOMAIN_GTT  : 0) |
254        (desc->usage & RADEON_PB_USAGE_DOMAIN_VRAM ?
255         RADEON_GEM_DOMAIN_VRAM : 0);
256
257    if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE,
258                            &args, sizeof(args))) {
259        fprintf(stderr, "Failed to allocate :\n");
260        fprintf(stderr, "   size      : %d bytes\n", size);
261        fprintf(stderr, "   alignment : %d bytes\n", desc->alignment);
262        fprintf(stderr, "   domains   : %d\n", args.initial_domain);
263        return NULL;
264    }
265
266    bo = CALLOC_STRUCT(radeon_bo);
267    if (!bo)
268	return NULL;
269
270    pipe_reference_init(&bo->base.base.reference, 1);
271    bo->base.base.alignment = desc->alignment;
272    bo->base.base.usage = desc->usage;
273    bo->base.base.size = size;
274    bo->base.vtbl = &radeon_bo_vtbl;
275    bo->mgr = mgr;
276    bo->handle = args.handle;
277    bo->size = size;
278
279    radeon_bo_ref(bo);
280    return &bo->base;
281}
282
283static void radeon_bomgr_flush(struct pb_manager *mgr)
284{
285    /* NOP */
286}
287
288static void radeon_bomgr_destroy(struct pb_manager *_mgr)
289{
290    struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
291    util_hash_table_destroy(mgr->bo_handles);
292    pipe_mutex_destroy(mgr->bo_handles_mutex);
293    FREE(mgr);
294}
295
296static unsigned handle_hash(void *key)
297{
298    return (unsigned)key;
299}
300
301static int handle_compare(void *key1, void *key2)
302{
303    return !((int)key1 == (int)key2);
304}
305
306struct pb_manager *radeon_bomgr_create(struct radeon_drm_winsys *rws)
307{
308    struct radeon_bomgr *mgr;
309
310    mgr = CALLOC_STRUCT(radeon_bomgr);
311    if (!mgr)
312	return NULL;
313
314    mgr->base.destroy = radeon_bomgr_destroy;
315    mgr->base.create_buffer = radeon_bomgr_create_bo;
316    mgr->base.flush = radeon_bomgr_flush;
317
318    mgr->rws = rws;
319    mgr->bo_handles = util_hash_table_create(handle_hash, handle_compare);
320    pipe_mutex_init(mgr->bo_handles_mutex);
321    return &mgr->base;
322}
323
324static void *radeon_bo_map(struct r300_winsys_bo *buf,
325                           struct r300_winsys_cs *cs,
326                           enum pipe_transfer_usage usage)
327{
328    struct pb_buffer *_buf = pb_buffer(buf);
329
330    return pb_map(_buf, get_pb_usage_from_transfer_flags(usage), cs);
331}
332
333static void radeon_bo_get_tiling(struct r300_winsys_bo *_buf,
334                                 enum r300_buffer_tiling *microtiled,
335                                 enum r300_buffer_tiling *macrotiled)
336{
337    struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf));
338    struct drm_radeon_gem_set_tiling args = {};
339
340    args.handle = bo->handle;
341
342    drmCommandWriteRead(bo->mgr->rws->fd,
343                        DRM_RADEON_GEM_GET_TILING,
344                        &args,
345                        sizeof(args));
346
347    *microtiled = R300_BUFFER_LINEAR;
348    *macrotiled = R300_BUFFER_LINEAR;
349    if (args.tiling_flags & RADEON_BO_FLAGS_MICRO_TILE)
350	*microtiled = R300_BUFFER_TILED;
351
352    if (args.tiling_flags & RADEON_BO_FLAGS_MACRO_TILE)
353	*macrotiled = R300_BUFFER_TILED;
354}
355
356static void radeon_bo_set_tiling(struct r300_winsys_bo *_buf,
357                                 enum r300_buffer_tiling microtiled,
358                                 enum r300_buffer_tiling macrotiled,
359                                 uint32_t pitch)
360{
361    struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf));
362    struct drm_radeon_gem_set_tiling args = {};
363
364    if (microtiled == R300_BUFFER_TILED)
365        args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE;
366    else if (microtiled == R300_BUFFER_SQUARETILED)
367        args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE_SQUARE;
368
369    if (macrotiled == R300_BUFFER_TILED)
370        args.tiling_flags |= RADEON_BO_FLAGS_MACRO_TILE;
371
372    args.handle = bo->handle;
373    args.pitch = pitch;
374
375    drmCommandWriteRead(bo->mgr->rws->fd,
376                        DRM_RADEON_GEM_SET_TILING,
377                        &args,
378                        sizeof(args));
379}
380
381static struct r300_winsys_cs_handle *radeon_drm_get_cs_handle(
382        struct r300_winsys_bo *_buf)
383{
384    /* return radeon_bo. */
385    return (struct r300_winsys_cs_handle*)
386            get_radeon_bo(pb_buffer(_buf));
387}
388
389static unsigned get_pb_usage_from_create_flags(unsigned bind, unsigned usage,
390                                               enum r300_buffer_domain domain)
391{
392    unsigned res = 0;
393
394    if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER))
395        res |= RADEON_PB_USAGE_CACHE;
396
397    if (domain & R300_DOMAIN_GTT)
398        res |= RADEON_PB_USAGE_DOMAIN_GTT;
399
400    if (domain & R300_DOMAIN_VRAM)
401        res |= RADEON_PB_USAGE_DOMAIN_VRAM;
402
403    return res;
404}
405
406static struct r300_winsys_bo *
407radeon_winsys_bo_create(struct r300_winsys_screen *rws,
408                        unsigned size,
409                        unsigned alignment,
410                        unsigned bind,
411                        unsigned usage,
412                        enum r300_buffer_domain domain)
413{
414    struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
415    struct pb_desc desc;
416    struct pb_manager *provider;
417    struct pb_buffer *buffer;
418
419    memset(&desc, 0, sizeof(desc));
420    desc.alignment = alignment;
421    desc.usage = get_pb_usage_from_create_flags(bind, usage, domain);
422
423    /* Assign a buffer manager. */
424    if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER))
425	provider = ws->cman;
426    else
427        provider = ws->kman;
428
429    buffer = provider->create_buffer(provider, size, &desc);
430    if (!buffer)
431	return NULL;
432
433    return (struct r300_winsys_bo*)buffer;
434}
435
436static struct r300_winsys_bo *radeon_winsys_bo_from_handle(struct r300_winsys_screen *rws,
437                                                           struct winsys_handle *whandle,
438                                                           unsigned *stride,
439                                                           unsigned *size)
440{
441    struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
442    struct radeon_bo *bo;
443    struct radeon_bomgr *mgr = radeon_bomgr(ws->kman);
444    struct drm_gem_open open_arg = {};
445
446    /* We must maintain a list of pairs <handle, bo>, so that we always return
447     * the same BO for one particular handle. If we didn't do that and created
448     * more than one BO for the same handle and then relocated them in a CS,
449     * we would hit a deadlock in the kernel.
450     *
451     * The list of pairs is guarded by a mutex, of course. */
452    pipe_mutex_lock(mgr->bo_handles_mutex);
453
454    /* First check if there already is an existing bo for the handle. */
455    bo = util_hash_table_get(mgr->bo_handles, (void*)(uintptr_t)whandle->handle);
456    if (bo) {
457        /* Increase the refcount. */
458        struct pb_buffer *b = NULL;
459        pb_reference(&b, &bo->base);
460        goto done;
461    }
462
463    /* There isn't, create a new one. */
464    bo = CALLOC_STRUCT(radeon_bo);
465    if (!bo) {
466        goto fail;
467    }
468
469    /* Open the BO. */
470    open_arg.name = whandle->handle;
471    if (drmIoctl(ws->fd, DRM_IOCTL_GEM_OPEN, &open_arg)) {
472        goto fail;
473    }
474    bo->handle = open_arg.handle;
475    bo->size = open_arg.size;
476    bo->name = whandle->handle;
477    radeon_bo_ref(bo);
478
479    /* Initialize it. */
480    pipe_reference_init(&bo->base.base.reference, 1);
481    bo->base.base.alignment = 0;
482    bo->base.base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ;
483    bo->base.base.size = bo->size;
484    bo->base.vtbl = &radeon_bo_vtbl;
485    bo->mgr = mgr;
486
487    util_hash_table_set(mgr->bo_handles, (void*)(uintptr_t)whandle->handle, bo);
488
489done:
490    pipe_mutex_unlock(mgr->bo_handles_mutex);
491
492    if (stride)
493        *stride = whandle->stride;
494    if (size)
495        *size = bo->base.base.size;
496
497    return (struct r300_winsys_bo*)bo;
498
499fail:
500    pipe_mutex_unlock(mgr->bo_handles_mutex);
501    return NULL;
502}
503
504static boolean radeon_winsys_bo_get_handle(struct r300_winsys_bo *buffer,
505                                           unsigned stride,
506                                           struct winsys_handle *whandle)
507{
508    struct drm_gem_flink flink = {};
509    struct radeon_bo *bo = get_radeon_bo(pb_buffer(buffer));
510    whandle->stride = stride;
511
512
513    if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
514        if (!bo->flinked) {
515            flink.handle = bo->handle;
516
517            if (ioctl(bo->mgr->rws->fd, DRM_IOCTL_GEM_FLINK, &flink)) {
518                return FALSE;
519            }
520
521            bo->flinked = TRUE;
522            bo->flink = flink.name;
523        }
524        whandle->handle = bo->flink;
525    } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
526        whandle->handle = bo->handle;
527    }
528    return TRUE;
529}
530
531void radeon_bomgr_init_functions(struct radeon_drm_winsys *ws)
532{
533    ws->base.buffer_get_cs_handle = radeon_drm_get_cs_handle;
534    ws->base.buffer_set_tiling = radeon_bo_set_tiling;
535    ws->base.buffer_get_tiling = radeon_bo_get_tiling;
536    ws->base.buffer_map = radeon_bo_map;
537    ws->base.buffer_unmap = pb_unmap;
538    ws->base.buffer_wait = radeon_bo_wait;
539    ws->base.buffer_is_busy = radeon_bo_is_busy;
540    ws->base.buffer_create = radeon_winsys_bo_create;
541    ws->base.buffer_from_handle = radeon_winsys_bo_from_handle;
542    ws->base.buffer_get_handle = radeon_winsys_bo_get_handle;
543}
544