radeon_drm_bo.c revision c35572352e3e92683988ee8d151b47f4190d62f9
1/* 2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com> 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 */ 26 27#define _FILE_OFFSET_BITS 64 28#include "radeon_drm_cs.h" 29 30#include "util/u_hash_table.h" 31#include "util/u_memory.h" 32#include "util/u_simple_list.h" 33#include "os/os_thread.h" 34 35#include "state_tracker/drm_driver.h" 36 37#include <sys/ioctl.h> 38#include <sys/mman.h> 39#include <xf86drm.h> 40#include <errno.h> 41 42#define RADEON_BO_FLAGS_MACRO_TILE 1 43#define RADEON_BO_FLAGS_MICRO_TILE 2 44#define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20 45 46extern const struct pb_vtbl radeon_bo_vtbl; 47 48 49static INLINE struct radeon_bo *radeon_bo(struct pb_buffer *bo) 50{ 51 assert(bo->vtbl == &radeon_bo_vtbl); 52 return (struct radeon_bo *)bo; 53} 54 55struct radeon_bomgr { 56 /* Base class. */ 57 struct pb_manager base; 58 59 /* Winsys. */ 60 struct radeon_drm_winsys *rws; 61 62 /* List of buffer handles and its mutex. */ 63 struct util_hash_table *bo_handles; 64 pipe_mutex bo_handles_mutex; 65}; 66 67static INLINE struct radeon_bomgr *radeon_bomgr(struct pb_manager *mgr) 68{ 69 return (struct radeon_bomgr *)mgr; 70} 71 72static struct radeon_bo *get_radeon_bo(struct pb_buffer *_buf) 73{ 74 struct radeon_bo *bo = NULL; 75 76 if (_buf->vtbl == &radeon_bo_vtbl) { 77 bo = radeon_bo(_buf); 78 } else { 79 struct pb_buffer *base_buf; 80 pb_size offset; 81 pb_get_base_buffer(_buf, &base_buf, &offset); 82 83 if (base_buf->vtbl == &radeon_bo_vtbl) 84 bo = radeon_bo(base_buf); 85 } 86 87 return bo; 88} 89 90 91 92static void radeon_bo_wait(struct r300_winsys_bo *_buf) 93{ 94 struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf)); 95 struct drm_radeon_gem_wait_idle args = {}; 96 97 while (p_atomic_read(&bo->num_active_ioctls)) { 98 sched_yield(); 99 } 100 101 args.handle = bo->handle; 102 while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT_IDLE, 103 &args, sizeof(args)) == -EBUSY); 104} 105 106static boolean radeon_bo_is_busy(struct r300_winsys_bo *_buf) 107{ 108 struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf)); 109 struct drm_radeon_gem_busy args = {}; 110 111 if (p_atomic_read(&bo->num_active_ioctls)) { 112 return TRUE; 113 } 114 115 args.handle = bo->handle; 116 return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_BUSY, 117 &args, sizeof(args)) != 0; 118} 119 120static void radeon_bo_destroy(struct pb_buffer *_buf) 121{ 122 struct radeon_bo *bo = radeon_bo(_buf); 123 struct drm_gem_close args = {}; 124 125 if (bo->name) { 126 pipe_mutex_lock(bo->mgr->bo_handles_mutex); 127 util_hash_table_remove(bo->mgr->bo_handles, 128 (void*)(uintptr_t)bo->name); 129 pipe_mutex_unlock(bo->mgr->bo_handles_mutex); 130 } 131 132 if (bo->ptr) 133 munmap(bo->ptr, bo->size); 134 135 /* Close object. */ 136 args.handle = bo->handle; 137 drmIoctl(bo->rws->fd, DRM_IOCTL_GEM_CLOSE, &args); 138 pipe_mutex_destroy(bo->map_mutex); 139 FREE(bo); 140} 141 142static unsigned get_pb_usage_from_transfer_flags(enum pipe_transfer_usage usage) 143{ 144 unsigned res = 0; 145 146 if (usage & PIPE_TRANSFER_DONTBLOCK) 147 res |= PB_USAGE_DONTBLOCK; 148 149 if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) 150 res |= PB_USAGE_UNSYNCHRONIZED; 151 152 return res; 153} 154 155static void *radeon_bo_map_internal(struct pb_buffer *_buf, 156 unsigned flags, void *flush_ctx) 157{ 158 struct radeon_bo *bo = radeon_bo(_buf); 159 struct radeon_drm_cs *cs = flush_ctx; 160 struct drm_radeon_gem_mmap args = {}; 161 void *ptr; 162 163 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */ 164 if (!(flags & PB_USAGE_UNSYNCHRONIZED)) { 165 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */ 166 if (flags & PB_USAGE_DONTBLOCK) { 167 if (radeon_bo_is_referenced_by_cs(cs, bo)) { 168 cs->flush_cs(cs->flush_data, R300_FLUSH_ASYNC); 169 return NULL; 170 } 171 172 if (radeon_bo_is_busy((struct r300_winsys_bo*)bo)) { 173 return NULL; 174 } 175 } else { 176 if (radeon_bo_is_referenced_by_cs(cs, bo)) { 177 cs->flush_cs(cs->flush_data, 0); 178 } else { 179 /* Try to avoid busy-waiting in radeon_bo_wait. */ 180 if (p_atomic_read(&bo->num_active_ioctls)) 181 radeon_drm_cs_sync_flush(cs); 182 } 183 184 radeon_bo_wait((struct r300_winsys_bo*)bo); 185 } 186 } 187 188 /* Return the pointer if it's already mapped. */ 189 if (bo->ptr) 190 return bo->ptr; 191 192 /* Map the buffer. */ 193 pipe_mutex_lock(bo->map_mutex); 194 args.handle = bo->handle; 195 args.offset = 0; 196 args.size = (uint64_t)bo->size; 197 if (drmCommandWriteRead(bo->rws->fd, 198 DRM_RADEON_GEM_MMAP, 199 &args, 200 sizeof(args))) { 201 pipe_mutex_unlock(bo->map_mutex); 202 fprintf(stderr, "radeon: gem_mmap failed: %p 0x%08X\n", 203 bo, bo->handle); 204 return NULL; 205 } 206 207 ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, 208 bo->rws->fd, args.addr_ptr); 209 if (ptr == MAP_FAILED) { 210 pipe_mutex_unlock(bo->map_mutex); 211 fprintf(stderr, "radeon: mmap failed, errno: %i\n", errno); 212 return NULL; 213 } 214 bo->ptr = ptr; 215 pipe_mutex_unlock(bo->map_mutex); 216 217 return bo->ptr; 218} 219 220static void radeon_bo_unmap_internal(struct pb_buffer *_buf) 221{ 222 /* NOP */ 223} 224 225static void radeon_bo_get_base_buffer(struct pb_buffer *buf, 226 struct pb_buffer **base_buf, 227 unsigned *offset) 228{ 229 *base_buf = buf; 230 *offset = 0; 231} 232 233static enum pipe_error radeon_bo_validate(struct pb_buffer *_buf, 234 struct pb_validate *vl, 235 unsigned flags) 236{ 237 /* Always pinned */ 238 return PIPE_OK; 239} 240 241static void radeon_bo_fence(struct pb_buffer *buf, 242 struct pipe_fence_handle *fence) 243{ 244} 245 246const struct pb_vtbl radeon_bo_vtbl = { 247 radeon_bo_destroy, 248 radeon_bo_map_internal, 249 radeon_bo_unmap_internal, 250 radeon_bo_validate, 251 radeon_bo_fence, 252 radeon_bo_get_base_buffer, 253}; 254 255static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr, 256 pb_size size, 257 const struct pb_desc *desc) 258{ 259 struct radeon_bomgr *mgr = radeon_bomgr(_mgr); 260 struct radeon_drm_winsys *rws = mgr->rws; 261 struct radeon_bo *bo; 262 struct drm_radeon_gem_create args = {}; 263 264 args.size = size; 265 args.alignment = desc->alignment; 266 args.initial_domain = 267 (desc->usage & RADEON_PB_USAGE_DOMAIN_GTT ? 268 RADEON_GEM_DOMAIN_GTT : 0) | 269 (desc->usage & RADEON_PB_USAGE_DOMAIN_VRAM ? 270 RADEON_GEM_DOMAIN_VRAM : 0); 271 272 if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE, 273 &args, sizeof(args))) { 274 fprintf(stderr, "Failed to allocate :\n"); 275 fprintf(stderr, " size : %d bytes\n", size); 276 fprintf(stderr, " alignment : %d bytes\n", desc->alignment); 277 fprintf(stderr, " domains : %d\n", args.initial_domain); 278 return NULL; 279 } 280 281 bo = CALLOC_STRUCT(radeon_bo); 282 if (!bo) 283 return NULL; 284 285 pipe_reference_init(&bo->base.base.reference, 1); 286 bo->base.base.alignment = desc->alignment; 287 bo->base.base.usage = desc->usage; 288 bo->base.base.size = size; 289 bo->base.vtbl = &radeon_bo_vtbl; 290 bo->mgr = mgr; 291 bo->rws = mgr->rws; 292 bo->handle = args.handle; 293 bo->size = size; 294 pipe_mutex_init(bo->map_mutex); 295 296 return &bo->base; 297} 298 299static void radeon_bomgr_flush(struct pb_manager *mgr) 300{ 301 /* NOP */ 302} 303 304/* This is for the cache bufmgr. */ 305static boolean radeon_bomgr_is_buffer_busy(struct pb_manager *_mgr, 306 struct pb_buffer *_buf) 307{ 308 struct radeon_bo *bo = radeon_bo(_buf); 309 310 if (radeon_bo_is_referenced_by_any_cs(bo)) { 311 return TRUE; 312 } 313 314 if (radeon_bo_is_busy((struct r300_winsys_bo*)bo)) { 315 return TRUE; 316 } 317 318 return FALSE; 319} 320 321static void radeon_bomgr_destroy(struct pb_manager *_mgr) 322{ 323 struct radeon_bomgr *mgr = radeon_bomgr(_mgr); 324 util_hash_table_destroy(mgr->bo_handles); 325 pipe_mutex_destroy(mgr->bo_handles_mutex); 326 FREE(mgr); 327} 328 329#define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x))) 330 331static unsigned handle_hash(void *key) 332{ 333 return PTR_TO_UINT(key); 334} 335 336static int handle_compare(void *key1, void *key2) 337{ 338 return PTR_TO_UINT(key1) != PTR_TO_UINT(key2); 339} 340 341struct pb_manager *radeon_bomgr_create(struct radeon_drm_winsys *rws) 342{ 343 struct radeon_bomgr *mgr; 344 345 mgr = CALLOC_STRUCT(radeon_bomgr); 346 if (!mgr) 347 return NULL; 348 349 mgr->base.destroy = radeon_bomgr_destroy; 350 mgr->base.create_buffer = radeon_bomgr_create_bo; 351 mgr->base.flush = radeon_bomgr_flush; 352 mgr->base.is_buffer_busy = radeon_bomgr_is_buffer_busy; 353 354 mgr->rws = rws; 355 mgr->bo_handles = util_hash_table_create(handle_hash, handle_compare); 356 pipe_mutex_init(mgr->bo_handles_mutex); 357 return &mgr->base; 358} 359 360static void *radeon_bo_map(struct r300_winsys_bo *buf, 361 struct r300_winsys_cs *cs, 362 enum pipe_transfer_usage usage) 363{ 364 struct pb_buffer *_buf = pb_buffer(buf); 365 366 return pb_map(_buf, get_pb_usage_from_transfer_flags(usage), cs); 367} 368 369static void radeon_bo_get_tiling(struct r300_winsys_bo *_buf, 370 enum r300_buffer_tiling *microtiled, 371 enum r300_buffer_tiling *macrotiled) 372{ 373 struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf)); 374 struct drm_radeon_gem_set_tiling args = {}; 375 376 args.handle = bo->handle; 377 378 drmCommandWriteRead(bo->rws->fd, 379 DRM_RADEON_GEM_GET_TILING, 380 &args, 381 sizeof(args)); 382 383 *microtiled = R300_BUFFER_LINEAR; 384 *macrotiled = R300_BUFFER_LINEAR; 385 if (args.tiling_flags & RADEON_BO_FLAGS_MICRO_TILE) 386 *microtiled = R300_BUFFER_TILED; 387 388 if (args.tiling_flags & RADEON_BO_FLAGS_MACRO_TILE) 389 *macrotiled = R300_BUFFER_TILED; 390} 391 392static void radeon_bo_set_tiling(struct r300_winsys_bo *_buf, 393 struct r300_winsys_cs *rcs, 394 enum r300_buffer_tiling microtiled, 395 enum r300_buffer_tiling macrotiled, 396 uint32_t pitch) 397{ 398 struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf)); 399 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); 400 struct drm_radeon_gem_set_tiling args = {}; 401 402 /* Tiling determines how DRM treats the buffer data. 403 * We must flush CS when changing it if the buffer is referenced. */ 404 if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) { 405 cs->flush_cs(cs->flush_data, 0); 406 } 407 408 while (p_atomic_read(&bo->num_active_ioctls)) { 409 sched_yield(); 410 } 411 412 if (microtiled == R300_BUFFER_TILED) 413 args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE; 414 else if (microtiled == R300_BUFFER_SQUARETILED) 415 args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE_SQUARE; 416 417 if (macrotiled == R300_BUFFER_TILED) 418 args.tiling_flags |= RADEON_BO_FLAGS_MACRO_TILE; 419 420 args.handle = bo->handle; 421 args.pitch = pitch; 422 423 drmCommandWriteRead(bo->rws->fd, 424 DRM_RADEON_GEM_SET_TILING, 425 &args, 426 sizeof(args)); 427} 428 429static struct r300_winsys_cs_handle *radeon_drm_get_cs_handle( 430 struct r300_winsys_bo *_buf) 431{ 432 /* return radeon_bo. */ 433 return (struct r300_winsys_cs_handle*) 434 get_radeon_bo(pb_buffer(_buf)); 435} 436 437static unsigned get_pb_usage_from_create_flags(unsigned bind, unsigned usage, 438 enum r300_buffer_domain domain) 439{ 440 unsigned res = 0; 441 442 if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) 443 res |= RADEON_PB_USAGE_CACHE; 444 445 if (domain & R300_DOMAIN_GTT) 446 res |= RADEON_PB_USAGE_DOMAIN_GTT; 447 448 if (domain & R300_DOMAIN_VRAM) 449 res |= RADEON_PB_USAGE_DOMAIN_VRAM; 450 451 return res; 452} 453 454static struct r300_winsys_bo * 455radeon_winsys_bo_create(struct r300_winsys_screen *rws, 456 unsigned size, 457 unsigned alignment, 458 unsigned bind, 459 unsigned usage, 460 enum r300_buffer_domain domain) 461{ 462 struct radeon_drm_winsys *ws = radeon_drm_winsys(rws); 463 struct pb_desc desc; 464 struct pb_manager *provider; 465 struct pb_buffer *buffer; 466 467 memset(&desc, 0, sizeof(desc)); 468 desc.alignment = alignment; 469 desc.usage = get_pb_usage_from_create_flags(bind, usage, domain); 470 471 /* Assign a buffer manager. */ 472 if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) 473 provider = ws->cman; 474 else 475 provider = ws->kman; 476 477 buffer = provider->create_buffer(provider, size, &desc); 478 if (!buffer) 479 return NULL; 480 481 return (struct r300_winsys_bo*)buffer; 482} 483 484static struct r300_winsys_bo *radeon_winsys_bo_from_handle(struct r300_winsys_screen *rws, 485 struct winsys_handle *whandle, 486 unsigned *stride, 487 unsigned *size) 488{ 489 struct radeon_drm_winsys *ws = radeon_drm_winsys(rws); 490 struct radeon_bo *bo; 491 struct radeon_bomgr *mgr = radeon_bomgr(ws->kman); 492 struct drm_gem_open open_arg = {}; 493 494 /* We must maintain a list of pairs <handle, bo>, so that we always return 495 * the same BO for one particular handle. If we didn't do that and created 496 * more than one BO for the same handle and then relocated them in a CS, 497 * we would hit a deadlock in the kernel. 498 * 499 * The list of pairs is guarded by a mutex, of course. */ 500 pipe_mutex_lock(mgr->bo_handles_mutex); 501 502 /* First check if there already is an existing bo for the handle. */ 503 bo = util_hash_table_get(mgr->bo_handles, (void*)(uintptr_t)whandle->handle); 504 if (bo) { 505 /* Increase the refcount. */ 506 struct pb_buffer *b = NULL; 507 pb_reference(&b, &bo->base); 508 goto done; 509 } 510 511 /* There isn't, create a new one. */ 512 bo = CALLOC_STRUCT(radeon_bo); 513 if (!bo) { 514 goto fail; 515 } 516 517 /* Open the BO. */ 518 open_arg.name = whandle->handle; 519 if (drmIoctl(ws->fd, DRM_IOCTL_GEM_OPEN, &open_arg)) { 520 FREE(bo); 521 goto fail; 522 } 523 bo->handle = open_arg.handle; 524 bo->size = open_arg.size; 525 bo->name = whandle->handle; 526 527 /* Initialize it. */ 528 pipe_reference_init(&bo->base.base.reference, 1); 529 bo->base.base.alignment = 0; 530 bo->base.base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ; 531 bo->base.base.size = bo->size; 532 bo->base.vtbl = &radeon_bo_vtbl; 533 bo->mgr = mgr; 534 bo->rws = mgr->rws; 535 pipe_mutex_init(bo->map_mutex); 536 537 util_hash_table_set(mgr->bo_handles, (void*)(uintptr_t)whandle->handle, bo); 538 539done: 540 pipe_mutex_unlock(mgr->bo_handles_mutex); 541 542 if (stride) 543 *stride = whandle->stride; 544 if (size) 545 *size = bo->base.base.size; 546 547 return (struct r300_winsys_bo*)bo; 548 549fail: 550 pipe_mutex_unlock(mgr->bo_handles_mutex); 551 return NULL; 552} 553 554static boolean radeon_winsys_bo_get_handle(struct r300_winsys_bo *buffer, 555 unsigned stride, 556 struct winsys_handle *whandle) 557{ 558 struct drm_gem_flink flink = {}; 559 struct radeon_bo *bo = get_radeon_bo(pb_buffer(buffer)); 560 561 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) { 562 if (!bo->flinked) { 563 flink.handle = bo->handle; 564 565 if (ioctl(bo->rws->fd, DRM_IOCTL_GEM_FLINK, &flink)) { 566 return FALSE; 567 } 568 569 bo->flinked = TRUE; 570 bo->flink = flink.name; 571 } 572 whandle->handle = bo->flink; 573 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) { 574 whandle->handle = bo->handle; 575 } 576 577 whandle->stride = stride; 578 return TRUE; 579} 580 581void radeon_bomgr_init_functions(struct radeon_drm_winsys *ws) 582{ 583 ws->base.buffer_get_cs_handle = radeon_drm_get_cs_handle; 584 ws->base.buffer_set_tiling = radeon_bo_set_tiling; 585 ws->base.buffer_get_tiling = radeon_bo_get_tiling; 586 ws->base.buffer_map = radeon_bo_map; 587 ws->base.buffer_unmap = pb_unmap; 588 ws->base.buffer_wait = radeon_bo_wait; 589 ws->base.buffer_is_busy = radeon_bo_is_busy; 590 ws->base.buffer_create = radeon_winsys_bo_create; 591 ws->base.buffer_from_handle = radeon_winsys_bo_from_handle; 592 ws->base.buffer_get_handle = radeon_winsys_bo_get_handle; 593} 594