radeon_drm_bo.c revision fa3f1348e49feeac511dbe5b22bbddc47f56ba81
1/* 2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com> 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 */ 26 27#define _FILE_OFFSET_BITS 64 28#include "radeon_drm_cs.h" 29 30#include "util/u_hash_table.h" 31#include "util/u_memory.h" 32#include "util/u_simple_list.h" 33#include "os/os_thread.h" 34 35#include "state_tracker/drm_driver.h" 36 37#include <sys/ioctl.h> 38#include <sys/mman.h> 39#include <xf86drm.h> 40#include <errno.h> 41 42#define RADEON_BO_FLAGS_MACRO_TILE 1 43#define RADEON_BO_FLAGS_MICRO_TILE 2 44#define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20 45 46extern const struct pb_vtbl radeon_bo_vtbl; 47 48 49static INLINE struct radeon_bo *radeon_bo(struct pb_buffer *bo) 50{ 51 assert(bo->vtbl == &radeon_bo_vtbl); 52 return (struct radeon_bo *)bo; 53} 54 55struct radeon_bomgr { 56 /* Base class. */ 57 struct pb_manager base; 58 59 /* Winsys. */ 60 struct radeon_drm_winsys *rws; 61 62 /* List of buffer handles and its mutex. */ 63 struct util_hash_table *bo_handles; 64 pipe_mutex bo_handles_mutex; 65}; 66 67static INLINE struct radeon_bomgr *radeon_bomgr(struct pb_manager *mgr) 68{ 69 return (struct radeon_bomgr *)mgr; 70} 71 72static struct radeon_bo *get_radeon_bo(struct pb_buffer *_buf) 73{ 74 struct radeon_bo *bo = NULL; 75 76 if (_buf->vtbl == &radeon_bo_vtbl) { 77 bo = radeon_bo(_buf); 78 } else { 79 struct pb_buffer *base_buf; 80 pb_size offset; 81 pb_get_base_buffer(_buf, &base_buf, &offset); 82 83 if (base_buf->vtbl == &radeon_bo_vtbl) 84 bo = radeon_bo(base_buf); 85 } 86 87 return bo; 88} 89 90void radeon_bo_unref(struct radeon_bo *bo) 91{ 92 struct drm_gem_close args = {}; 93 94 if (!p_atomic_dec_zero(&bo->ref_count)) 95 return; 96 97 if (bo->name) { 98 pipe_mutex_lock(bo->mgr->bo_handles_mutex); 99 util_hash_table_remove(bo->mgr->bo_handles, 100 (void*)(uintptr_t)bo->name); 101 pipe_mutex_unlock(bo->mgr->bo_handles_mutex); 102 } 103 104 if (bo->ptr) 105 munmap(bo->ptr, bo->size); 106 107 /* Close object. */ 108 args.handle = bo->handle; 109 drmIoctl(bo->rws->fd, DRM_IOCTL_GEM_CLOSE, &args); 110 pipe_mutex_destroy(bo->map_mutex); 111 FREE(bo); 112} 113 114static void radeon_bo_wait(struct r300_winsys_bo *_buf) 115{ 116 struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf)); 117 struct drm_radeon_gem_wait_idle args = {}; 118 119 while (p_atomic_read(&bo->num_active_ioctls)) { 120 sched_yield(); 121 } 122 123 args.handle = bo->handle; 124 while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT_IDLE, 125 &args, sizeof(args)) == -EBUSY); 126} 127 128static boolean radeon_bo_is_busy(struct r300_winsys_bo *_buf) 129{ 130 struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf)); 131 struct drm_radeon_gem_busy args = {}; 132 133 if (p_atomic_read(&bo->num_active_ioctls)) { 134 return TRUE; 135 } 136 137 args.handle = bo->handle; 138 return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_BUSY, 139 &args, sizeof(args)) != 0; 140} 141 142static void radeon_bo_destroy(struct pb_buffer *_buf) 143{ 144 struct radeon_bo *bo = radeon_bo(_buf); 145 146 radeon_bo_unref(bo); 147} 148 149static unsigned get_pb_usage_from_transfer_flags(enum pipe_transfer_usage usage) 150{ 151 unsigned res = 0; 152 153 if (usage & PIPE_TRANSFER_DONTBLOCK) 154 res |= PB_USAGE_DONTBLOCK; 155 156 if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) 157 res |= PB_USAGE_UNSYNCHRONIZED; 158 159 return res; 160} 161 162static void *radeon_bo_map_internal(struct pb_buffer *_buf, 163 unsigned flags, void *flush_ctx) 164{ 165 struct radeon_bo *bo = radeon_bo(_buf); 166 struct radeon_drm_cs *cs = flush_ctx; 167 struct drm_radeon_gem_mmap args = {}; 168 void *ptr; 169 170 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */ 171 if (!(flags & PB_USAGE_UNSYNCHRONIZED)) { 172 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */ 173 if (flags & PB_USAGE_DONTBLOCK) { 174 if (radeon_bo_is_referenced_by_cs(cs, bo)) { 175 cs->flush_cs(cs->flush_data); 176 return NULL; 177 } 178 179 if (radeon_bo_is_busy((struct r300_winsys_bo*)bo)) { 180 return NULL; 181 } 182 } else { 183 if (radeon_bo_is_referenced_by_cs(cs, bo)) { 184 cs->flush_cs(cs->flush_data); 185 } 186 187 radeon_bo_wait((struct r300_winsys_bo*)bo); 188 } 189 } 190 191 /* Return the pointer if it's already mapped. */ 192 if (bo->ptr) 193 return bo->ptr; 194 195 /* Map the buffer. */ 196 pipe_mutex_lock(bo->map_mutex); 197 args.handle = bo->handle; 198 args.offset = 0; 199 args.size = (uint64_t)bo->size; 200 if (drmCommandWriteRead(bo->rws->fd, 201 DRM_RADEON_GEM_MMAP, 202 &args, 203 sizeof(args))) { 204 pipe_mutex_unlock(bo->map_mutex); 205 fprintf(stderr, "radeon: gem_mmap failed: %p 0x%08X\n", 206 bo, bo->handle); 207 return NULL; 208 } 209 210 ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, 211 bo->rws->fd, args.addr_ptr); 212 if (ptr == MAP_FAILED) { 213 pipe_mutex_unlock(bo->map_mutex); 214 fprintf(stderr, "radeon: mmap failed, errno: %i\n", errno); 215 return NULL; 216 } 217 bo->ptr = ptr; 218 pipe_mutex_unlock(bo->map_mutex); 219 220 return bo->ptr; 221} 222 223static void radeon_bo_unmap_internal(struct pb_buffer *_buf) 224{ 225 /* NOP */ 226} 227 228static void radeon_bo_get_base_buffer(struct pb_buffer *buf, 229 struct pb_buffer **base_buf, 230 unsigned *offset) 231{ 232 *base_buf = buf; 233 *offset = 0; 234} 235 236static enum pipe_error radeon_bo_validate(struct pb_buffer *_buf, 237 struct pb_validate *vl, 238 unsigned flags) 239{ 240 /* Always pinned */ 241 return PIPE_OK; 242} 243 244static void radeon_bo_fence(struct pb_buffer *buf, 245 struct pipe_fence_handle *fence) 246{ 247} 248 249const struct pb_vtbl radeon_bo_vtbl = { 250 radeon_bo_destroy, 251 radeon_bo_map_internal, 252 radeon_bo_unmap_internal, 253 radeon_bo_validate, 254 radeon_bo_fence, 255 radeon_bo_get_base_buffer, 256}; 257 258static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr, 259 pb_size size, 260 const struct pb_desc *desc) 261{ 262 struct radeon_bomgr *mgr = radeon_bomgr(_mgr); 263 struct radeon_drm_winsys *rws = mgr->rws; 264 struct radeon_bo *bo; 265 struct drm_radeon_gem_create args = {}; 266 267 args.size = size; 268 args.alignment = desc->alignment; 269 args.initial_domain = 270 (desc->usage & RADEON_PB_USAGE_DOMAIN_GTT ? 271 RADEON_GEM_DOMAIN_GTT : 0) | 272 (desc->usage & RADEON_PB_USAGE_DOMAIN_VRAM ? 273 RADEON_GEM_DOMAIN_VRAM : 0); 274 275 if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE, 276 &args, sizeof(args))) { 277 fprintf(stderr, "Failed to allocate :\n"); 278 fprintf(stderr, " size : %d bytes\n", size); 279 fprintf(stderr, " alignment : %d bytes\n", desc->alignment); 280 fprintf(stderr, " domains : %d\n", args.initial_domain); 281 return NULL; 282 } 283 284 bo = CALLOC_STRUCT(radeon_bo); 285 if (!bo) 286 return NULL; 287 288 pipe_reference_init(&bo->base.base.reference, 1); 289 bo->base.base.alignment = desc->alignment; 290 bo->base.base.usage = desc->usage; 291 bo->base.base.size = size; 292 bo->base.vtbl = &radeon_bo_vtbl; 293 bo->mgr = mgr; 294 bo->rws = mgr->rws; 295 bo->handle = args.handle; 296 bo->size = size; 297 pipe_mutex_init(bo->map_mutex); 298 299 radeon_bo_ref(bo); 300 return &bo->base; 301} 302 303static void radeon_bomgr_flush(struct pb_manager *mgr) 304{ 305 /* NOP */ 306} 307 308/* This is for the cache bufmgr. */ 309static boolean radeon_bomgr_is_buffer_busy(struct pb_manager *_mgr, 310 struct pb_buffer *_buf) 311{ 312 struct radeon_bo *bo = radeon_bo(_buf); 313 314 if (radeon_bo_is_referenced_by_any_cs(bo)) { 315 return TRUE; 316 } 317 318 if (radeon_bo_is_busy((struct r300_winsys_bo*)bo)) { 319 return TRUE; 320 } 321 322 return FALSE; 323} 324 325static void radeon_bomgr_destroy(struct pb_manager *_mgr) 326{ 327 struct radeon_bomgr *mgr = radeon_bomgr(_mgr); 328 util_hash_table_destroy(mgr->bo_handles); 329 pipe_mutex_destroy(mgr->bo_handles_mutex); 330 FREE(mgr); 331} 332 333#define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x))) 334 335static unsigned handle_hash(void *key) 336{ 337 return PTR_TO_UINT(key); 338} 339 340static int handle_compare(void *key1, void *key2) 341{ 342 return PTR_TO_UINT(key1) != PTR_TO_UINT(key2); 343} 344 345struct pb_manager *radeon_bomgr_create(struct radeon_drm_winsys *rws) 346{ 347 struct radeon_bomgr *mgr; 348 349 mgr = CALLOC_STRUCT(radeon_bomgr); 350 if (!mgr) 351 return NULL; 352 353 mgr->base.destroy = radeon_bomgr_destroy; 354 mgr->base.create_buffer = radeon_bomgr_create_bo; 355 mgr->base.flush = radeon_bomgr_flush; 356 mgr->base.is_buffer_busy = radeon_bomgr_is_buffer_busy; 357 358 mgr->rws = rws; 359 mgr->bo_handles = util_hash_table_create(handle_hash, handle_compare); 360 pipe_mutex_init(mgr->bo_handles_mutex); 361 return &mgr->base; 362} 363 364static void *radeon_bo_map(struct r300_winsys_bo *buf, 365 struct r300_winsys_cs *cs, 366 enum pipe_transfer_usage usage) 367{ 368 struct pb_buffer *_buf = pb_buffer(buf); 369 370 return pb_map(_buf, get_pb_usage_from_transfer_flags(usage), cs); 371} 372 373static void radeon_bo_get_tiling(struct r300_winsys_bo *_buf, 374 enum r300_buffer_tiling *microtiled, 375 enum r300_buffer_tiling *macrotiled) 376{ 377 struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf)); 378 struct drm_radeon_gem_set_tiling args = {}; 379 380 args.handle = bo->handle; 381 382 drmCommandWriteRead(bo->rws->fd, 383 DRM_RADEON_GEM_GET_TILING, 384 &args, 385 sizeof(args)); 386 387 *microtiled = R300_BUFFER_LINEAR; 388 *macrotiled = R300_BUFFER_LINEAR; 389 if (args.tiling_flags & RADEON_BO_FLAGS_MICRO_TILE) 390 *microtiled = R300_BUFFER_TILED; 391 392 if (args.tiling_flags & RADEON_BO_FLAGS_MACRO_TILE) 393 *macrotiled = R300_BUFFER_TILED; 394} 395 396static void radeon_bo_set_tiling(struct r300_winsys_bo *_buf, 397 struct r300_winsys_cs *rcs, 398 enum r300_buffer_tiling microtiled, 399 enum r300_buffer_tiling macrotiled, 400 uint32_t pitch) 401{ 402 struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf)); 403 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); 404 struct drm_radeon_gem_set_tiling args = {}; 405 406 /* Tiling determines how DRM treats the buffer data. 407 * We must flush CS when changing it if the buffer is referenced. */ 408 if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) { 409 radeon_drm_cs_flush(rcs); 410 radeon_drm_cs_sync_flush(rcs); 411 } 412 413 while (p_atomic_read(&bo->num_active_ioctls)) { 414 sched_yield(); 415 } 416 417 if (microtiled == R300_BUFFER_TILED) 418 args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE; 419 else if (microtiled == R300_BUFFER_SQUARETILED) 420 args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE_SQUARE; 421 422 if (macrotiled == R300_BUFFER_TILED) 423 args.tiling_flags |= RADEON_BO_FLAGS_MACRO_TILE; 424 425 args.handle = bo->handle; 426 args.pitch = pitch; 427 428 drmCommandWriteRead(bo->rws->fd, 429 DRM_RADEON_GEM_SET_TILING, 430 &args, 431 sizeof(args)); 432} 433 434static struct r300_winsys_cs_handle *radeon_drm_get_cs_handle( 435 struct r300_winsys_bo *_buf) 436{ 437 /* return radeon_bo. */ 438 return (struct r300_winsys_cs_handle*) 439 get_radeon_bo(pb_buffer(_buf)); 440} 441 442static unsigned get_pb_usage_from_create_flags(unsigned bind, unsigned usage, 443 enum r300_buffer_domain domain) 444{ 445 unsigned res = 0; 446 447 if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) 448 res |= RADEON_PB_USAGE_CACHE; 449 450 if (domain & R300_DOMAIN_GTT) 451 res |= RADEON_PB_USAGE_DOMAIN_GTT; 452 453 if (domain & R300_DOMAIN_VRAM) 454 res |= RADEON_PB_USAGE_DOMAIN_VRAM; 455 456 return res; 457} 458 459static struct r300_winsys_bo * 460radeon_winsys_bo_create(struct r300_winsys_screen *rws, 461 unsigned size, 462 unsigned alignment, 463 unsigned bind, 464 unsigned usage, 465 enum r300_buffer_domain domain) 466{ 467 struct radeon_drm_winsys *ws = radeon_drm_winsys(rws); 468 struct pb_desc desc; 469 struct pb_manager *provider; 470 struct pb_buffer *buffer; 471 472 memset(&desc, 0, sizeof(desc)); 473 desc.alignment = alignment; 474 desc.usage = get_pb_usage_from_create_flags(bind, usage, domain); 475 476 /* Assign a buffer manager. */ 477 if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) 478 provider = ws->cman; 479 else 480 provider = ws->kman; 481 482 buffer = provider->create_buffer(provider, size, &desc); 483 if (!buffer) 484 return NULL; 485 486 return (struct r300_winsys_bo*)buffer; 487} 488 489static struct r300_winsys_bo *radeon_winsys_bo_from_handle(struct r300_winsys_screen *rws, 490 struct winsys_handle *whandle, 491 unsigned *stride, 492 unsigned *size) 493{ 494 struct radeon_drm_winsys *ws = radeon_drm_winsys(rws); 495 struct radeon_bo *bo; 496 struct radeon_bomgr *mgr = radeon_bomgr(ws->kman); 497 struct drm_gem_open open_arg = {}; 498 499 /* We must maintain a list of pairs <handle, bo>, so that we always return 500 * the same BO for one particular handle. If we didn't do that and created 501 * more than one BO for the same handle and then relocated them in a CS, 502 * we would hit a deadlock in the kernel. 503 * 504 * The list of pairs is guarded by a mutex, of course. */ 505 pipe_mutex_lock(mgr->bo_handles_mutex); 506 507 /* First check if there already is an existing bo for the handle. */ 508 bo = util_hash_table_get(mgr->bo_handles, (void*)(uintptr_t)whandle->handle); 509 if (bo) { 510 /* Increase the refcount. */ 511 struct pb_buffer *b = NULL; 512 pb_reference(&b, &bo->base); 513 goto done; 514 } 515 516 /* There isn't, create a new one. */ 517 bo = CALLOC_STRUCT(radeon_bo); 518 if (!bo) { 519 goto fail; 520 } 521 522 /* Open the BO. */ 523 open_arg.name = whandle->handle; 524 if (drmIoctl(ws->fd, DRM_IOCTL_GEM_OPEN, &open_arg)) { 525 FREE(bo); 526 goto fail; 527 } 528 bo->handle = open_arg.handle; 529 bo->size = open_arg.size; 530 bo->name = whandle->handle; 531 radeon_bo_ref(bo); 532 533 /* Initialize it. */ 534 pipe_reference_init(&bo->base.base.reference, 1); 535 bo->base.base.alignment = 0; 536 bo->base.base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ; 537 bo->base.base.size = bo->size; 538 bo->base.vtbl = &radeon_bo_vtbl; 539 bo->mgr = mgr; 540 bo->rws = mgr->rws; 541 pipe_mutex_init(bo->map_mutex); 542 543 util_hash_table_set(mgr->bo_handles, (void*)(uintptr_t)whandle->handle, bo); 544 545done: 546 pipe_mutex_unlock(mgr->bo_handles_mutex); 547 548 if (stride) 549 *stride = whandle->stride; 550 if (size) 551 *size = bo->base.base.size; 552 553 return (struct r300_winsys_bo*)bo; 554 555fail: 556 pipe_mutex_unlock(mgr->bo_handles_mutex); 557 return NULL; 558} 559 560static boolean radeon_winsys_bo_get_handle(struct r300_winsys_bo *buffer, 561 unsigned stride, 562 struct winsys_handle *whandle) 563{ 564 struct drm_gem_flink flink = {}; 565 struct radeon_bo *bo = get_radeon_bo(pb_buffer(buffer)); 566 567 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) { 568 if (!bo->flinked) { 569 flink.handle = bo->handle; 570 571 if (ioctl(bo->rws->fd, DRM_IOCTL_GEM_FLINK, &flink)) { 572 return FALSE; 573 } 574 575 bo->flinked = TRUE; 576 bo->flink = flink.name; 577 } 578 whandle->handle = bo->flink; 579 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) { 580 whandle->handle = bo->handle; 581 } 582 583 whandle->stride = stride; 584 return TRUE; 585} 586 587void radeon_bomgr_init_functions(struct radeon_drm_winsys *ws) 588{ 589 ws->base.buffer_get_cs_handle = radeon_drm_get_cs_handle; 590 ws->base.buffer_set_tiling = radeon_bo_set_tiling; 591 ws->base.buffer_get_tiling = radeon_bo_get_tiling; 592 ws->base.buffer_map = radeon_bo_map; 593 ws->base.buffer_unmap = pb_unmap; 594 ws->base.buffer_wait = radeon_bo_wait; 595 ws->base.buffer_is_busy = radeon_bo_is_busy; 596 ws->base.buffer_create = radeon_winsys_bo_create; 597 ws->base.buffer_from_handle = radeon_winsys_bo_from_handle; 598 ws->base.buffer_get_handle = radeon_winsys_bo_get_handle; 599} 600