radeon_drm_winsys.c revision 622b65d33bcc46a6b2cede6081b32a26a4ec7c7f 
1/*
2 * Copyright © 2009 Corbin Simpson
3 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27/*
28 * Authors:
29 *      Corbin Simpson <MostAwesomeDude@gmail.com>
30 *      Joakim Sindholt <opensource@zhasha.com>
31 *      Marek Olšák <maraeo@gmail.com>
32 */
33
34#include "radeon_drm_bo.h"
35#include "radeon_drm_cs.h"
36#include "radeon_drm_public.h"
37
38#include "pipebuffer/pb_bufmgr.h"
39#include "util/u_memory.h"
40
41#include <xf86drm.h>
42#include <stdio.h>
43
44/*
45 * this are copy from radeon_drm, once an updated libdrm is released
46 * we should bump configure.ac requirement for it and remove the following
47 * field
48 */
49#ifndef RADEON_INFO_TILING_CONFIG
50#define RADEON_INFO_TILING_CONFIG 6
51#endif
52
53#ifndef RADEON_INFO_WANT_HYPERZ
54#define RADEON_INFO_WANT_HYPERZ 7
55#endif
56
57#ifndef RADEON_INFO_WANT_CMASK
58#define RADEON_INFO_WANT_CMASK 8
59#endif
60
61#ifndef RADEON_INFO_CLOCK_CRYSTAL_FREQ
62#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 9
63#endif
64
65#ifndef RADEON_INFO_NUM_BACKENDS
66#define RADEON_INFO_NUM_BACKENDS 0xa
67#endif
68
69#ifndef RADEON_INFO_NUM_TILE_PIPES
70#define RADEON_INFO_NUM_TILE_PIPES 0xb
71#endif
72
73#ifndef RADEON_INFO_BACKEND_MAP
74#define RADEON_INFO_BACKEND_MAP 0xd
75#endif
76
77#ifndef RADEON_INFO_VA_START
78/* virtual address start, va < start are reserved by the kernel */
79#define RADEON_INFO_VA_START        0x0e
80/* maximum size of ib using the virtual memory cs */
81#define RADEON_INFO_IB_VM_MAX_SIZE  0x0f
82#endif
83
84
85/* Enable/disable feature access for one command stream.
86 * If enable == TRUE, return TRUE on success.
87 * Otherwise, return FALSE.
88 *
89 * We basically do the same thing kernel does, because we have to deal
90 * with multiple contexts (here command streams) backed by one winsys. */
91static boolean radeon_set_fd_access(struct radeon_drm_cs *applier,
92                                    struct radeon_drm_cs **owner,
93                                    pipe_mutex *mutex,
94                                    unsigned request, boolean enable)
95{
96    struct drm_radeon_info info;
97    unsigned value = enable ? 1 : 0;
98
99    memset(&info, 0, sizeof(info));
100
101    pipe_mutex_lock(*mutex);
102
103    /* Early exit if we are sure the request will fail. */
104    if (enable) {
105        if (*owner) {
106            pipe_mutex_unlock(*mutex);
107            return FALSE;
108        }
109    } else {
110        if (*owner != applier) {
111            pipe_mutex_unlock(*mutex);
112            return FALSE;
113        }
114    }
115
116    /* Pass through the request to the kernel. */
117    info.value = (unsigned long)&value;
118    info.request = request;
119    if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
120                            &info, sizeof(info)) != 0) {
121        pipe_mutex_unlock(*mutex);
122        return FALSE;
123    }
124
125    /* Update the rights in the winsys. */
126    if (enable) {
127        if (value) {
128            *owner = applier;
129            fprintf(stderr, "radeon: Acquired Hyper-Z.\n");
130            pipe_mutex_unlock(*mutex);
131            return TRUE;
132        }
133    } else {
134        *owner = NULL;
135        fprintf(stderr, "radeon: Released Hyper-Z.\n");
136    }
137
138    pipe_mutex_unlock(*mutex);
139    return FALSE;
140}
141
142static boolean radeon_get_drm_value(int fd, unsigned request,
143                                    const char *errname, uint32_t *out)
144{
145    struct drm_radeon_info info;
146    int retval;
147
148    memset(&info, 0, sizeof(info));
149
150    info.value = (unsigned long)out;
151    info.request = request;
152
153    retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
154    if (retval) {
155        if (errname) {
156            fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
157                    errname, retval);
158        }
159        return FALSE;
160    }
161    return TRUE;
162}
163
164/* Helper function to do the ioctls needed for setup and init. */
165static boolean do_winsys_init(struct radeon_drm_winsys *ws)
166{
167    struct drm_radeon_gem_info gem_info;
168    int retval;
169    drmVersionPtr version;
170
171    memset(&gem_info, 0, sizeof(gem_info));
172
173    /* We do things in a specific order here.
174     *
175     * DRM version first. We need to be sure we're running on a KMS chipset.
176     * This is also for some features.
177     *
178     * Then, the PCI ID. This is essential and should return usable numbers
179     * for all Radeons. If this fails, we probably got handed an FD for some
180     * non-Radeon card.
181     *
182     * The GEM info is actually bogus on the kernel side, as well as our side
183     * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
184     * we don't actually use the info for anything yet.
185     *
186     * The GB and Z pipe requests should always succeed, but they might not
187     * return sensical values for all chipsets, but that's alright because
188     * the pipe drivers already know that.
189     */
190
191    /* Get DRM version. */
192    version = drmGetVersion(ws->fd);
193    if (version->version_major != 2 ||
194        version->version_minor < 3) {
195        fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
196                "only compatible with 2.3.x (kernel 2.6.34) or later.\n",
197                __FUNCTION__,
198                version->version_major,
199                version->version_minor,
200                version->version_patchlevel);
201        drmFreeVersion(version);
202        return FALSE;
203    }
204
205    ws->info.drm_major = version->version_major;
206    ws->info.drm_minor = version->version_minor;
207    ws->info.drm_patchlevel = version->version_patchlevel;
208    drmFreeVersion(version);
209
210    /* Get PCI ID. */
211    if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
212                              &ws->info.pci_id))
213        return FALSE;
214
215    /* Check PCI ID. */
216    switch (ws->info.pci_id) {
217#define CHIPSET(pci_id, name, family) case pci_id:
218#include "pci_ids/r300_pci_ids.h"
219#undef CHIPSET
220        ws->gen = R300;
221        break;
222
223#define CHIPSET(pci_id, name, family) case pci_id:
224#include "pci_ids/r600_pci_ids.h"
225#undef CHIPSET
226        ws->gen = R600;
227        break;
228
229    default:
230        fprintf(stderr, "radeon: Invalid PCI ID.\n");
231        return FALSE;
232    }
233
234    /* Get GEM info. */
235    retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
236            &gem_info, sizeof(gem_info));
237    if (retval) {
238        fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
239                retval);
240        return FALSE;
241    }
242    ws->info.gart_size = gem_info.gart_size;
243    ws->info.vram_size = gem_info.vram_size;
244
245    ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
246
247    /* Generation-specific queries. */
248    if (ws->gen == R300) {
249        if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
250                                  "GB pipe count",
251                                  &ws->info.r300_num_gb_pipes))
252            return FALSE;
253
254        if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
255                                  "Z pipe count",
256                                  &ws->info.r300_num_z_pipes))
257            return FALSE;
258    }
259    else if (ws->gen == R600) {
260        if (ws->info.drm_minor >= 9 &&
261            !radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
262                                  "num backends",
263                                  &ws->info.r600_num_backends))
264            return FALSE;
265
266        /* get the GPU counter frequency, failure is not fatal */
267        radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
268                             &ws->info.r600_clock_crystal_freq);
269
270        radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
271                             &ws->info.r600_tiling_config);
272
273        if (ws->info.drm_minor >= 11) {
274            radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
275                                 &ws->info.r600_num_tile_pipes);
276
277            if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
278                                      &ws->info.r600_backend_map))
279                ws->info.r600_backend_map_valid = TRUE;
280        }
281
282        ws->info.r600_virtual_address = FALSE;
283        if (ws->info.drm_minor >= 13) {
284            ws->info.r600_virtual_address = TRUE;
285            if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
286                                      &ws->info.r600_va_start))
287                ws->info.r600_virtual_address = FALSE;
288            if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
289                                      &ws->info.r600_ib_vm_max_size))
290                ws->info.r600_virtual_address = FALSE;
291        }
292
293	/* XXX don't enable this for R700 yet, it's broken on those asics */
294	ws->info.r600_has_streamout = debug_get_bool_option("R600_STREAMOUT", FALSE);
295    }
296
297    return TRUE;
298}
299
300static void radeon_winsys_destroy(struct radeon_winsys *rws)
301{
302    struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
303
304    pipe_mutex_destroy(ws->hyperz_owner_mutex);
305    pipe_mutex_destroy(ws->cmask_owner_mutex);
306
307    ws->cman->destroy(ws->cman);
308    ws->kman->destroy(ws->kman);
309    if (ws->gen == R600) {
310        radeon_surface_manager_free(ws->surf_man);
311    }
312    FREE(rws);
313}
314
315static void radeon_query_info(struct radeon_winsys *rws,
316                              struct radeon_info *info)
317{
318    *info = ((struct radeon_drm_winsys *)rws)->info;
319}
320
321static boolean radeon_cs_request_feature(struct radeon_winsys_cs *rcs,
322                                         enum radeon_feature_id fid,
323                                         boolean enable)
324{
325    struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
326
327    switch (fid) {
328    case RADEON_FID_R300_HYPERZ_ACCESS:
329        if (debug_get_bool_option("RADEON_HYPERZ", FALSE)) {
330            return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
331                                        &cs->ws->hyperz_owner_mutex,
332                                        RADEON_INFO_WANT_HYPERZ, enable);
333        } else {
334            return FALSE;
335        }
336
337    case RADEON_FID_R300_CMASK_ACCESS:
338        if (debug_get_bool_option("RADEON_CMASK", FALSE)) {
339            return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
340                                        &cs->ws->cmask_owner_mutex,
341                                        RADEON_INFO_WANT_CMASK, enable);
342        } else {
343            return FALSE;
344        }
345    }
346    return FALSE;
347}
348
349static int radeon_drm_winsys_surface_init(struct radeon_winsys *rws,
350                                          struct radeon_surface *surf)
351{
352    struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
353
354    return radeon_surface_init(ws->surf_man, surf);
355}
356
357static int radeon_drm_winsys_surface_best(struct radeon_winsys *rws,
358                                          struct radeon_surface *surf)
359{
360    struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
361
362    return radeon_surface_best(ws->surf_man, surf);
363}
364
365struct radeon_winsys *radeon_drm_winsys_create(int fd)
366{
367    struct radeon_drm_winsys *ws = CALLOC_STRUCT(radeon_drm_winsys);
368    if (!ws) {
369        return NULL;
370    }
371
372    ws->fd = fd;
373
374    if (!do_winsys_init(ws))
375        goto fail;
376
377    /* Create managers. */
378    ws->kman = radeon_bomgr_create(ws);
379    if (!ws->kman)
380        goto fail;
381    ws->cman = pb_cache_manager_create(ws->kman, 1000000);
382    if (!ws->cman)
383        goto fail;
384
385    /* FIXME check for libdrm version ?? */
386    if (ws->gen == R600) {
387        ws->surf_man = radeon_surface_manager_new(fd);
388        if (!ws->surf_man)
389            goto fail;
390    }
391
392    /* Set functions. */
393    ws->base.destroy = radeon_winsys_destroy;
394    ws->base.query_info = radeon_query_info;
395    ws->base.cs_request_feature = radeon_cs_request_feature;
396    ws->base.surface_init = radeon_drm_winsys_surface_init;
397    ws->base.surface_best = radeon_drm_winsys_surface_best;
398
399    radeon_bomgr_init_functions(ws);
400    radeon_drm_cs_init_functions(ws);
401
402    pipe_mutex_init(ws->hyperz_owner_mutex);
403    pipe_mutex_init(ws->cmask_owner_mutex);
404
405    return &ws->base;
406
407fail:
408    if (ws->cman)
409        ws->cman->destroy(ws->cman);
410    if (ws->kman)
411        ws->kman->destroy(ws->kman);
412    if (ws->surf_man)
413        radeon_surface_manager_free(ws->surf_man);
414    FREE(ws);
415    return NULL;
416}
417