brw_blorp_blit.cpp revision 082874e3891e588f674508be6578f600b35852c4
1/* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#include "main/teximage.h" 25 26#include "glsl/ralloc.h" 27 28#include "intel_fbo.h" 29 30#include "brw_blorp.h" 31#include "brw_context.h" 32#include "brw_eu.h" 33#include "brw_state.h" 34 35 36/** 37 * Helper function for handling mirror image blits. 38 * 39 * If coord0 > coord1, swap them and invert the "mirror" boolean. 40 */ 41static inline void 42fixup_mirroring(bool &mirror, GLint &coord0, GLint &coord1) 43{ 44 if (coord0 > coord1) { 45 mirror = !mirror; 46 GLint tmp = coord0; 47 coord0 = coord1; 48 coord1 = tmp; 49 } 50} 51 52 53/** 54 * Adjust {src,dst}_x{0,1} to account for clipping and scissoring of 55 * destination coordinates. 56 * 57 * Return true if there is still blitting to do, false if all pixels got 58 * rejected by the clip and/or scissor. 59 * 60 * For clarity, the nomenclature of this function assumes we are clipping and 61 * scissoring the X coordinate; the exact same logic applies for Y 62 * coordinates. 63 * 64 * Note: this function may also be used to account for clipping of source 65 * coordinates, by swapping the roles of src and dst. 66 */ 67static inline bool 68clip_or_scissor(bool mirror, GLint &src_x0, GLint &src_x1, GLint &dst_x0, 69 GLint &dst_x1, GLint fb_xmin, GLint fb_xmax) 70{ 71 /* If we are going to scissor everything away, stop. */ 72 if (!(fb_xmin < fb_xmax && 73 dst_x0 < fb_xmax && 74 fb_xmin < dst_x1 && 75 dst_x0 < dst_x1)) { 76 return false; 77 } 78 79 /* Clip the destination rectangle, and keep track of how many pixels we 80 * clipped off of the left and right sides of it. 81 */ 82 GLint pixels_clipped_left = 0; 83 GLint pixels_clipped_right = 0; 84 if (dst_x0 < fb_xmin) { 85 pixels_clipped_left = fb_xmin - dst_x0; 86 dst_x0 = fb_xmin; 87 } 88 if (fb_xmax < dst_x1) { 89 pixels_clipped_right = dst_x1 - fb_xmax; 90 dst_x1 = fb_xmax; 91 } 92 93 /* If we are mirrored, then before applying pixels_clipped_{left,right} to 94 * the source coordinates, we need to flip them to account for the 95 * mirroring. 96 */ 97 if (mirror) { 98 GLint tmp = pixels_clipped_left; 99 pixels_clipped_left = pixels_clipped_right; 100 pixels_clipped_right = tmp; 101 } 102 103 /* Adjust the source rectangle to remove the pixels corresponding to those 104 * that were clipped/scissored out of the destination rectangle. 105 */ 106 src_x0 += pixels_clipped_left; 107 src_x1 -= pixels_clipped_right; 108 109 return true; 110} 111 112 113static struct intel_mipmap_tree * 114find_miptree(GLbitfield buffer_bit, struct gl_renderbuffer *rb) 115{ 116 struct intel_renderbuffer *irb = intel_renderbuffer(rb); 117 struct intel_mipmap_tree *mt = irb->mt; 118 if (buffer_bit == GL_STENCIL_BUFFER_BIT && mt->stencil_mt) 119 mt = mt->stencil_mt; 120 return mt; 121} 122 123 124static void 125do_blorp_blit(struct intel_context *intel, GLbitfield buffer_bit, 126 struct gl_renderbuffer *src_rb, struct gl_renderbuffer *dst_rb, 127 GLint srcX0, GLint srcY0, 128 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1, 129 bool mirror_x, bool mirror_y) 130{ 131 struct gl_context *ctx = &intel->ctx; 132 133 /* Find source/dst miptrees */ 134 struct intel_mipmap_tree *src_mt = find_miptree(buffer_bit, src_rb); 135 struct intel_mipmap_tree *dst_mt = find_miptree(buffer_bit, dst_rb); 136 137 /* Get ready to blit. This includes depth resolving the src and dst 138 * buffers if necessary. 139 */ 140 intel_renderbuffer_resolve_depth(intel, intel_renderbuffer(src_rb)); 141 intel_renderbuffer_resolve_depth(intel, intel_renderbuffer(dst_rb)); 142 143 /* Do the blit */ 144 brw_blorp_blit_params params(brw_context(ctx), src_mt, dst_mt, 145 srcX0, srcY0, dstX0, dstY0, dstX1, dstY1, 146 mirror_x, mirror_y); 147 brw_blorp_exec(intel, ¶ms); 148 149 /* Mark the dst buffer as needing a HiZ resolve if necessary. */ 150 intel_renderbuffer_set_needs_hiz_resolve(intel_renderbuffer(dst_rb)); 151} 152 153 154static bool 155formats_match(GLbitfield buffer_bit, struct gl_renderbuffer *src_rb, 156 struct gl_renderbuffer *dst_rb) 157{ 158 /* Note: don't just check gl_renderbuffer::Format, because in some cases 159 * multiple gl_formats resolve to the same native type in the miptree (for 160 * example MESA_FORMAT_X8_Z24 and MESA_FORMAT_S8_Z24), and we can blit 161 * between those formats. 162 */ 163 return find_miptree(buffer_bit, src_rb)->format == 164 find_miptree(buffer_bit, dst_rb)->format; 165} 166 167 168static bool 169try_blorp_blit(struct intel_context *intel, 170 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1, 171 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1, 172 GLenum filter, GLbitfield buffer_bit) 173{ 174 struct gl_context *ctx = &intel->ctx; 175 176 /* Sync up the state of window system buffers. We need to do this before 177 * we go looking for the buffers. 178 */ 179 intel_prepare_render(intel); 180 181 const struct gl_framebuffer *read_fb = ctx->ReadBuffer; 182 const struct gl_framebuffer *draw_fb = ctx->DrawBuffer; 183 184 /* Detect if the blit needs to be mirrored */ 185 bool mirror_x = false, mirror_y = false; 186 fixup_mirroring(mirror_x, srcX0, srcX1); 187 fixup_mirroring(mirror_x, dstX0, dstX1); 188 fixup_mirroring(mirror_y, srcY0, srcY1); 189 fixup_mirroring(mirror_y, dstY0, dstY1); 190 191 /* Make sure width and height match */ 192 if (srcX1 - srcX0 != dstX1 - dstX0) return false; 193 if (srcY1 - srcY0 != dstY1 - dstY0) return false; 194 195 /* If the destination rectangle needs to be clipped or scissored, do so. 196 */ 197 if (!(clip_or_scissor(mirror_x, srcX0, srcX1, dstX0, dstX1, 198 draw_fb->_Xmin, draw_fb->_Xmax) && 199 clip_or_scissor(mirror_y, srcY0, srcY1, dstY0, dstY1, 200 draw_fb->_Ymin, draw_fb->_Ymax))) { 201 /* Everything got clipped/scissored away, so the blit was successful. */ 202 return true; 203 } 204 205 /* If the source rectangle needs to be clipped or scissored, do so. */ 206 if (!(clip_or_scissor(mirror_x, dstX0, dstX1, srcX0, srcX1, 207 0, read_fb->Width) && 208 clip_or_scissor(mirror_y, dstY0, dstY1, srcY0, srcY1, 209 0, read_fb->Height))) { 210 /* Everything got clipped/scissored away, so the blit was successful. */ 211 return true; 212 } 213 214 /* Account for the fact that in the system framebuffer, the origin is at 215 * the lower left. 216 */ 217 if (read_fb->Name == 0) { 218 GLint tmp = read_fb->Height - srcY0; 219 srcY0 = read_fb->Height - srcY1; 220 srcY1 = tmp; 221 mirror_y = !mirror_y; 222 } 223 if (draw_fb->Name == 0) { 224 GLint tmp = draw_fb->Height - dstY0; 225 dstY0 = draw_fb->Height - dstY1; 226 dstY1 = tmp; 227 mirror_y = !mirror_y; 228 } 229 230 /* Find buffers */ 231 struct gl_renderbuffer *src_rb; 232 struct gl_renderbuffer *dst_rb; 233 switch (buffer_bit) { 234 case GL_COLOR_BUFFER_BIT: 235 src_rb = read_fb->_ColorReadBuffer; 236 for (unsigned i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; ++i) { 237 dst_rb = ctx->DrawBuffer->_ColorDrawBuffers[i]; 238 if (dst_rb && !formats_match(buffer_bit, src_rb, dst_rb)) 239 return false; 240 } 241 for (unsigned i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; ++i) { 242 dst_rb = ctx->DrawBuffer->_ColorDrawBuffers[i]; 243 do_blorp_blit(intel, buffer_bit, src_rb, dst_rb, srcX0, srcY0, 244 dstX0, dstY0, dstX1, dstY1, mirror_x, mirror_y); 245 } 246 break; 247 case GL_DEPTH_BUFFER_BIT: 248 src_rb = read_fb->Attachment[BUFFER_DEPTH].Renderbuffer; 249 dst_rb = draw_fb->Attachment[BUFFER_DEPTH].Renderbuffer; 250 if (!formats_match(buffer_bit, src_rb, dst_rb)) 251 return false; 252 do_blorp_blit(intel, buffer_bit, src_rb, dst_rb, srcX0, srcY0, 253 dstX0, dstY0, dstX1, dstY1, mirror_x, mirror_y); 254 break; 255 case GL_STENCIL_BUFFER_BIT: 256 src_rb = read_fb->Attachment[BUFFER_STENCIL].Renderbuffer; 257 dst_rb = draw_fb->Attachment[BUFFER_STENCIL].Renderbuffer; 258 if (!formats_match(buffer_bit, src_rb, dst_rb)) 259 return false; 260 do_blorp_blit(intel, buffer_bit, src_rb, dst_rb, srcX0, srcY0, 261 dstX0, dstY0, dstX1, dstY1, mirror_x, mirror_y); 262 break; 263 default: 264 assert(false); 265 } 266 267 return true; 268} 269 270GLbitfield 271brw_blorp_framebuffer(struct intel_context *intel, 272 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1, 273 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1, 274 GLbitfield mask, GLenum filter) 275{ 276 /* BLORP is not supported before Gen6. */ 277 if (intel->gen < 6) 278 return mask; 279 280 static GLbitfield buffer_bits[] = { 281 GL_COLOR_BUFFER_BIT, 282 GL_DEPTH_BUFFER_BIT, 283 GL_STENCIL_BUFFER_BIT, 284 }; 285 286 for (unsigned int i = 0; i < ARRAY_SIZE(buffer_bits); ++i) { 287 if ((mask & buffer_bits[i]) && 288 try_blorp_blit(intel, 289 srcX0, srcY0, srcX1, srcY1, 290 dstX0, dstY0, dstX1, dstY1, 291 filter, buffer_bits[i])) { 292 mask &= ~buffer_bits[i]; 293 } 294 } 295 296 return mask; 297} 298 299 300/** 301 * Enum to specify the order of arguments in a sampler message 302 */ 303enum sampler_message_arg 304{ 305 SAMPLER_MESSAGE_ARG_U_FLOAT, 306 SAMPLER_MESSAGE_ARG_V_FLOAT, 307 SAMPLER_MESSAGE_ARG_U_INT, 308 SAMPLER_MESSAGE_ARG_V_INT, 309 SAMPLER_MESSAGE_ARG_SI_INT, 310 SAMPLER_MESSAGE_ARG_MCS_INT, 311 SAMPLER_MESSAGE_ARG_ZERO_INT, 312}; 313 314/** 315 * Generator for WM programs used in BLORP blits. 316 * 317 * The bulk of the work done by the WM program is to wrap and unwrap the 318 * coordinate transformations used by the hardware to store surfaces in 319 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the 320 * sample index for a multisampled surface) to a memory offset by the 321 * following formulas: 322 * 323 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S)) 324 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset)) 325 * 326 * For a single-sampled surface, or for a multisampled surface using 327 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity 328 * function: 329 * 330 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0) 331 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0) 332 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S) 333 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S) 334 * 335 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa() 336 * embeds the sample number into bit 1 of the X and Y coordinates: 337 * 338 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0) 339 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1) 340 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1) 341 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S) 342 * where X' = (X & ~0b11) >> 1 | (X & 0b1) 343 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1) 344 * S = (Y & 0b10) | (X & 0b10) >> 1 345 * 346 * For X tiling, tile() combines together the low-order bits of the X and Y 347 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512 348 * bytes wide and 8 rows high: 349 * 350 * tile(x_tiled, X, Y, S) = A 351 * where A = tile_num << 12 | offset 352 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9) 353 * offset = (Y' & 0b111) << 9 354 * | (X & 0b111111111) 355 * X' = X * cpp 356 * Y' = Y + S * qpitch 357 * detile(x_tiled, A) = (X, Y, S) 358 * where X = X' / cpp 359 * Y = Y' % qpitch 360 * S = Y' / qpitch 361 * Y' = (tile_num / tile_pitch) << 3 362 * | (A & 0b111000000000) >> 9 363 * X' = (tile_num % tile_pitch) << 9 364 * | (A & 0b111111111) 365 * 366 * (In all tiling formulas, cpp is the number of bytes occupied by a single 367 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required 368 * to fill the width of the surface, and qpitch is the spacing (in rows) 369 * between array slices). 370 * 371 * For Y tiling, tile() combines together the low-order bits of the X and Y 372 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128 373 * bytes wide and 32 rows high: 374 * 375 * tile(y_tiled, X, Y, S) = A 376 * where A = tile_num << 12 | offset 377 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7) 378 * offset = (X' & 0b1110000) << 5 379 * | (Y' & 0b11111) << 4 380 * | (X' & 0b1111) 381 * X' = X * cpp 382 * Y' = Y + S * qpitch 383 * detile(y_tiled, A) = (X, Y, S) 384 * where X = X' / cpp 385 * Y = Y' % qpitch 386 * S = Y' / qpitch 387 * Y' = (tile_num / tile_pitch) << 5 388 * | (A & 0b111110000) >> 4 389 * X' = (tile_num % tile_pitch) << 7 390 * | (A & 0b111000000000) >> 5 391 * | (A & 0b1111) 392 * 393 * For W tiling, tile() combines together the low-order bits of the X and Y 394 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64 395 * bytes wide and 64 rows high (note that W tiling is only used for stencil 396 * buffers, which always have cpp = 1 and S=0): 397 * 398 * tile(w_tiled, X, Y, S) = A 399 * where A = tile_num << 12 | offset 400 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6) 401 * offset = (X' & 0b111000) << 6 402 * | (Y' & 0b111100) << 3 403 * | (X' & 0b100) << 2 404 * | (Y' & 0b10) << 2 405 * | (X' & 0b10) << 1 406 * | (Y' & 0b1) << 1 407 * | (X' & 0b1) 408 * X' = X * cpp = X 409 * Y' = Y + S * qpitch 410 * detile(w_tiled, A) = (X, Y, S) 411 * where X = X' / cpp = X' 412 * Y = Y' % qpitch = Y' 413 * S = Y / qpitch = 0 414 * Y' = (tile_num / tile_pitch) << 6 415 * | (A & 0b111100000) >> 3 416 * | (A & 0b1000) >> 2 417 * | (A & 0b10) >> 1 418 * X' = (tile_num % tile_pitch) << 6 419 * | (A & 0b111000000000) >> 6 420 * | (A & 0b10000) >> 2 421 * | (A & 0b100) >> 1 422 * | (A & 0b1) 423 * 424 * Finally, for a non-tiled surface, tile() simply combines together the X and 425 * Y coordinates in the natural way: 426 * 427 * tile(untiled, X, Y, S) = A 428 * where A = Y * pitch + X' 429 * X' = X * cpp 430 * Y' = Y + S * qpitch 431 * detile(untiled, A) = (X, Y, S) 432 * where X = X' / cpp 433 * Y = Y' % qpitch 434 * S = Y' / qpitch 435 * X' = A % pitch 436 * Y' = A / pitch 437 * 438 * (In these formulas, pitch is the number of bytes occupied by a single row 439 * of samples). 440 */ 441class brw_blorp_blit_program 442{ 443public: 444 brw_blorp_blit_program(struct brw_context *brw, 445 const brw_blorp_blit_prog_key *key); 446 ~brw_blorp_blit_program(); 447 448 const GLuint *compile(struct brw_context *brw, GLuint *program_size); 449 450 brw_blorp_prog_data prog_data; 451 452private: 453 void alloc_regs(); 454 void alloc_push_const_regs(int base_reg); 455 void compute_frag_coords(); 456 void translate_tiling(bool old_tiled_w, bool new_tiled_w); 457 void encode_msaa(unsigned num_samples, intel_msaa_layout layout); 458 void decode_msaa(unsigned num_samples, intel_msaa_layout layout); 459 void kill_if_outside_dst_rect(); 460 void translate_dst_to_src(); 461 void single_to_blend(); 462 void manual_blend(unsigned num_samples); 463 void sample(struct brw_reg dst); 464 void texel_fetch(struct brw_reg dst); 465 void mcs_fetch(); 466 void expand_to_32_bits(struct brw_reg src, struct brw_reg dst); 467 void texture_lookup(struct brw_reg dst, GLuint msg_type, 468 const sampler_message_arg *args, int num_args); 469 void render_target_write(); 470 471 /** 472 * Base-2 logarithm of the maximum number of samples that can be blended. 473 */ 474 static const unsigned LOG2_MAX_BLEND_SAMPLES = 3; 475 476 void *mem_ctx; 477 struct brw_context *brw; 478 const brw_blorp_blit_prog_key *key; 479 struct brw_compile func; 480 481 /* Thread dispatch header */ 482 struct brw_reg R0; 483 484 /* Pixel X/Y coordinates (always in R1). */ 485 struct brw_reg R1; 486 487 /* Push constants */ 488 struct brw_reg dst_x0; 489 struct brw_reg dst_x1; 490 struct brw_reg dst_y0; 491 struct brw_reg dst_y1; 492 struct { 493 struct brw_reg multiplier; 494 struct brw_reg offset; 495 } x_transform, y_transform; 496 497 /* Data read from texture (4 vec16's per array element) */ 498 struct brw_reg texture_data[LOG2_MAX_BLEND_SAMPLES + 1]; 499 500 /* Auxiliary storage for the contents of the MCS surface. 501 * 502 * Since the sampler always returns 8 registers worth of data, this is 8 503 * registers wide, even though we only use the first 2 registers of it. 504 */ 505 struct brw_reg mcs_data; 506 507 /* X coordinates. We have two of them so that we can perform coordinate 508 * transformations easily. 509 */ 510 struct brw_reg x_coords[2]; 511 512 /* Y coordinates. We have two of them so that we can perform coordinate 513 * transformations easily. 514 */ 515 struct brw_reg y_coords[2]; 516 517 /* Which element of x_coords and y_coords is currently in use. 518 */ 519 int xy_coord_index; 520 521 /* True if, at the point in the program currently being compiled, the 522 * sample index is known to be zero. 523 */ 524 bool s_is_zero; 525 526 /* Register storing the sample index when s_is_zero is false. */ 527 struct brw_reg sample_index; 528 529 /* Temporaries */ 530 struct brw_reg t1; 531 struct brw_reg t2; 532 533 /* MRF used for sampling and render target writes */ 534 GLuint base_mrf; 535}; 536 537brw_blorp_blit_program::brw_blorp_blit_program( 538 struct brw_context *brw, 539 const brw_blorp_blit_prog_key *key) 540 : mem_ctx(ralloc_context(NULL)), 541 brw(brw), 542 key(key) 543{ 544 brw_init_compile(brw, &func, mem_ctx); 545} 546 547brw_blorp_blit_program::~brw_blorp_blit_program() 548{ 549 ralloc_free(mem_ctx); 550} 551 552const GLuint * 553brw_blorp_blit_program::compile(struct brw_context *brw, 554 GLuint *program_size) 555{ 556 /* Sanity checks */ 557 if (key->dst_tiled_w && key->rt_samples > 0) { 558 /* If the destination image is W tiled and multisampled, then the thread 559 * must be dispatched once per sample, not once per pixel. This is 560 * necessary because after conversion between W and Y tiling, there's no 561 * guarantee that all samples corresponding to a single pixel will still 562 * be together. 563 */ 564 assert(key->persample_msaa_dispatch); 565 } 566 567 if (key->blend) { 568 /* We are blending, which means we won't have an opportunity to 569 * translate the tiling and sample count for the texture surface. So 570 * the surface state for the texture must be configured with the correct 571 * tiling and sample count. 572 */ 573 assert(!key->src_tiled_w); 574 assert(key->tex_samples == key->src_samples); 575 assert(key->tex_layout == key->src_layout); 576 assert(key->tex_samples > 0); 577 } 578 579 if (key->persample_msaa_dispatch) { 580 /* It only makes sense to do persample dispatch if the render target is 581 * configured as multisampled. 582 */ 583 assert(key->rt_samples > 0); 584 } 585 586 /* Make sure layout is consistent with sample count */ 587 assert((key->tex_layout == INTEL_MSAA_LAYOUT_NONE) == 588 (key->tex_samples == 0)); 589 assert((key->rt_layout == INTEL_MSAA_LAYOUT_NONE) == 590 (key->rt_samples == 0)); 591 assert((key->src_layout == INTEL_MSAA_LAYOUT_NONE) == 592 (key->src_samples == 0)); 593 assert((key->dst_layout == INTEL_MSAA_LAYOUT_NONE) == 594 (key->dst_samples == 0)); 595 596 /* Set up prog_data */ 597 memset(&prog_data, 0, sizeof(prog_data)); 598 prog_data.persample_msaa_dispatch = key->persample_msaa_dispatch; 599 600 brw_set_compression_control(&func, BRW_COMPRESSION_NONE); 601 602 alloc_regs(); 603 compute_frag_coords(); 604 605 /* Render target and texture hardware don't support W tiling. */ 606 const bool rt_tiled_w = false; 607 const bool tex_tiled_w = false; 608 609 /* The address that data will be written to is determined by the 610 * coordinates supplied to the WM thread and the tiling and sample count of 611 * the render target, according to the formula: 612 * 613 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset)) 614 * 615 * If the actual tiling and sample count of the destination surface are not 616 * the same as the configuration of the render target, then these 617 * coordinates are wrong and we have to adjust them to compensate for the 618 * difference. 619 */ 620 if (rt_tiled_w != key->dst_tiled_w || 621 key->rt_samples != key->dst_samples || 622 key->rt_layout != key->dst_layout) { 623 encode_msaa(key->rt_samples, key->rt_layout); 624 /* Now (X, Y, S) = detile(rt_tiling, offset) */ 625 translate_tiling(rt_tiled_w, key->dst_tiled_w); 626 /* Now (X, Y, S) = detile(dst_tiling, offset) */ 627 decode_msaa(key->dst_samples, key->dst_layout); 628 } 629 630 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)). 631 * 632 * That is: X, Y and S now contain the true coordinates and sample index of 633 * the data that the WM thread should output. 634 * 635 * If we need to kill pixels that are outside the destination rectangle, 636 * now is the time to do it. 637 */ 638 639 if (key->use_kill) 640 kill_if_outside_dst_rect(); 641 642 /* Next, apply a translation to obtain coordinates in the source image. */ 643 translate_dst_to_src(); 644 645 /* If the source image is not multisampled, then we want to fetch sample 646 * number 0, because that's the only sample there is. 647 */ 648 if (key->src_samples == 0) 649 s_is_zero = true; 650 651 /* X, Y, and S are now the coordinates of the pixel in the source image 652 * that we want to texture from. Exception: if we are blending, then S is 653 * irrelevant, because we are going to fetch all samples. 654 */ 655 if (key->blend) { 656 if (brw->intel.gen == 6) { 657 /* Gen6 hardware an automatically blend using the SAMPLE message */ 658 single_to_blend(); 659 sample(texture_data[0]); 660 } else { 661 /* Gen7+ hardware doesn't automaticaly blend. */ 662 manual_blend(key->src_samples); 663 } 664 } else { 665 /* We aren't blending, which means we just want to fetch a single sample 666 * from the source surface. The address that we want to fetch from is 667 * related to the X, Y and S values according to the formula: 668 * 669 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)). 670 * 671 * If the actual tiling and sample count of the source surface are not 672 * the same as the configuration of the texture, then we need to adjust 673 * the coordinates to compensate for the difference. 674 */ 675 if (tex_tiled_w != key->src_tiled_w || 676 key->tex_samples != key->src_samples || 677 key->tex_layout != key->src_layout) { 678 encode_msaa(key->src_samples, key->src_layout); 679 /* Now (X, Y, S) = detile(src_tiling, offset) */ 680 translate_tiling(key->src_tiled_w, tex_tiled_w); 681 /* Now (X, Y, S) = detile(tex_tiling, offset) */ 682 decode_msaa(key->tex_samples, key->tex_layout); 683 } 684 685 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)). 686 * 687 * In other words: X, Y, and S now contain values which, when passed to 688 * the texturing unit, will cause data to be read from the correct 689 * memory location. So we can fetch the texel now. 690 */ 691 if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS) 692 mcs_fetch(); 693 texel_fetch(texture_data[0]); 694 } 695 696 /* Finally, write the fetched (or blended) value to the render target and 697 * terminate the thread. 698 */ 699 render_target_write(); 700 return brw_get_program(&func, program_size); 701} 702 703void 704brw_blorp_blit_program::alloc_push_const_regs(int base_reg) 705{ 706#define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name) 707#define ALLOC_REG(name) \ 708 this->name = \ 709 brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, base_reg, CONST_LOC(name) / 2) 710 711 ALLOC_REG(dst_x0); 712 ALLOC_REG(dst_x1); 713 ALLOC_REG(dst_y0); 714 ALLOC_REG(dst_y1); 715 ALLOC_REG(x_transform.multiplier); 716 ALLOC_REG(x_transform.offset); 717 ALLOC_REG(y_transform.multiplier); 718 ALLOC_REG(y_transform.offset); 719#undef CONST_LOC 720#undef ALLOC_REG 721} 722 723void 724brw_blorp_blit_program::alloc_regs() 725{ 726 int reg = 0; 727 this->R0 = retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW); 728 this->R1 = retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW); 729 prog_data.first_curbe_grf = reg; 730 alloc_push_const_regs(reg); 731 reg += BRW_BLORP_NUM_PUSH_CONST_REGS; 732 for (unsigned i = 0; i < ARRAY_SIZE(texture_data); ++i) { 733 this->texture_data[i] = 734 retype(vec16(brw_vec8_grf(reg, 0)), key->texture_data_type); 735 reg += 8; 736 } 737 this->mcs_data = 738 retype(brw_vec8_grf(reg, 0), BRW_REGISTER_TYPE_UD); reg += 8; 739 for (int i = 0; i < 2; ++i) { 740 this->x_coords[i] 741 = vec16(retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW)); 742 this->y_coords[i] 743 = vec16(retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW)); 744 } 745 this->xy_coord_index = 0; 746 this->sample_index 747 = vec16(retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW)); 748 this->t1 = vec16(retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW)); 749 this->t2 = vec16(retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW)); 750 751 /* Make sure we didn't run out of registers */ 752 assert(reg <= GEN7_MRF_HACK_START); 753 754 int mrf = 2; 755 this->base_mrf = mrf; 756} 757 758/* In the code that follows, X and Y can be used to quickly refer to the 759 * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y 760 * prime") to the inactive elements. 761 * 762 * S can be used to quickly refer to sample_index. 763 */ 764#define X x_coords[xy_coord_index] 765#define Y y_coords[xy_coord_index] 766#define Xp x_coords[!xy_coord_index] 767#define Yp y_coords[!xy_coord_index] 768#define S sample_index 769 770/* Quickly swap the roles of (X, Y) and (Xp, Yp). Saves us from having to do 771 * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation. 772 */ 773#define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index; 774 775/** 776 * Emit code to compute the X and Y coordinates of the pixels being rendered 777 * by this WM invocation. 778 * 779 * Assuming the render target is set up for Y tiling, these (X, Y) values are 780 * related to the address offset where outputs will be written by the formula: 781 * 782 * (X, Y, S) = decode_msaa(detile(offset)). 783 * 784 * (See brw_blorp_blit_program). 785 */ 786void 787brw_blorp_blit_program::compute_frag_coords() 788{ 789 /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0) 790 * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4) 791 * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8) 792 * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12) 793 * 794 * Pixels within a subspan are laid out in this arrangement: 795 * 0 1 796 * 2 3 797 * 798 * So, to compute the coordinates of each pixel, we need to read every 2nd 799 * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value 800 * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4). 801 * In other words, the data we want to access is R1.4<2;4,0>UW. 802 * 803 * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the 804 * result, since pixels n+1 and n+3 are in the right half of the subspan. 805 */ 806 brw_ADD(&func, X, stride(suboffset(R1, 4), 2, 4, 0), brw_imm_v(0x10101010)); 807 808 /* Similarly, Y coordinates for subspans come from R1.2[31:16] through 809 * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th 810 * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of 811 * R1.4<2;4,0>UW). 812 * 813 * And we need to add the repeating sequence (0, 0, 1, 1, ...), since 814 * pixels n+2 and n+3 are in the bottom half of the subspan. 815 */ 816 brw_ADD(&func, Y, stride(suboffset(R1, 5), 2, 4, 0), brw_imm_v(0x11001100)); 817 818 if (key->persample_msaa_dispatch) { 819 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples > 0. 820 * Therefore, subspan 0 will represent sample 0, subspan 1 will 821 * represent sample 1, and so on. 822 * 823 * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1, 1, 824 * 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to populate a 825 * temporary variable with the sequence (0, 1, 2, 3), and then copy from 826 * it using vstride=1, width=4, hstride=0. 827 * 828 * TODO: implement the necessary calculation for 8x multisampling. 829 */ 830 brw_MOV(&func, t1, brw_imm_v(0x3210)); 831 brw_MOV(&func, S, stride(t1, 1, 4, 0)); 832 s_is_zero = false; 833 } else { 834 /* Either the destination surface is single-sampled, or the WM will be 835 * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch 836 * per pixel). In either case, it's not meaningful to compute a sample 837 * value. Just set it to 0. 838 */ 839 s_is_zero = true; 840 } 841} 842 843/** 844 * Emit code to compensate for the difference between Y and W tiling. 845 * 846 * This code modifies the X and Y coordinates according to the formula: 847 * 848 * (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S)) 849 * 850 * (See brw_blorp_blit_program). 851 * 852 * It can only translate between W and Y tiling, so new_tiling and old_tiling 853 * are booleans where true represents W tiling and false represents Y tiling. 854 */ 855void 856brw_blorp_blit_program::translate_tiling(bool old_tiled_w, bool new_tiled_w) 857{ 858 if (old_tiled_w == new_tiled_w) 859 return; 860 861 /* In the code that follows, we can safely assume that S = 0, because W 862 * tiling formats always use IMS layout. 863 */ 864 assert(s_is_zero); 865 866 if (new_tiled_w) { 867 /* Given X and Y coordinates that describe an address using Y tiling, 868 * translate to the X and Y coordinates that describe the same address 869 * using W tiling. 870 * 871 * If we break down the low order bits of X and Y, using a 872 * single letter to represent each low-order bit: 873 * 874 * X = A << 7 | 0bBCDEFGH 875 * Y = J << 5 | 0bKLMNP (1) 876 * 877 * Then we can apply the Y tiling formula to see the memory offset being 878 * addressed: 879 * 880 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2) 881 * 882 * If we apply the W detiling formula to this memory location, that the 883 * corresponding X' and Y' coordinates are: 884 * 885 * X' = A << 6 | 0bBCDPFH (3) 886 * Y' = J << 6 | 0bKLMNEG 887 * 888 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'), 889 * we need to make the following computation: 890 * 891 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4) 892 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1 893 */ 894 brw_AND(&func, t1, X, brw_imm_uw(0xfff4)); /* X & ~0b1011 */ 895 brw_SHR(&func, t1, t1, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */ 896 brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */ 897 brw_SHL(&func, t2, t2, brw_imm_uw(2)); /* (Y & 0b1) << 2 */ 898 brw_OR(&func, t1, t1, t2); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */ 899 brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */ 900 brw_OR(&func, Xp, t1, t2); 901 brw_AND(&func, t1, Y, brw_imm_uw(0xfffe)); /* Y & ~0b1 */ 902 brw_SHL(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */ 903 brw_AND(&func, t2, X, brw_imm_uw(8)); /* X & 0b1000 */ 904 brw_SHR(&func, t2, t2, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */ 905 brw_OR(&func, t1, t1, t2); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */ 906 brw_AND(&func, t2, X, brw_imm_uw(2)); /* X & 0b10 */ 907 brw_SHR(&func, t2, t2, brw_imm_uw(1)); /* (X & 0b10) >> 1 */ 908 brw_OR(&func, Yp, t1, t2); 909 SWAP_XY_AND_XPYP(); 910 } else { 911 /* Applying the same logic as above, but in reverse, we obtain the 912 * formulas: 913 * 914 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1 915 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2 916 */ 917 brw_AND(&func, t1, X, brw_imm_uw(0xfffa)); /* X & ~0b101 */ 918 brw_SHL(&func, t1, t1, brw_imm_uw(1)); /* (X & ~0b101) << 1 */ 919 brw_AND(&func, t2, Y, brw_imm_uw(2)); /* Y & 0b10 */ 920 brw_SHL(&func, t2, t2, brw_imm_uw(2)); /* (Y & 0b10) << 2 */ 921 brw_OR(&func, t1, t1, t2); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */ 922 brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */ 923 brw_SHL(&func, t2, t2, brw_imm_uw(1)); /* (Y & 0b1) << 1 */ 924 brw_OR(&func, t1, t1, t2); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 925 | (Y & 0b1) << 1 */ 926 brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */ 927 brw_OR(&func, Xp, t1, t2); 928 brw_AND(&func, t1, Y, brw_imm_uw(0xfffc)); /* Y & ~0b11 */ 929 brw_SHR(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */ 930 brw_AND(&func, t2, X, brw_imm_uw(4)); /* X & 0b100 */ 931 brw_SHR(&func, t2, t2, brw_imm_uw(2)); /* (X & 0b100) >> 2 */ 932 brw_OR(&func, Yp, t1, t2); 933 SWAP_XY_AND_XPYP(); 934 } 935} 936 937/** 938 * Emit code to compensate for the difference between MSAA and non-MSAA 939 * surfaces. 940 * 941 * This code modifies the X and Y coordinates according to the formula: 942 * 943 * (X', Y', S') = encode_msaa_4x(X, Y, S) 944 * 945 * (See brw_blorp_blit_program). 946 */ 947void 948brw_blorp_blit_program::encode_msaa(unsigned num_samples, 949 intel_msaa_layout layout) 950{ 951 switch (layout) { 952 case INTEL_MSAA_LAYOUT_NONE: 953 /* No translation necessary, and S should already be zero. */ 954 assert(s_is_zero); 955 break; 956 case INTEL_MSAA_LAYOUT_CMS: 957 /* We can't compensate for compressed layout since at this point in the 958 * program we haven't read from the MCS buffer. 959 */ 960 assert(!"Bad layout in encode_msaa"); 961 break; 962 case INTEL_MSAA_LAYOUT_UMS: 963 /* No translation necessary. */ 964 break; 965 case INTEL_MSAA_LAYOUT_IMS: 966 /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0) 967 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1) 968 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1) 969 */ 970 brw_AND(&func, t1, X, brw_imm_uw(0xfffe)); /* X & ~0b1 */ 971 if (!s_is_zero) { 972 brw_AND(&func, t2, S, brw_imm_uw(1)); /* S & 0b1 */ 973 brw_OR(&func, t1, t1, t2); /* (X & ~0b1) | (S & 0b1) */ 974 } 975 brw_SHL(&func, t1, t1, brw_imm_uw(1)); /* (X & ~0b1) << 1 976 | (S & 0b1) << 1 */ 977 brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */ 978 brw_OR(&func, Xp, t1, t2); 979 brw_AND(&func, t1, Y, brw_imm_uw(0xfffe)); /* Y & ~0b1 */ 980 brw_SHL(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */ 981 if (!s_is_zero) { 982 brw_AND(&func, t2, S, brw_imm_uw(2)); /* S & 0b10 */ 983 brw_OR(&func, t1, t1, t2); /* (Y & ~0b1) << 1 | (S & 0b10) */ 984 } 985 brw_AND(&func, t2, Y, brw_imm_uw(1)); 986 brw_OR(&func, Yp, t1, t2); 987 SWAP_XY_AND_XPYP(); 988 s_is_zero = true; 989 break; 990 } 991} 992 993/** 994 * Emit code to compensate for the difference between MSAA and non-MSAA 995 * surfaces. 996 * 997 * This code modifies the X and Y coordinates according to the formula: 998 * 999 * (X', Y', S) = decode_msaa(num_samples, X, Y, S) 1000 * 1001 * (See brw_blorp_blit_program). 1002 */ 1003void 1004brw_blorp_blit_program::decode_msaa(unsigned num_samples, 1005 intel_msaa_layout layout) 1006{ 1007 switch (layout) { 1008 case INTEL_MSAA_LAYOUT_NONE: 1009 /* No translation necessary, and S should already be zero. */ 1010 assert(s_is_zero); 1011 break; 1012 case INTEL_MSAA_LAYOUT_CMS: 1013 /* We can't compensate for compressed layout since at this point in the 1014 * program we don't have access to the MCS buffer. 1015 */ 1016 assert(!"Bad layout in encode_msaa"); 1017 break; 1018 case INTEL_MSAA_LAYOUT_UMS: 1019 /* No translation necessary. */ 1020 break; 1021 case INTEL_MSAA_LAYOUT_IMS: 1022 /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S) 1023 * where X' = (X & ~0b11) >> 1 | (X & 0b1) 1024 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1) 1025 * S = (Y & 0b10) | (X & 0b10) >> 1 1026 */ 1027 assert(s_is_zero); 1028 brw_AND(&func, t1, X, brw_imm_uw(0xfffc)); /* X & ~0b11 */ 1029 brw_SHR(&func, t1, t1, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */ 1030 brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */ 1031 brw_OR(&func, Xp, t1, t2); 1032 brw_AND(&func, t1, Y, brw_imm_uw(0xfffc)); /* Y & ~0b11 */ 1033 brw_SHR(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */ 1034 brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */ 1035 brw_OR(&func, Yp, t1, t2); 1036 brw_AND(&func, t1, Y, brw_imm_uw(2)); /* Y & 0b10 */ 1037 brw_AND(&func, t2, X, brw_imm_uw(2)); /* X & 0b10 */ 1038 brw_SHR(&func, t2, t2, brw_imm_uw(1)); /* (X & 0b10) >> 1 */ 1039 brw_OR(&func, S, t1, t2); 1040 s_is_zero = false; 1041 SWAP_XY_AND_XPYP(); 1042 break; 1043 } 1044} 1045 1046/** 1047 * Emit code that kills pixels whose X and Y coordinates are outside the 1048 * boundary of the rectangle defined by the push constants (dst_x0, dst_y0, 1049 * dst_x1, dst_y1). 1050 */ 1051void 1052brw_blorp_blit_program::kill_if_outside_dst_rect() 1053{ 1054 struct brw_reg f0 = brw_flag_reg(); 1055 struct brw_reg g1 = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW); 1056 struct brw_reg null16 = vec16(retype(brw_null_reg(), BRW_REGISTER_TYPE_UW)); 1057 1058 brw_CMP(&func, null16, BRW_CONDITIONAL_GE, X, dst_x0); 1059 brw_CMP(&func, null16, BRW_CONDITIONAL_GE, Y, dst_y0); 1060 brw_CMP(&func, null16, BRW_CONDITIONAL_L, X, dst_x1); 1061 brw_CMP(&func, null16, BRW_CONDITIONAL_L, Y, dst_y1); 1062 1063 brw_set_predicate_control(&func, BRW_PREDICATE_NONE); 1064 brw_push_insn_state(&func); 1065 brw_set_mask_control(&func, BRW_MASK_DISABLE); 1066 brw_AND(&func, g1, f0, g1); 1067 brw_pop_insn_state(&func); 1068} 1069 1070/** 1071 * Emit code to translate from destination (X, Y) coordinates to source (X, Y) 1072 * coordinates. 1073 */ 1074void 1075brw_blorp_blit_program::translate_dst_to_src() 1076{ 1077 brw_MUL(&func, Xp, X, x_transform.multiplier); 1078 brw_MUL(&func, Yp, Y, y_transform.multiplier); 1079 brw_ADD(&func, Xp, Xp, x_transform.offset); 1080 brw_ADD(&func, Yp, Yp, y_transform.offset); 1081 SWAP_XY_AND_XPYP(); 1082} 1083 1084/** 1085 * Emit code to transform the X and Y coordinates as needed for blending 1086 * together the different samples in an MSAA texture. 1087 */ 1088void 1089brw_blorp_blit_program::single_to_blend() 1090{ 1091 /* When looking up samples in an MSAA texture using the SAMPLE message, 1092 * Gen6 requires the texture coordinates to be odd integers (so that they 1093 * correspond to the center of a 2x2 block representing the four samples 1094 * that maxe up a pixel). So we need to multiply our X and Y coordinates 1095 * each by 2 and then add 1. 1096 */ 1097 brw_SHL(&func, t1, X, brw_imm_w(1)); 1098 brw_SHL(&func, t2, Y, brw_imm_w(1)); 1099 brw_ADD(&func, Xp, t1, brw_imm_w(1)); 1100 brw_ADD(&func, Yp, t2, brw_imm_w(1)); 1101 SWAP_XY_AND_XPYP(); 1102} 1103 1104 1105/** 1106 * Count the number of trailing 1 bits in the given value. For example: 1107 * 1108 * count_trailing_one_bits(0) == 0 1109 * count_trailing_one_bits(7) == 3 1110 * count_trailing_one_bits(11) == 2 1111 */ 1112inline int count_trailing_one_bits(unsigned value) 1113{ 1114#if defined(__GNUC__) && ((__GNUC__ * 100 + __GNUC_MINOR__) >= 304) /* gcc 3.4 or later */ 1115 return __builtin_ctz(~value); 1116#else 1117 return _mesa_bitcount(value & ~(value + 1)); 1118#endif 1119} 1120 1121 1122void 1123brw_blorp_blit_program::manual_blend(unsigned num_samples) 1124{ 1125 if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS) 1126 mcs_fetch(); 1127 1128 /* We add together samples using a binary tree structure, e.g. for 4x MSAA: 1129 * 1130 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4 1131 * 1132 * This ensures that when all samples have the same value, no numerical 1133 * precision is lost, since each addition operation always adds two equal 1134 * values, and summing two equal floating point values does not lose 1135 * precision. 1136 * 1137 * We perform this computation by treating the texture_data array as a 1138 * stack and performing the following operations: 1139 * 1140 * - push sample 0 onto stack 1141 * - push sample 1 onto stack 1142 * - add top two stack entries 1143 * - push sample 2 onto stack 1144 * - push sample 3 onto stack 1145 * - add top two stack entries 1146 * - add top two stack entries 1147 * - divide top stack entry by 4 1148 * 1149 * Note that after pushing sample i onto the stack, the number of add 1150 * operations we do is equal to the number of trailing 1 bits in i. This 1151 * works provided the total number of samples is a power of two, which it 1152 * always is for i965. 1153 * 1154 * For integer formats, we replace the add operations with average 1155 * operations and skip the final division. 1156 */ 1157 typedef struct brw_instruction *(*brw_op2_ptr)(struct brw_compile *, 1158 struct brw_reg, 1159 struct brw_reg, 1160 struct brw_reg); 1161 brw_op2_ptr combine_op = 1162 key->texture_data_type == BRW_REGISTER_TYPE_F ? brw_ADD : brw_AVG; 1163 unsigned stack_depth = 0; 1164 for (unsigned i = 0; i < num_samples; ++i) { 1165 assert(stack_depth == _mesa_bitcount(i)); /* Loop invariant */ 1166 1167 /* Push sample i onto the stack */ 1168 assert(stack_depth < ARRAY_SIZE(texture_data)); 1169 if (i == 0) { 1170 s_is_zero = true; 1171 } else { 1172 s_is_zero = false; 1173 brw_MOV(&func, S, brw_imm_uw(i)); 1174 } 1175 texel_fetch(texture_data[stack_depth++]); 1176 1177 if (i == 0 && key->tex_layout == INTEL_MSAA_LAYOUT_CMS) { 1178 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface) 1179 * suggests an optimization: 1180 * 1181 * "A simple optimization with probable large return in 1182 * performance is to compare the MCS value to zero (indicating 1183 * all samples are on sample slice 0), and sample only from 1184 * sample slice 0 using ld2dss if MCS is zero." 1185 * 1186 * Note that in the case where the MCS value is zero, sampling from 1187 * sample slice 0 using ld2dss and sampling from sample 0 using 1188 * ld2dms are equivalent (since all samples are on sample slice 0). 1189 * Since we have already sampled from sample 0, all we need to do is 1190 * skip the remaining fetches and averaging if MCS is zero. 1191 */ 1192 brw_CMP(&func, vec16(brw_null_reg()), BRW_CONDITIONAL_NZ, 1193 mcs_data, brw_imm_ud(0)); 1194 brw_IF(&func, BRW_EXECUTE_16); 1195 } 1196 1197 /* Do count_trailing_one_bits(i) times */ 1198 for (int j = count_trailing_one_bits(i); j-- > 0; ) { 1199 assert(stack_depth >= 2); 1200 --stack_depth; 1201 1202 /* TODO: should use a smaller loop bound for non_RGBA formats */ 1203 for (int k = 0; k < 4; ++k) { 1204 combine_op(&func, offset(texture_data[stack_depth - 1], 2*k), 1205 offset(vec8(texture_data[stack_depth - 1]), 2*k), 1206 offset(vec8(texture_data[stack_depth]), 2*k)); 1207 } 1208 } 1209 } 1210 1211 /* We should have just 1 sample on the stack now. */ 1212 assert(stack_depth == 1); 1213 1214 if (key->texture_data_type == BRW_REGISTER_TYPE_F) { 1215 /* Scale the result down by a factor of num_samples */ 1216 /* TODO: should use a smaller loop bound for non-RGBA formats */ 1217 for (int j = 0; j < 4; ++j) { 1218 brw_MUL(&func, offset(texture_data[0], 2*j), 1219 offset(vec8(texture_data[0]), 2*j), 1220 brw_imm_f(1.0/num_samples)); 1221 } 1222 } 1223 1224 if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS) 1225 brw_ENDIF(&func); 1226} 1227 1228/** 1229 * Emit code to look up a value in the texture using the SAMPLE message (which 1230 * does blending of MSAA surfaces). 1231 */ 1232void 1233brw_blorp_blit_program::sample(struct brw_reg dst) 1234{ 1235 static const sampler_message_arg args[2] = { 1236 SAMPLER_MESSAGE_ARG_U_FLOAT, 1237 SAMPLER_MESSAGE_ARG_V_FLOAT 1238 }; 1239 1240 texture_lookup(dst, GEN5_SAMPLER_MESSAGE_SAMPLE, args, ARRAY_SIZE(args)); 1241} 1242 1243/** 1244 * Emit code to look up a value in the texture using the SAMPLE_LD message 1245 * (which does a simple texel fetch). 1246 */ 1247void 1248brw_blorp_blit_program::texel_fetch(struct brw_reg dst) 1249{ 1250 static const sampler_message_arg gen6_args[5] = { 1251 SAMPLER_MESSAGE_ARG_U_INT, 1252 SAMPLER_MESSAGE_ARG_V_INT, 1253 SAMPLER_MESSAGE_ARG_ZERO_INT, /* R */ 1254 SAMPLER_MESSAGE_ARG_ZERO_INT, /* LOD */ 1255 SAMPLER_MESSAGE_ARG_SI_INT 1256 }; 1257 static const sampler_message_arg gen7_ld_args[3] = { 1258 SAMPLER_MESSAGE_ARG_U_INT, 1259 SAMPLER_MESSAGE_ARG_ZERO_INT, /* LOD */ 1260 SAMPLER_MESSAGE_ARG_V_INT 1261 }; 1262 static const sampler_message_arg gen7_ld2dss_args[3] = { 1263 SAMPLER_MESSAGE_ARG_SI_INT, 1264 SAMPLER_MESSAGE_ARG_U_INT, 1265 SAMPLER_MESSAGE_ARG_V_INT 1266 }; 1267 static const sampler_message_arg gen7_ld2dms_args[4] = { 1268 SAMPLER_MESSAGE_ARG_SI_INT, 1269 SAMPLER_MESSAGE_ARG_MCS_INT, 1270 SAMPLER_MESSAGE_ARG_U_INT, 1271 SAMPLER_MESSAGE_ARG_V_INT 1272 }; 1273 1274 switch (brw->intel.gen) { 1275 case 6: 1276 texture_lookup(dst, GEN5_SAMPLER_MESSAGE_SAMPLE_LD, gen6_args, 1277 s_is_zero ? 2 : 5); 1278 break; 1279 case 7: 1280 switch (key->tex_layout) { 1281 case INTEL_MSAA_LAYOUT_IMS: 1282 /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage 1283 * Format): 1284 * 1285 * If this field is MSFMT_DEPTH_STENCIL 1286 * [a.k.a. INTEL_MSAA_LAYOUT_IMS], the only sampling engine 1287 * messages allowed are "ld2dms", "resinfo", and "sampleinfo". 1288 * 1289 * So fall through to emit the same message as we use for 1290 * INTEL_MSAA_LAYOUT_CMS. 1291 */ 1292 case INTEL_MSAA_LAYOUT_CMS: 1293 texture_lookup(dst, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS, 1294 gen7_ld2dms_args, ARRAY_SIZE(gen7_ld2dms_args)); 1295 break; 1296 case INTEL_MSAA_LAYOUT_UMS: 1297 texture_lookup(dst, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS, 1298 gen7_ld2dss_args, ARRAY_SIZE(gen7_ld2dss_args)); 1299 break; 1300 case INTEL_MSAA_LAYOUT_NONE: 1301 assert(s_is_zero); 1302 texture_lookup(dst, GEN5_SAMPLER_MESSAGE_SAMPLE_LD, gen7_ld_args, 1303 ARRAY_SIZE(gen7_ld_args)); 1304 break; 1305 } 1306 break; 1307 default: 1308 assert(!"Should not get here."); 1309 break; 1310 }; 1311} 1312 1313void 1314brw_blorp_blit_program::mcs_fetch() 1315{ 1316 static const sampler_message_arg gen7_ld_mcs_args[2] = { 1317 SAMPLER_MESSAGE_ARG_U_INT, 1318 SAMPLER_MESSAGE_ARG_V_INT 1319 }; 1320 texture_lookup(vec16(mcs_data), GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS, 1321 gen7_ld_mcs_args, ARRAY_SIZE(gen7_ld_mcs_args)); 1322} 1323 1324void 1325brw_blorp_blit_program::expand_to_32_bits(struct brw_reg src, 1326 struct brw_reg dst) 1327{ 1328 brw_MOV(&func, vec8(dst), vec8(src)); 1329 brw_set_compression_control(&func, BRW_COMPRESSION_2NDHALF); 1330 brw_MOV(&func, offset(vec8(dst), 1), suboffset(vec8(src), 8)); 1331 brw_set_compression_control(&func, BRW_COMPRESSION_NONE); 1332} 1333 1334void 1335brw_blorp_blit_program::texture_lookup(struct brw_reg dst, 1336 GLuint msg_type, 1337 const sampler_message_arg *args, 1338 int num_args) 1339{ 1340 struct brw_reg mrf = 1341 retype(vec16(brw_message_reg(base_mrf)), BRW_REGISTER_TYPE_UD); 1342 for (int arg = 0; arg < num_args; ++arg) { 1343 switch (args[arg]) { 1344 case SAMPLER_MESSAGE_ARG_U_FLOAT: 1345 expand_to_32_bits(X, retype(mrf, BRW_REGISTER_TYPE_F)); 1346 break; 1347 case SAMPLER_MESSAGE_ARG_V_FLOAT: 1348 expand_to_32_bits(Y, retype(mrf, BRW_REGISTER_TYPE_F)); 1349 break; 1350 case SAMPLER_MESSAGE_ARG_U_INT: 1351 expand_to_32_bits(X, mrf); 1352 break; 1353 case SAMPLER_MESSAGE_ARG_V_INT: 1354 expand_to_32_bits(Y, mrf); 1355 break; 1356 case SAMPLER_MESSAGE_ARG_SI_INT: 1357 /* Note: on Gen7, this code may be reached with s_is_zero==true 1358 * because in Gen7's ld2dss message, the sample index is the first 1359 * argument. When this happens, we need to move a 0 into the 1360 * appropriate message register. 1361 */ 1362 if (s_is_zero) 1363 brw_MOV(&func, mrf, brw_imm_ud(0)); 1364 else 1365 expand_to_32_bits(S, mrf); 1366 break; 1367 case SAMPLER_MESSAGE_ARG_MCS_INT: 1368 switch (key->tex_layout) { 1369 case INTEL_MSAA_LAYOUT_CMS: 1370 brw_MOV(&func, mrf, mcs_data); 1371 break; 1372 case INTEL_MSAA_LAYOUT_IMS: 1373 /* When sampling from an IMS surface, MCS data is not relevant, 1374 * and the hardware ignores it. So don't bother populating it. 1375 */ 1376 break; 1377 default: 1378 /* We shouldn't be trying to send MCS data with any other 1379 * layouts. 1380 */ 1381 assert (!"Unsupported layout for MCS data"); 1382 break; 1383 } 1384 break; 1385 case SAMPLER_MESSAGE_ARG_ZERO_INT: 1386 brw_MOV(&func, mrf, brw_imm_ud(0)); 1387 break; 1388 } 1389 mrf.nr += 2; 1390 } 1391 1392 brw_SAMPLE(&func, 1393 retype(dst, BRW_REGISTER_TYPE_UW) /* dest */, 1394 base_mrf /* msg_reg_nr */, 1395 brw_message_reg(base_mrf) /* src0 */, 1396 BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX, 1397 0 /* sampler */, 1398 WRITEMASK_XYZW, 1399 msg_type, 1400 8 /* response_length. TODO: should be smaller for non-RGBA formats? */, 1401 mrf.nr - base_mrf /* msg_length */, 1402 0 /* header_present */, 1403 BRW_SAMPLER_SIMD_MODE_SIMD16, 1404 BRW_SAMPLER_RETURN_FORMAT_FLOAT32); 1405} 1406 1407#undef X 1408#undef Y 1409#undef U 1410#undef V 1411#undef S 1412#undef SWAP_XY_AND_XPYP 1413 1414void 1415brw_blorp_blit_program::render_target_write() 1416{ 1417 struct brw_reg mrf_rt_write = 1418 retype(vec16(brw_message_reg(base_mrf)), key->texture_data_type); 1419 int mrf_offset = 0; 1420 1421 /* If we may have killed pixels, then we need to send R0 and R1 in a header 1422 * so that the render target knows which pixels we killed. 1423 */ 1424 bool use_header = key->use_kill; 1425 if (use_header) { 1426 /* Copy R0/1 to MRF */ 1427 brw_MOV(&func, retype(mrf_rt_write, BRW_REGISTER_TYPE_UD), 1428 retype(R0, BRW_REGISTER_TYPE_UD)); 1429 mrf_offset += 2; 1430 } 1431 1432 /* Copy texture data to MRFs */ 1433 for (int i = 0; i < 4; ++i) { 1434 /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */ 1435 brw_MOV(&func, offset(mrf_rt_write, mrf_offset), 1436 offset(vec8(texture_data[0]), 2*i)); 1437 mrf_offset += 2; 1438 } 1439 1440 /* Now write to the render target and terminate the thread */ 1441 brw_fb_WRITE(&func, 1442 16 /* dispatch_width */, 1443 base_mrf /* msg_reg_nr */, 1444 mrf_rt_write /* src0 */, 1445 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE, 1446 BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX, 1447 mrf_offset /* msg_length. TODO: Should be smaller for non-RGBA formats. */, 1448 0 /* response_length */, 1449 true /* eot */, 1450 use_header); 1451} 1452 1453 1454void 1455brw_blorp_coord_transform_params::setup(GLuint src0, GLuint dst0, GLuint dst1, 1456 bool mirror) 1457{ 1458 if (!mirror) { 1459 /* When not mirroring a coordinate (say, X), we need: 1460 * x' - src_x0 = x - dst_x0 1461 * Therefore: 1462 * x' = 1*x + (src_x0 - dst_x0) 1463 */ 1464 multiplier = 1; 1465 offset = src0 - dst0; 1466 } else { 1467 /* When mirroring X we need: 1468 * x' - src_x0 = dst_x1 - x - 1 1469 * Therefore: 1470 * x' = -1*x + (src_x0 + dst_x1 - 1) 1471 */ 1472 multiplier = -1; 1473 offset = src0 + dst1 - 1; 1474 } 1475} 1476 1477 1478/** 1479 * Determine which MSAA layout the GPU pipeline should be configured for, 1480 * based on the chip generation, the number of samples, and the true layout of 1481 * the image in memory. 1482 */ 1483inline intel_msaa_layout 1484compute_msaa_layout_for_pipeline(struct brw_context *brw, unsigned num_samples, 1485 intel_msaa_layout true_layout) 1486{ 1487 if (num_samples == 0) { 1488 /* When configuring the GPU for non-MSAA, we can still accommodate IMS 1489 * format buffers, by transforming coordinates appropriately. 1490 */ 1491 assert(true_layout == INTEL_MSAA_LAYOUT_NONE || 1492 true_layout == INTEL_MSAA_LAYOUT_IMS); 1493 return INTEL_MSAA_LAYOUT_NONE; 1494 } else { 1495 assert(true_layout != INTEL_MSAA_LAYOUT_NONE); 1496 } 1497 1498 /* Prior to Gen7, all MSAA surfaces use IMS layout. */ 1499 if (brw->intel.gen == 6) { 1500 assert(true_layout == INTEL_MSAA_LAYOUT_IMS); 1501 } 1502 1503 return true_layout; 1504} 1505 1506 1507brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context *brw, 1508 struct intel_mipmap_tree *src_mt, 1509 struct intel_mipmap_tree *dst_mt, 1510 GLuint src_x0, GLuint src_y0, 1511 GLuint dst_x0, GLuint dst_y0, 1512 GLuint dst_x1, GLuint dst_y1, 1513 bool mirror_x, bool mirror_y) 1514{ 1515 src.set(brw, src_mt, 0, 0); 1516 dst.set(brw, dst_mt, 0, 0); 1517 1518 use_wm_prog = true; 1519 memset(&wm_prog_key, 0, sizeof(wm_prog_key)); 1520 1521 /* texture_data_type indicates the register type that should be used to 1522 * manipulate texture data. 1523 */ 1524 switch (_mesa_get_format_datatype(src_mt->format)) { 1525 case GL_UNSIGNED_NORMALIZED: 1526 case GL_SIGNED_NORMALIZED: 1527 case GL_FLOAT: 1528 wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_F; 1529 break; 1530 case GL_UNSIGNED_INT: 1531 if (src_mt->format == MESA_FORMAT_S8) { 1532 /* We process stencil as though it's an unsigned normalized color */ 1533 wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_F; 1534 } else { 1535 wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_UD; 1536 } 1537 break; 1538 case GL_INT: 1539 wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_D; 1540 break; 1541 default: 1542 assert(!"Unrecognized blorp format"); 1543 break; 1544 } 1545 1546 if (brw->intel.gen > 6) { 1547 /* Gen7's rendering hardware only supports the IMS layout for depth and 1548 * stencil render targets. Blorp always maps its destination surface as 1549 * a color render target (even if it's actually a depth or stencil 1550 * buffer). So if the destination is IMS, we'll have to map it as a 1551 * single-sampled texture and interleave the samples ourselves. 1552 */ 1553 if (dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) 1554 dst.num_samples = 0; 1555 } 1556 1557 if (dst.map_stencil_as_y_tiled && dst.num_samples > 0) { 1558 /* If the destination surface is a W-tiled multisampled stencil buffer 1559 * that we're mapping as Y tiled, then we need to arrange for the WM 1560 * program to run once per sample rather than once per pixel, because 1561 * the memory layout of related samples doesn't match between W and Y 1562 * tiling. 1563 */ 1564 wm_prog_key.persample_msaa_dispatch = true; 1565 } 1566 1567 if (src.num_samples > 0 && dst.num_samples > 0) { 1568 /* We are blitting from a multisample buffer to a multisample buffer, so 1569 * we must preserve samples within a pixel. This means we have to 1570 * arrange for the WM program to run once per sample rather than once 1571 * per pixel. 1572 */ 1573 wm_prog_key.persample_msaa_dispatch = true; 1574 } 1575 1576 /* The render path must be configured to use the same number of samples as 1577 * the destination buffer. 1578 */ 1579 num_samples = dst.num_samples; 1580 1581 GLenum base_format = _mesa_get_format_base_format(src_mt->format); 1582 if (base_format != GL_DEPTH_COMPONENT && /* TODO: what about depth/stencil? */ 1583 base_format != GL_STENCIL_INDEX && 1584 src_mt->num_samples > 0 && dst_mt->num_samples == 0) { 1585 /* We are downsampling a color buffer, so blend. */ 1586 wm_prog_key.blend = true; 1587 } 1588 1589 /* src_samples and dst_samples are the true sample counts */ 1590 wm_prog_key.src_samples = src_mt->num_samples; 1591 wm_prog_key.dst_samples = dst_mt->num_samples; 1592 1593 /* tex_samples and rt_samples are the sample counts that are set up in 1594 * SURFACE_STATE. 1595 */ 1596 wm_prog_key.tex_samples = src.num_samples; 1597 wm_prog_key.rt_samples = dst.num_samples; 1598 1599 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will 1600 * use to access the source and destination surfaces. 1601 */ 1602 wm_prog_key.tex_layout = 1603 compute_msaa_layout_for_pipeline(brw, src.num_samples, src.msaa_layout); 1604 wm_prog_key.rt_layout = 1605 compute_msaa_layout_for_pipeline(brw, dst.num_samples, dst.msaa_layout); 1606 1607 /* src_layout and dst_layout indicate the true MSAA layout used by src and 1608 * dst. 1609 */ 1610 wm_prog_key.src_layout = src_mt->msaa_layout; 1611 wm_prog_key.dst_layout = dst_mt->msaa_layout; 1612 1613 wm_prog_key.src_tiled_w = src.map_stencil_as_y_tiled; 1614 wm_prog_key.dst_tiled_w = dst.map_stencil_as_y_tiled; 1615 x0 = wm_push_consts.dst_x0 = dst_x0; 1616 y0 = wm_push_consts.dst_y0 = dst_y0; 1617 x1 = wm_push_consts.dst_x1 = dst_x1; 1618 y1 = wm_push_consts.dst_y1 = dst_y1; 1619 wm_push_consts.x_transform.setup(src_x0, dst_x0, dst_x1, mirror_x); 1620 wm_push_consts.y_transform.setup(src_y0, dst_y0, dst_y1, mirror_y); 1621 1622 if (dst.num_samples == 0 && dst_mt->num_samples > 0) { 1623 /* We must expand the rectangle we send through the rendering pipeline, 1624 * to account for the fact that we are mapping the destination region as 1625 * single-sampled when it is in fact multisampled. We must also align 1626 * it to a multiple of the multisampling pattern, because the 1627 * differences between multisampled and single-sampled surface formats 1628 * will mean that pixels are scrambled within the multisampling pattern. 1629 * TODO: what if this makes the coordinates too large? 1630 * 1631 * Note: this only works if the destination surface uses the IMS layout. 1632 * If it's UMS, then we have no choice but to set up the rendering 1633 * pipeline as multisampled. 1634 */ 1635 assert(dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS); 1636 switch (dst_mt->num_samples) { 1637 case 4: 1638 x0 = (x0 * 2) & ~3; 1639 y0 = (y0 * 2) & ~3; 1640 x1 = ALIGN(x1 * 2, 4); 1641 y1 = ALIGN(y1 * 2, 4); 1642 break; 1643 case 8: 1644 x0 = (x0 * 4) & ~7; 1645 y0 = (y0 * 2) & ~3; 1646 x1 = ALIGN(x1 * 4, 8); 1647 y1 = ALIGN(y1 * 2, 4); 1648 break; 1649 default: 1650 assert(!"Unrecognized sample count in brw_blorp_blit_params ctor"); 1651 break; 1652 } 1653 wm_prog_key.use_kill = true; 1654 } 1655 1656 if (dst.map_stencil_as_y_tiled) { 1657 /* We must modify the rectangle we send through the rendering pipeline, 1658 * to account for the fact that we are mapping it as Y-tiled when it is 1659 * in fact W-tiled. Y tiles have dimensions 128x32 whereas W tiles have 1660 * dimensions 64x64. We must also align it to a multiple of the tile 1661 * size, because the differences between W and Y tiling formats will 1662 * mean that pixels are scrambled within the tile. 1663 * 1664 * Note: if the destination surface configured to use IMS layout, then 1665 * the effective tile size we need to align it to is smaller, because 1666 * each pixel covers a 2x2 or a 4x2 block of samples. 1667 * 1668 * TODO: what if this makes the coordinates too large? 1669 */ 1670 unsigned x_align = 64, y_align = 64; 1671 if (dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) { 1672 x_align /= (dst_mt->num_samples == 4 ? 2 : 4); 1673 y_align /= 2; 1674 } 1675 x0 = (x0 & ~(x_align - 1)) * 2; 1676 y0 = (y0 & ~(y_align - 1)) / 2; 1677 x1 = ALIGN(x1, x_align) * 2; 1678 y1 = ALIGN(y1, y_align) / 2; 1679 wm_prog_key.use_kill = true; 1680 } 1681} 1682 1683uint32_t 1684brw_blorp_blit_params::get_wm_prog(struct brw_context *brw, 1685 brw_blorp_prog_data **prog_data) const 1686{ 1687 uint32_t prog_offset; 1688 if (!brw_search_cache(&brw->cache, BRW_BLORP_BLIT_PROG, 1689 &this->wm_prog_key, sizeof(this->wm_prog_key), 1690 &prog_offset, prog_data)) { 1691 brw_blorp_blit_program prog(brw, &this->wm_prog_key); 1692 GLuint program_size; 1693 const GLuint *program = prog.compile(brw, &program_size); 1694 brw_upload_cache(&brw->cache, BRW_BLORP_BLIT_PROG, 1695 &this->wm_prog_key, sizeof(this->wm_prog_key), 1696 program, program_size, 1697 &prog.prog_data, sizeof(prog.prog_data), 1698 &prog_offset, prog_data); 1699 } 1700 return prog_offset; 1701} 1702