brw_blorp_blit.cpp revision 602e9a0f3727b036caf3a7b228fe90d36d832ea7
1/* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#include "main/teximage.h" 25#include "main/fbobject.h" 26 27#include "glsl/ralloc.h" 28 29#include "intel_fbo.h" 30 31#include "brw_blorp.h" 32#include "brw_context.h" 33#include "brw_eu.h" 34#include "brw_state.h" 35 36 37/** 38 * Helper function for handling mirror image blits. 39 * 40 * If coord0 > coord1, swap them and invert the "mirror" boolean. 41 */ 42static inline void 43fixup_mirroring(bool &mirror, GLint &coord0, GLint &coord1) 44{ 45 if (coord0 > coord1) { 46 mirror = !mirror; 47 GLint tmp = coord0; 48 coord0 = coord1; 49 coord1 = tmp; 50 } 51} 52 53 54/** 55 * Adjust {src,dst}_x{0,1} to account for clipping and scissoring of 56 * destination coordinates. 57 * 58 * Return true if there is still blitting to do, false if all pixels got 59 * rejected by the clip and/or scissor. 60 * 61 * For clarity, the nomenclature of this function assumes we are clipping and 62 * scissoring the X coordinate; the exact same logic applies for Y 63 * coordinates. 64 * 65 * Note: this function may also be used to account for clipping of source 66 * coordinates, by swapping the roles of src and dst. 67 */ 68static inline bool 69clip_or_scissor(bool mirror, GLint &src_x0, GLint &src_x1, GLint &dst_x0, 70 GLint &dst_x1, GLint fb_xmin, GLint fb_xmax) 71{ 72 /* If we are going to scissor everything away, stop. */ 73 if (!(fb_xmin < fb_xmax && 74 dst_x0 < fb_xmax && 75 fb_xmin < dst_x1 && 76 dst_x0 < dst_x1)) { 77 return false; 78 } 79 80 /* Clip the destination rectangle, and keep track of how many pixels we 81 * clipped off of the left and right sides of it. 82 */ 83 GLint pixels_clipped_left = 0; 84 GLint pixels_clipped_right = 0; 85 if (dst_x0 < fb_xmin) { 86 pixels_clipped_left = fb_xmin - dst_x0; 87 dst_x0 = fb_xmin; 88 } 89 if (fb_xmax < dst_x1) { 90 pixels_clipped_right = dst_x1 - fb_xmax; 91 dst_x1 = fb_xmax; 92 } 93 94 /* If we are mirrored, then before applying pixels_clipped_{left,right} to 95 * the source coordinates, we need to flip them to account for the 96 * mirroring. 97 */ 98 if (mirror) { 99 GLint tmp = pixels_clipped_left; 100 pixels_clipped_left = pixels_clipped_right; 101 pixels_clipped_right = tmp; 102 } 103 104 /* Adjust the source rectangle to remove the pixels corresponding to those 105 * that were clipped/scissored out of the destination rectangle. 106 */ 107 src_x0 += pixels_clipped_left; 108 src_x1 -= pixels_clipped_right; 109 110 return true; 111} 112 113 114static struct intel_mipmap_tree * 115find_miptree(GLbitfield buffer_bit, struct intel_renderbuffer *irb) 116{ 117 struct intel_mipmap_tree *mt = irb->mt; 118 if (buffer_bit == GL_STENCIL_BUFFER_BIT && mt->stencil_mt) 119 mt = mt->stencil_mt; 120 return mt; 121} 122 123void 124brw_blorp_blit_miptrees(struct intel_context *intel, 125 struct intel_mipmap_tree *src_mt, 126 struct intel_mipmap_tree *dst_mt, 127 int src_x0, int src_y0, 128 int dst_x0, int dst_y0, 129 int dst_x1, int dst_y1, 130 bool mirror_x, bool mirror_y) 131{ 132 brw_blorp_blit_params params(brw_context(&intel->ctx), 133 src_mt, dst_mt, 134 src_x0, src_y0, 135 dst_x0, dst_y0, 136 dst_x1, dst_y1, 137 mirror_x, mirror_y); 138 brw_blorp_exec(intel, ¶ms); 139} 140 141static void 142do_blorp_blit(struct intel_context *intel, GLbitfield buffer_bit, 143 struct intel_renderbuffer *src_irb, 144 struct intel_renderbuffer *dst_irb, 145 GLint srcX0, GLint srcY0, 146 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1, 147 bool mirror_x, bool mirror_y) 148{ 149 /* Find source/dst miptrees */ 150 struct intel_mipmap_tree *src_mt = find_miptree(buffer_bit, src_irb); 151 struct intel_mipmap_tree *dst_mt = find_miptree(buffer_bit, dst_irb); 152 153 /* Get ready to blit. This includes depth resolving the src and dst 154 * buffers if necessary. 155 */ 156 intel_renderbuffer_resolve_depth(intel, src_irb); 157 intel_renderbuffer_resolve_depth(intel, dst_irb); 158 159 /* Do the blit */ 160 brw_blorp_blit_miptrees(intel, src_mt, dst_mt, 161 srcX0, srcY0, dstX0, dstY0, dstX1, dstY1, 162 mirror_x, mirror_y); 163 164 intel_renderbuffer_set_needs_hiz_resolve(dst_irb); 165 intel_renderbuffer_set_needs_downsample(dst_irb); 166} 167 168 169static bool 170formats_match(GLbitfield buffer_bit, struct intel_renderbuffer *src_irb, 171 struct intel_renderbuffer *dst_irb) 172{ 173 /* Note: don't just check gl_renderbuffer::Format, because in some cases 174 * multiple gl_formats resolve to the same native type in the miptree (for 175 * example MESA_FORMAT_X8_Z24 and MESA_FORMAT_S8_Z24), and we can blit 176 * between those formats. 177 */ 178 return find_miptree(buffer_bit, src_irb)->format == 179 find_miptree(buffer_bit, dst_irb)->format; 180} 181 182 183static bool 184try_blorp_blit(struct intel_context *intel, 185 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1, 186 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1, 187 GLenum filter, GLbitfield buffer_bit) 188{ 189 struct gl_context *ctx = &intel->ctx; 190 191 /* Sync up the state of window system buffers. We need to do this before 192 * we go looking for the buffers. 193 */ 194 intel_prepare_render(intel); 195 196 const struct gl_framebuffer *read_fb = ctx->ReadBuffer; 197 const struct gl_framebuffer *draw_fb = ctx->DrawBuffer; 198 199 /* Detect if the blit needs to be mirrored */ 200 bool mirror_x = false, mirror_y = false; 201 fixup_mirroring(mirror_x, srcX0, srcX1); 202 fixup_mirroring(mirror_x, dstX0, dstX1); 203 fixup_mirroring(mirror_y, srcY0, srcY1); 204 fixup_mirroring(mirror_y, dstY0, dstY1); 205 206 /* Make sure width and height match */ 207 if (srcX1 - srcX0 != dstX1 - dstX0) return false; 208 if (srcY1 - srcY0 != dstY1 - dstY0) return false; 209 210 /* If the destination rectangle needs to be clipped or scissored, do so. 211 */ 212 if (!(clip_or_scissor(mirror_x, srcX0, srcX1, dstX0, dstX1, 213 draw_fb->_Xmin, draw_fb->_Xmax) && 214 clip_or_scissor(mirror_y, srcY0, srcY1, dstY0, dstY1, 215 draw_fb->_Ymin, draw_fb->_Ymax))) { 216 /* Everything got clipped/scissored away, so the blit was successful. */ 217 return true; 218 } 219 220 /* If the source rectangle needs to be clipped or scissored, do so. */ 221 if (!(clip_or_scissor(mirror_x, dstX0, dstX1, srcX0, srcX1, 222 0, read_fb->Width) && 223 clip_or_scissor(mirror_y, dstY0, dstY1, srcY0, srcY1, 224 0, read_fb->Height))) { 225 /* Everything got clipped/scissored away, so the blit was successful. */ 226 return true; 227 } 228 229 /* Account for the fact that in the system framebuffer, the origin is at 230 * the lower left. 231 */ 232 if (_mesa_is_winsys_fbo(read_fb)) { 233 GLint tmp = read_fb->Height - srcY0; 234 srcY0 = read_fb->Height - srcY1; 235 srcY1 = tmp; 236 mirror_y = !mirror_y; 237 } 238 if (_mesa_is_winsys_fbo(draw_fb)) { 239 GLint tmp = draw_fb->Height - dstY0; 240 dstY0 = draw_fb->Height - dstY1; 241 dstY1 = tmp; 242 mirror_y = !mirror_y; 243 } 244 245 /* Find buffers */ 246 struct intel_renderbuffer *src_irb; 247 struct intel_renderbuffer *dst_irb; 248 switch (buffer_bit) { 249 case GL_COLOR_BUFFER_BIT: 250 src_irb = intel_renderbuffer(read_fb->_ColorReadBuffer); 251 for (unsigned i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; ++i) { 252 dst_irb = intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i]); 253 if (dst_irb && !formats_match(buffer_bit, src_irb, dst_irb)) 254 return false; 255 } 256 for (unsigned i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; ++i) { 257 dst_irb = intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i]); 258 do_blorp_blit(intel, buffer_bit, src_irb, dst_irb, srcX0, srcY0, 259 dstX0, dstY0, dstX1, dstY1, mirror_x, mirror_y); 260 } 261 break; 262 case GL_DEPTH_BUFFER_BIT: 263 src_irb = 264 intel_renderbuffer(read_fb->Attachment[BUFFER_DEPTH].Renderbuffer); 265 dst_irb = 266 intel_renderbuffer(draw_fb->Attachment[BUFFER_DEPTH].Renderbuffer); 267 if (!formats_match(buffer_bit, src_irb, dst_irb)) 268 return false; 269 do_blorp_blit(intel, buffer_bit, src_irb, dst_irb, srcX0, srcY0, 270 dstX0, dstY0, dstX1, dstY1, mirror_x, mirror_y); 271 break; 272 case GL_STENCIL_BUFFER_BIT: 273 src_irb = 274 intel_renderbuffer(read_fb->Attachment[BUFFER_STENCIL].Renderbuffer); 275 dst_irb = 276 intel_renderbuffer(draw_fb->Attachment[BUFFER_STENCIL].Renderbuffer); 277 if (!formats_match(buffer_bit, src_irb, dst_irb)) 278 return false; 279 do_blorp_blit(intel, buffer_bit, src_irb, dst_irb, srcX0, srcY0, 280 dstX0, dstY0, dstX1, dstY1, mirror_x, mirror_y); 281 break; 282 default: 283 assert(false); 284 } 285 286 return true; 287} 288 289GLbitfield 290brw_blorp_framebuffer(struct intel_context *intel, 291 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1, 292 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1, 293 GLbitfield mask, GLenum filter) 294{ 295 /* BLORP is not supported before Gen6. */ 296 if (intel->gen < 6) 297 return mask; 298 299 static GLbitfield buffer_bits[] = { 300 GL_COLOR_BUFFER_BIT, 301 GL_DEPTH_BUFFER_BIT, 302 GL_STENCIL_BUFFER_BIT, 303 }; 304 305 for (unsigned int i = 0; i < ARRAY_SIZE(buffer_bits); ++i) { 306 if ((mask & buffer_bits[i]) && 307 try_blorp_blit(intel, 308 srcX0, srcY0, srcX1, srcY1, 309 dstX0, dstY0, dstX1, dstY1, 310 filter, buffer_bits[i])) { 311 mask &= ~buffer_bits[i]; 312 } 313 } 314 315 return mask; 316} 317 318 319/** 320 * Enum to specify the order of arguments in a sampler message 321 */ 322enum sampler_message_arg 323{ 324 SAMPLER_MESSAGE_ARG_U_FLOAT, 325 SAMPLER_MESSAGE_ARG_V_FLOAT, 326 SAMPLER_MESSAGE_ARG_U_INT, 327 SAMPLER_MESSAGE_ARG_V_INT, 328 SAMPLER_MESSAGE_ARG_SI_INT, 329 SAMPLER_MESSAGE_ARG_MCS_INT, 330 SAMPLER_MESSAGE_ARG_ZERO_INT, 331}; 332 333/** 334 * Generator for WM programs used in BLORP blits. 335 * 336 * The bulk of the work done by the WM program is to wrap and unwrap the 337 * coordinate transformations used by the hardware to store surfaces in 338 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the 339 * sample index for a multisampled surface) to a memory offset by the 340 * following formulas: 341 * 342 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S)) 343 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset)) 344 * 345 * For a single-sampled surface, or for a multisampled surface using 346 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity 347 * function: 348 * 349 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0) 350 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0) 351 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S) 352 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S) 353 * 354 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa() 355 * embeds the sample number into bit 1 of the X and Y coordinates: 356 * 357 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0) 358 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1) 359 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1) 360 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S) 361 * where X' = (X & ~0b11) >> 1 | (X & 0b1) 362 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1) 363 * S = (Y & 0b10) | (X & 0b10) >> 1 364 * 365 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa() 366 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of 367 * the Y coordinate: 368 * 369 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0) 370 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1) 371 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1) 372 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S) 373 * where X' = (X & ~0b111) >> 2 | (X & 0b1) 374 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1) 375 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1 376 * 377 * For X tiling, tile() combines together the low-order bits of the X and Y 378 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512 379 * bytes wide and 8 rows high: 380 * 381 * tile(x_tiled, X, Y, S) = A 382 * where A = tile_num << 12 | offset 383 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9) 384 * offset = (Y' & 0b111) << 9 385 * | (X & 0b111111111) 386 * X' = X * cpp 387 * Y' = Y + S * qpitch 388 * detile(x_tiled, A) = (X, Y, S) 389 * where X = X' / cpp 390 * Y = Y' % qpitch 391 * S = Y' / qpitch 392 * Y' = (tile_num / tile_pitch) << 3 393 * | (A & 0b111000000000) >> 9 394 * X' = (tile_num % tile_pitch) << 9 395 * | (A & 0b111111111) 396 * 397 * (In all tiling formulas, cpp is the number of bytes occupied by a single 398 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required 399 * to fill the width of the surface, and qpitch is the spacing (in rows) 400 * between array slices). 401 * 402 * For Y tiling, tile() combines together the low-order bits of the X and Y 403 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128 404 * bytes wide and 32 rows high: 405 * 406 * tile(y_tiled, X, Y, S) = A 407 * where A = tile_num << 12 | offset 408 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7) 409 * offset = (X' & 0b1110000) << 5 410 * | (Y' & 0b11111) << 4 411 * | (X' & 0b1111) 412 * X' = X * cpp 413 * Y' = Y + S * qpitch 414 * detile(y_tiled, A) = (X, Y, S) 415 * where X = X' / cpp 416 * Y = Y' % qpitch 417 * S = Y' / qpitch 418 * Y' = (tile_num / tile_pitch) << 5 419 * | (A & 0b111110000) >> 4 420 * X' = (tile_num % tile_pitch) << 7 421 * | (A & 0b111000000000) >> 5 422 * | (A & 0b1111) 423 * 424 * For W tiling, tile() combines together the low-order bits of the X and Y 425 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64 426 * bytes wide and 64 rows high (note that W tiling is only used for stencil 427 * buffers, which always have cpp = 1 and S=0): 428 * 429 * tile(w_tiled, X, Y, S) = A 430 * where A = tile_num << 12 | offset 431 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6) 432 * offset = (X' & 0b111000) << 6 433 * | (Y' & 0b111100) << 3 434 * | (X' & 0b100) << 2 435 * | (Y' & 0b10) << 2 436 * | (X' & 0b10) << 1 437 * | (Y' & 0b1) << 1 438 * | (X' & 0b1) 439 * X' = X * cpp = X 440 * Y' = Y + S * qpitch 441 * detile(w_tiled, A) = (X, Y, S) 442 * where X = X' / cpp = X' 443 * Y = Y' % qpitch = Y' 444 * S = Y / qpitch = 0 445 * Y' = (tile_num / tile_pitch) << 6 446 * | (A & 0b111100000) >> 3 447 * | (A & 0b1000) >> 2 448 * | (A & 0b10) >> 1 449 * X' = (tile_num % tile_pitch) << 6 450 * | (A & 0b111000000000) >> 6 451 * | (A & 0b10000) >> 2 452 * | (A & 0b100) >> 1 453 * | (A & 0b1) 454 * 455 * Finally, for a non-tiled surface, tile() simply combines together the X and 456 * Y coordinates in the natural way: 457 * 458 * tile(untiled, X, Y, S) = A 459 * where A = Y * pitch + X' 460 * X' = X * cpp 461 * Y' = Y + S * qpitch 462 * detile(untiled, A) = (X, Y, S) 463 * where X = X' / cpp 464 * Y = Y' % qpitch 465 * S = Y' / qpitch 466 * X' = A % pitch 467 * Y' = A / pitch 468 * 469 * (In these formulas, pitch is the number of bytes occupied by a single row 470 * of samples). 471 */ 472class brw_blorp_blit_program 473{ 474public: 475 brw_blorp_blit_program(struct brw_context *brw, 476 const brw_blorp_blit_prog_key *key); 477 ~brw_blorp_blit_program(); 478 479 const GLuint *compile(struct brw_context *brw, GLuint *program_size); 480 481 brw_blorp_prog_data prog_data; 482 483private: 484 void alloc_regs(); 485 void alloc_push_const_regs(int base_reg); 486 void compute_frag_coords(); 487 void translate_tiling(bool old_tiled_w, bool new_tiled_w); 488 void encode_msaa(unsigned num_samples, intel_msaa_layout layout); 489 void decode_msaa(unsigned num_samples, intel_msaa_layout layout); 490 void kill_if_outside_dst_rect(); 491 void translate_dst_to_src(); 492 void single_to_blend(); 493 void manual_blend(unsigned num_samples); 494 void sample(struct brw_reg dst); 495 void texel_fetch(struct brw_reg dst); 496 void mcs_fetch(); 497 void expand_to_32_bits(struct brw_reg src, struct brw_reg dst); 498 void texture_lookup(struct brw_reg dst, GLuint msg_type, 499 const sampler_message_arg *args, int num_args); 500 void render_target_write(); 501 502 /** 503 * Base-2 logarithm of the maximum number of samples that can be blended. 504 */ 505 static const unsigned LOG2_MAX_BLEND_SAMPLES = 3; 506 507 void *mem_ctx; 508 struct brw_context *brw; 509 const brw_blorp_blit_prog_key *key; 510 struct brw_compile func; 511 512 /* Thread dispatch header */ 513 struct brw_reg R0; 514 515 /* Pixel X/Y coordinates (always in R1). */ 516 struct brw_reg R1; 517 518 /* Push constants */ 519 struct brw_reg dst_x0; 520 struct brw_reg dst_x1; 521 struct brw_reg dst_y0; 522 struct brw_reg dst_y1; 523 struct { 524 struct brw_reg multiplier; 525 struct brw_reg offset; 526 } x_transform, y_transform; 527 528 /* Data read from texture (4 vec16's per array element) */ 529 struct brw_reg texture_data[LOG2_MAX_BLEND_SAMPLES + 1]; 530 531 /* Auxiliary storage for the contents of the MCS surface. 532 * 533 * Since the sampler always returns 8 registers worth of data, this is 8 534 * registers wide, even though we only use the first 2 registers of it. 535 */ 536 struct brw_reg mcs_data; 537 538 /* X coordinates. We have two of them so that we can perform coordinate 539 * transformations easily. 540 */ 541 struct brw_reg x_coords[2]; 542 543 /* Y coordinates. We have two of them so that we can perform coordinate 544 * transformations easily. 545 */ 546 struct brw_reg y_coords[2]; 547 548 /* Which element of x_coords and y_coords is currently in use. 549 */ 550 int xy_coord_index; 551 552 /* True if, at the point in the program currently being compiled, the 553 * sample index is known to be zero. 554 */ 555 bool s_is_zero; 556 557 /* Register storing the sample index when s_is_zero is false. */ 558 struct brw_reg sample_index; 559 560 /* Temporaries */ 561 struct brw_reg t1; 562 struct brw_reg t2; 563 564 /* MRF used for sampling and render target writes */ 565 GLuint base_mrf; 566}; 567 568brw_blorp_blit_program::brw_blorp_blit_program( 569 struct brw_context *brw, 570 const brw_blorp_blit_prog_key *key) 571 : mem_ctx(ralloc_context(NULL)), 572 brw(brw), 573 key(key) 574{ 575 brw_init_compile(brw, &func, mem_ctx); 576} 577 578brw_blorp_blit_program::~brw_blorp_blit_program() 579{ 580 ralloc_free(mem_ctx); 581} 582 583const GLuint * 584brw_blorp_blit_program::compile(struct brw_context *brw, 585 GLuint *program_size) 586{ 587 /* Sanity checks */ 588 if (key->dst_tiled_w && key->rt_samples > 0) { 589 /* If the destination image is W tiled and multisampled, then the thread 590 * must be dispatched once per sample, not once per pixel. This is 591 * necessary because after conversion between W and Y tiling, there's no 592 * guarantee that all samples corresponding to a single pixel will still 593 * be together. 594 */ 595 assert(key->persample_msaa_dispatch); 596 } 597 598 if (key->blend) { 599 /* We are blending, which means we won't have an opportunity to 600 * translate the tiling and sample count for the texture surface. So 601 * the surface state for the texture must be configured with the correct 602 * tiling and sample count. 603 */ 604 assert(!key->src_tiled_w); 605 assert(key->tex_samples == key->src_samples); 606 assert(key->tex_layout == key->src_layout); 607 assert(key->tex_samples > 0); 608 } 609 610 if (key->persample_msaa_dispatch) { 611 /* It only makes sense to do persample dispatch if the render target is 612 * configured as multisampled. 613 */ 614 assert(key->rt_samples > 0); 615 } 616 617 /* Make sure layout is consistent with sample count */ 618 assert((key->tex_layout == INTEL_MSAA_LAYOUT_NONE) == 619 (key->tex_samples == 0)); 620 assert((key->rt_layout == INTEL_MSAA_LAYOUT_NONE) == 621 (key->rt_samples == 0)); 622 assert((key->src_layout == INTEL_MSAA_LAYOUT_NONE) == 623 (key->src_samples == 0)); 624 assert((key->dst_layout == INTEL_MSAA_LAYOUT_NONE) == 625 (key->dst_samples == 0)); 626 627 /* Set up prog_data */ 628 memset(&prog_data, 0, sizeof(prog_data)); 629 prog_data.persample_msaa_dispatch = key->persample_msaa_dispatch; 630 631 brw_set_compression_control(&func, BRW_COMPRESSION_NONE); 632 633 alloc_regs(); 634 compute_frag_coords(); 635 636 /* Render target and texture hardware don't support W tiling. */ 637 const bool rt_tiled_w = false; 638 const bool tex_tiled_w = false; 639 640 /* The address that data will be written to is determined by the 641 * coordinates supplied to the WM thread and the tiling and sample count of 642 * the render target, according to the formula: 643 * 644 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset)) 645 * 646 * If the actual tiling and sample count of the destination surface are not 647 * the same as the configuration of the render target, then these 648 * coordinates are wrong and we have to adjust them to compensate for the 649 * difference. 650 */ 651 if (rt_tiled_w != key->dst_tiled_w || 652 key->rt_samples != key->dst_samples || 653 key->rt_layout != key->dst_layout) { 654 encode_msaa(key->rt_samples, key->rt_layout); 655 /* Now (X, Y, S) = detile(rt_tiling, offset) */ 656 translate_tiling(rt_tiled_w, key->dst_tiled_w); 657 /* Now (X, Y, S) = detile(dst_tiling, offset) */ 658 decode_msaa(key->dst_samples, key->dst_layout); 659 } 660 661 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)). 662 * 663 * That is: X, Y and S now contain the true coordinates and sample index of 664 * the data that the WM thread should output. 665 * 666 * If we need to kill pixels that are outside the destination rectangle, 667 * now is the time to do it. 668 */ 669 670 if (key->use_kill) 671 kill_if_outside_dst_rect(); 672 673 /* Next, apply a translation to obtain coordinates in the source image. */ 674 translate_dst_to_src(); 675 676 /* If the source image is not multisampled, then we want to fetch sample 677 * number 0, because that's the only sample there is. 678 */ 679 if (key->src_samples == 0) 680 s_is_zero = true; 681 682 /* X, Y, and S are now the coordinates of the pixel in the source image 683 * that we want to texture from. Exception: if we are blending, then S is 684 * irrelevant, because we are going to fetch all samples. 685 */ 686 if (key->blend) { 687 if (brw->intel.gen == 6) { 688 /* Gen6 hardware an automatically blend using the SAMPLE message */ 689 single_to_blend(); 690 sample(texture_data[0]); 691 } else { 692 /* Gen7+ hardware doesn't automaticaly blend. */ 693 manual_blend(key->src_samples); 694 } 695 } else { 696 /* We aren't blending, which means we just want to fetch a single sample 697 * from the source surface. The address that we want to fetch from is 698 * related to the X, Y and S values according to the formula: 699 * 700 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)). 701 * 702 * If the actual tiling and sample count of the source surface are not 703 * the same as the configuration of the texture, then we need to adjust 704 * the coordinates to compensate for the difference. 705 */ 706 if (tex_tiled_w != key->src_tiled_w || 707 key->tex_samples != key->src_samples || 708 key->tex_layout != key->src_layout) { 709 encode_msaa(key->src_samples, key->src_layout); 710 /* Now (X, Y, S) = detile(src_tiling, offset) */ 711 translate_tiling(key->src_tiled_w, tex_tiled_w); 712 /* Now (X, Y, S) = detile(tex_tiling, offset) */ 713 decode_msaa(key->tex_samples, key->tex_layout); 714 } 715 716 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)). 717 * 718 * In other words: X, Y, and S now contain values which, when passed to 719 * the texturing unit, will cause data to be read from the correct 720 * memory location. So we can fetch the texel now. 721 */ 722 if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS) 723 mcs_fetch(); 724 texel_fetch(texture_data[0]); 725 } 726 727 /* Finally, write the fetched (or blended) value to the render target and 728 * terminate the thread. 729 */ 730 render_target_write(); 731 return brw_get_program(&func, program_size); 732} 733 734void 735brw_blorp_blit_program::alloc_push_const_regs(int base_reg) 736{ 737#define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name) 738#define ALLOC_REG(name) \ 739 this->name = \ 740 brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, base_reg, CONST_LOC(name) / 2) 741 742 ALLOC_REG(dst_x0); 743 ALLOC_REG(dst_x1); 744 ALLOC_REG(dst_y0); 745 ALLOC_REG(dst_y1); 746 ALLOC_REG(x_transform.multiplier); 747 ALLOC_REG(x_transform.offset); 748 ALLOC_REG(y_transform.multiplier); 749 ALLOC_REG(y_transform.offset); 750#undef CONST_LOC 751#undef ALLOC_REG 752} 753 754void 755brw_blorp_blit_program::alloc_regs() 756{ 757 int reg = 0; 758 this->R0 = retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW); 759 this->R1 = retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW); 760 prog_data.first_curbe_grf = reg; 761 alloc_push_const_regs(reg); 762 reg += BRW_BLORP_NUM_PUSH_CONST_REGS; 763 for (unsigned i = 0; i < ARRAY_SIZE(texture_data); ++i) { 764 this->texture_data[i] = 765 retype(vec16(brw_vec8_grf(reg, 0)), key->texture_data_type); 766 reg += 8; 767 } 768 this->mcs_data = 769 retype(brw_vec8_grf(reg, 0), BRW_REGISTER_TYPE_UD); reg += 8; 770 for (int i = 0; i < 2; ++i) { 771 this->x_coords[i] 772 = vec16(retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW)); 773 this->y_coords[i] 774 = vec16(retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW)); 775 } 776 this->xy_coord_index = 0; 777 this->sample_index 778 = vec16(retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW)); 779 this->t1 = vec16(retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW)); 780 this->t2 = vec16(retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW)); 781 782 /* Make sure we didn't run out of registers */ 783 assert(reg <= GEN7_MRF_HACK_START); 784 785 int mrf = 2; 786 this->base_mrf = mrf; 787} 788 789/* In the code that follows, X and Y can be used to quickly refer to the 790 * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y 791 * prime") to the inactive elements. 792 * 793 * S can be used to quickly refer to sample_index. 794 */ 795#define X x_coords[xy_coord_index] 796#define Y y_coords[xy_coord_index] 797#define Xp x_coords[!xy_coord_index] 798#define Yp y_coords[!xy_coord_index] 799#define S sample_index 800 801/* Quickly swap the roles of (X, Y) and (Xp, Yp). Saves us from having to do 802 * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation. 803 */ 804#define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index; 805 806/** 807 * Emit code to compute the X and Y coordinates of the pixels being rendered 808 * by this WM invocation. 809 * 810 * Assuming the render target is set up for Y tiling, these (X, Y) values are 811 * related to the address offset where outputs will be written by the formula: 812 * 813 * (X, Y, S) = decode_msaa(detile(offset)). 814 * 815 * (See brw_blorp_blit_program). 816 */ 817void 818brw_blorp_blit_program::compute_frag_coords() 819{ 820 /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0) 821 * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4) 822 * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8) 823 * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12) 824 * 825 * Pixels within a subspan are laid out in this arrangement: 826 * 0 1 827 * 2 3 828 * 829 * So, to compute the coordinates of each pixel, we need to read every 2nd 830 * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value 831 * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4). 832 * In other words, the data we want to access is R1.4<2;4,0>UW. 833 * 834 * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the 835 * result, since pixels n+1 and n+3 are in the right half of the subspan. 836 */ 837 brw_ADD(&func, X, stride(suboffset(R1, 4), 2, 4, 0), brw_imm_v(0x10101010)); 838 839 /* Similarly, Y coordinates for subspans come from R1.2[31:16] through 840 * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th 841 * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of 842 * R1.4<2;4,0>UW). 843 * 844 * And we need to add the repeating sequence (0, 0, 1, 1, ...), since 845 * pixels n+2 and n+3 are in the bottom half of the subspan. 846 */ 847 brw_ADD(&func, Y, stride(suboffset(R1, 5), 2, 4, 0), brw_imm_v(0x11001100)); 848 849 if (key->persample_msaa_dispatch) { 850 switch (key->rt_samples) { 851 case 4: 852 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 4. 853 * Therefore, subspan 0 will represent sample 0, subspan 1 will 854 * represent sample 1, and so on. 855 * 856 * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1, 857 * 1, 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to 858 * populate a temporary variable with the sequence (0, 1, 2, 3), and 859 * then copy from it using vstride=1, width=4, hstride=0. 860 */ 861 brw_MOV(&func, t1, brw_imm_v(0x3210)); 862 brw_MOV(&func, S, stride(t1, 1, 4, 0)); 863 break; 864 case 8: { 865 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 8. 866 * Therefore, subspan 0 will represent sample N (where N is 0 or 4), 867 * subspan 1 will represent sample 1, and so on. We can find the 868 * value of N by looking at R0.0 bits 7:6 ("Starting Sample Pair 869 * Index") and multiplying by two (since samples are always delivered 870 * in pairs). That is, we compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 871 * 0xc0) >> 5. 872 * 873 * Then we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 874 * 2, 2, 2, 3, 3, 3, 3), which we compute by populating a temporary 875 * variable with the sequence (0, 1, 2, 3), and then reading from it 876 * using vstride=1, width=4, hstride=0. 877 */ 878 struct brw_reg t1_ud1 = vec1(retype(t1, BRW_REGISTER_TYPE_UD)); 879 struct brw_reg r0_ud1 = vec1(retype(R0, BRW_REGISTER_TYPE_UD)); 880 brw_AND(&func, t1_ud1, r0_ud1, brw_imm_ud(0xc0)); 881 brw_SHR(&func, t1_ud1, t1_ud1, brw_imm_ud(5)); 882 brw_MOV(&func, t2, brw_imm_v(0x3210)); 883 brw_ADD(&func, S, retype(t1_ud1, BRW_REGISTER_TYPE_UW), 884 stride(t2, 1, 4, 0)); 885 break; 886 } 887 default: 888 assert(!"Unrecognized sample count in " 889 "brw_blorp_blit_program::compute_frag_coords()"); 890 break; 891 } 892 s_is_zero = false; 893 } else { 894 /* Either the destination surface is single-sampled, or the WM will be 895 * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch 896 * per pixel). In either case, it's not meaningful to compute a sample 897 * value. Just set it to 0. 898 */ 899 s_is_zero = true; 900 } 901} 902 903/** 904 * Emit code to compensate for the difference between Y and W tiling. 905 * 906 * This code modifies the X and Y coordinates according to the formula: 907 * 908 * (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S)) 909 * 910 * (See brw_blorp_blit_program). 911 * 912 * It can only translate between W and Y tiling, so new_tiling and old_tiling 913 * are booleans where true represents W tiling and false represents Y tiling. 914 */ 915void 916brw_blorp_blit_program::translate_tiling(bool old_tiled_w, bool new_tiled_w) 917{ 918 if (old_tiled_w == new_tiled_w) 919 return; 920 921 /* In the code that follows, we can safely assume that S = 0, because W 922 * tiling formats always use IMS layout. 923 */ 924 assert(s_is_zero); 925 926 if (new_tiled_w) { 927 /* Given X and Y coordinates that describe an address using Y tiling, 928 * translate to the X and Y coordinates that describe the same address 929 * using W tiling. 930 * 931 * If we break down the low order bits of X and Y, using a 932 * single letter to represent each low-order bit: 933 * 934 * X = A << 7 | 0bBCDEFGH 935 * Y = J << 5 | 0bKLMNP (1) 936 * 937 * Then we can apply the Y tiling formula to see the memory offset being 938 * addressed: 939 * 940 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2) 941 * 942 * If we apply the W detiling formula to this memory location, that the 943 * corresponding X' and Y' coordinates are: 944 * 945 * X' = A << 6 | 0bBCDPFH (3) 946 * Y' = J << 6 | 0bKLMNEG 947 * 948 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'), 949 * we need to make the following computation: 950 * 951 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4) 952 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1 953 */ 954 brw_AND(&func, t1, X, brw_imm_uw(0xfff4)); /* X & ~0b1011 */ 955 brw_SHR(&func, t1, t1, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */ 956 brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */ 957 brw_SHL(&func, t2, t2, brw_imm_uw(2)); /* (Y & 0b1) << 2 */ 958 brw_OR(&func, t1, t1, t2); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */ 959 brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */ 960 brw_OR(&func, Xp, t1, t2); 961 brw_AND(&func, t1, Y, brw_imm_uw(0xfffe)); /* Y & ~0b1 */ 962 brw_SHL(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */ 963 brw_AND(&func, t2, X, brw_imm_uw(8)); /* X & 0b1000 */ 964 brw_SHR(&func, t2, t2, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */ 965 brw_OR(&func, t1, t1, t2); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */ 966 brw_AND(&func, t2, X, brw_imm_uw(2)); /* X & 0b10 */ 967 brw_SHR(&func, t2, t2, brw_imm_uw(1)); /* (X & 0b10) >> 1 */ 968 brw_OR(&func, Yp, t1, t2); 969 SWAP_XY_AND_XPYP(); 970 } else { 971 /* Applying the same logic as above, but in reverse, we obtain the 972 * formulas: 973 * 974 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1 975 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2 976 */ 977 brw_AND(&func, t1, X, brw_imm_uw(0xfffa)); /* X & ~0b101 */ 978 brw_SHL(&func, t1, t1, brw_imm_uw(1)); /* (X & ~0b101) << 1 */ 979 brw_AND(&func, t2, Y, brw_imm_uw(2)); /* Y & 0b10 */ 980 brw_SHL(&func, t2, t2, brw_imm_uw(2)); /* (Y & 0b10) << 2 */ 981 brw_OR(&func, t1, t1, t2); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */ 982 brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */ 983 brw_SHL(&func, t2, t2, brw_imm_uw(1)); /* (Y & 0b1) << 1 */ 984 brw_OR(&func, t1, t1, t2); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 985 | (Y & 0b1) << 1 */ 986 brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */ 987 brw_OR(&func, Xp, t1, t2); 988 brw_AND(&func, t1, Y, brw_imm_uw(0xfffc)); /* Y & ~0b11 */ 989 brw_SHR(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */ 990 brw_AND(&func, t2, X, brw_imm_uw(4)); /* X & 0b100 */ 991 brw_SHR(&func, t2, t2, brw_imm_uw(2)); /* (X & 0b100) >> 2 */ 992 brw_OR(&func, Yp, t1, t2); 993 SWAP_XY_AND_XPYP(); 994 } 995} 996 997/** 998 * Emit code to compensate for the difference between MSAA and non-MSAA 999 * surfaces. 1000 * 1001 * This code modifies the X and Y coordinates according to the formula: 1002 * 1003 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S) 1004 * 1005 * (See brw_blorp_blit_program). 1006 */ 1007void 1008brw_blorp_blit_program::encode_msaa(unsigned num_samples, 1009 intel_msaa_layout layout) 1010{ 1011 switch (layout) { 1012 case INTEL_MSAA_LAYOUT_NONE: 1013 /* No translation necessary, and S should already be zero. */ 1014 assert(s_is_zero); 1015 break; 1016 case INTEL_MSAA_LAYOUT_CMS: 1017 /* We can't compensate for compressed layout since at this point in the 1018 * program we haven't read from the MCS buffer. 1019 */ 1020 assert(!"Bad layout in encode_msaa"); 1021 break; 1022 case INTEL_MSAA_LAYOUT_UMS: 1023 /* No translation necessary. */ 1024 break; 1025 case INTEL_MSAA_LAYOUT_IMS: 1026 switch (num_samples) { 1027 case 4: 1028 /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0) 1029 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1) 1030 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1) 1031 */ 1032 brw_AND(&func, t1, X, brw_imm_uw(0xfffe)); /* X & ~0b1 */ 1033 if (!s_is_zero) { 1034 brw_AND(&func, t2, S, brw_imm_uw(1)); /* S & 0b1 */ 1035 brw_OR(&func, t1, t1, t2); /* (X & ~0b1) | (S & 0b1) */ 1036 } 1037 brw_SHL(&func, t1, t1, brw_imm_uw(1)); /* (X & ~0b1) << 1 1038 | (S & 0b1) << 1 */ 1039 brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */ 1040 brw_OR(&func, Xp, t1, t2); 1041 brw_AND(&func, t1, Y, brw_imm_uw(0xfffe)); /* Y & ~0b1 */ 1042 brw_SHL(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */ 1043 if (!s_is_zero) { 1044 brw_AND(&func, t2, S, brw_imm_uw(2)); /* S & 0b10 */ 1045 brw_OR(&func, t1, t1, t2); /* (Y & ~0b1) << 1 | (S & 0b10) */ 1046 } 1047 brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */ 1048 brw_OR(&func, Yp, t1, t2); 1049 break; 1050 case 8: 1051 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0) 1052 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 1053 * | (X & 0b1) 1054 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1) 1055 */ 1056 brw_AND(&func, t1, X, brw_imm_uw(0xfffe)); /* X & ~0b1 */ 1057 brw_SHL(&func, t1, t1, brw_imm_uw(2)); /* (X & ~0b1) << 2 */ 1058 if (!s_is_zero) { 1059 brw_AND(&func, t2, S, brw_imm_uw(4)); /* S & 0b100 */ 1060 brw_OR(&func, t1, t1, t2); /* (X & ~0b1) << 2 | (S & 0b100) */ 1061 brw_AND(&func, t2, S, brw_imm_uw(1)); /* S & 0b1 */ 1062 brw_SHL(&func, t2, t2, brw_imm_uw(1)); /* (S & 0b1) << 1 */ 1063 brw_OR(&func, t1, t1, t2); /* (X & ~0b1) << 2 | (S & 0b100) 1064 | (S & 0b1) << 1 */ 1065 } 1066 brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */ 1067 brw_OR(&func, Xp, t1, t2); 1068 brw_AND(&func, t1, Y, brw_imm_uw(0xfffe)); /* Y & ~0b1 */ 1069 brw_SHL(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */ 1070 if (!s_is_zero) { 1071 brw_AND(&func, t2, S, brw_imm_uw(2)); /* S & 0b10 */ 1072 brw_OR(&func, t1, t1, t2); /* (Y & ~0b1) << 1 | (S & 0b10) */ 1073 } 1074 brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */ 1075 brw_OR(&func, Yp, t1, t2); 1076 break; 1077 } 1078 SWAP_XY_AND_XPYP(); 1079 s_is_zero = true; 1080 break; 1081 } 1082} 1083 1084/** 1085 * Emit code to compensate for the difference between MSAA and non-MSAA 1086 * surfaces. 1087 * 1088 * This code modifies the X and Y coordinates according to the formula: 1089 * 1090 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S) 1091 * 1092 * (See brw_blorp_blit_program). 1093 */ 1094void 1095brw_blorp_blit_program::decode_msaa(unsigned num_samples, 1096 intel_msaa_layout layout) 1097{ 1098 switch (layout) { 1099 case INTEL_MSAA_LAYOUT_NONE: 1100 /* No translation necessary, and S should already be zero. */ 1101 assert(s_is_zero); 1102 break; 1103 case INTEL_MSAA_LAYOUT_CMS: 1104 /* We can't compensate for compressed layout since at this point in the 1105 * program we don't have access to the MCS buffer. 1106 */ 1107 assert(!"Bad layout in encode_msaa"); 1108 break; 1109 case INTEL_MSAA_LAYOUT_UMS: 1110 /* No translation necessary. */ 1111 break; 1112 case INTEL_MSAA_LAYOUT_IMS: 1113 assert(s_is_zero); 1114 switch (num_samples) { 1115 case 4: 1116 /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S) 1117 * where X' = (X & ~0b11) >> 1 | (X & 0b1) 1118 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1) 1119 * S = (Y & 0b10) | (X & 0b10) >> 1 1120 */ 1121 brw_AND(&func, t1, X, brw_imm_uw(0xfffc)); /* X & ~0b11 */ 1122 brw_SHR(&func, t1, t1, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */ 1123 brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */ 1124 brw_OR(&func, Xp, t1, t2); 1125 brw_AND(&func, t1, Y, brw_imm_uw(0xfffc)); /* Y & ~0b11 */ 1126 brw_SHR(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */ 1127 brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */ 1128 brw_OR(&func, Yp, t1, t2); 1129 brw_AND(&func, t1, Y, brw_imm_uw(2)); /* Y & 0b10 */ 1130 brw_AND(&func, t2, X, brw_imm_uw(2)); /* X & 0b10 */ 1131 brw_SHR(&func, t2, t2, brw_imm_uw(1)); /* (X & 0b10) >> 1 */ 1132 brw_OR(&func, S, t1, t2); 1133 break; 1134 case 8: 1135 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S) 1136 * where X' = (X & ~0b111) >> 2 | (X & 0b1) 1137 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1) 1138 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1 1139 */ 1140 brw_AND(&func, t1, X, brw_imm_uw(0xfff8)); /* X & ~0b111 */ 1141 brw_SHR(&func, t1, t1, brw_imm_uw(2)); /* (X & ~0b111) >> 2 */ 1142 brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */ 1143 brw_OR(&func, Xp, t1, t2); 1144 brw_AND(&func, t1, Y, brw_imm_uw(0xfffc)); /* Y & ~0b11 */ 1145 brw_SHR(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */ 1146 brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */ 1147 brw_OR(&func, Yp, t1, t2); 1148 brw_AND(&func, t1, X, brw_imm_uw(4)); /* X & 0b100 */ 1149 brw_AND(&func, t2, Y, brw_imm_uw(2)); /* Y & 0b10 */ 1150 brw_OR(&func, t1, t1, t2); /* (X & 0b100) | (Y & 0b10) */ 1151 brw_AND(&func, t2, X, brw_imm_uw(2)); /* X & 0b10 */ 1152 brw_SHR(&func, t2, t2, brw_imm_uw(1)); /* (X & 0b10) >> 1 */ 1153 brw_OR(&func, S, t1, t2); 1154 break; 1155 } 1156 s_is_zero = false; 1157 SWAP_XY_AND_XPYP(); 1158 break; 1159 } 1160} 1161 1162/** 1163 * Emit code that kills pixels whose X and Y coordinates are outside the 1164 * boundary of the rectangle defined by the push constants (dst_x0, dst_y0, 1165 * dst_x1, dst_y1). 1166 */ 1167void 1168brw_blorp_blit_program::kill_if_outside_dst_rect() 1169{ 1170 struct brw_reg f0 = brw_flag_reg(); 1171 struct brw_reg g1 = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW); 1172 struct brw_reg null16 = vec16(retype(brw_null_reg(), BRW_REGISTER_TYPE_UW)); 1173 1174 brw_CMP(&func, null16, BRW_CONDITIONAL_GE, X, dst_x0); 1175 brw_CMP(&func, null16, BRW_CONDITIONAL_GE, Y, dst_y0); 1176 brw_CMP(&func, null16, BRW_CONDITIONAL_L, X, dst_x1); 1177 brw_CMP(&func, null16, BRW_CONDITIONAL_L, Y, dst_y1); 1178 1179 brw_set_predicate_control(&func, BRW_PREDICATE_NONE); 1180 brw_push_insn_state(&func); 1181 brw_set_mask_control(&func, BRW_MASK_DISABLE); 1182 brw_AND(&func, g1, f0, g1); 1183 brw_pop_insn_state(&func); 1184} 1185 1186/** 1187 * Emit code to translate from destination (X, Y) coordinates to source (X, Y) 1188 * coordinates. 1189 */ 1190void 1191brw_blorp_blit_program::translate_dst_to_src() 1192{ 1193 brw_MUL(&func, Xp, X, x_transform.multiplier); 1194 brw_MUL(&func, Yp, Y, y_transform.multiplier); 1195 brw_ADD(&func, Xp, Xp, x_transform.offset); 1196 brw_ADD(&func, Yp, Yp, y_transform.offset); 1197 SWAP_XY_AND_XPYP(); 1198} 1199 1200/** 1201 * Emit code to transform the X and Y coordinates as needed for blending 1202 * together the different samples in an MSAA texture. 1203 */ 1204void 1205brw_blorp_blit_program::single_to_blend() 1206{ 1207 /* When looking up samples in an MSAA texture using the SAMPLE message, 1208 * Gen6 requires the texture coordinates to be odd integers (so that they 1209 * correspond to the center of a 2x2 block representing the four samples 1210 * that maxe up a pixel). So we need to multiply our X and Y coordinates 1211 * each by 2 and then add 1. 1212 */ 1213 brw_SHL(&func, t1, X, brw_imm_w(1)); 1214 brw_SHL(&func, t2, Y, brw_imm_w(1)); 1215 brw_ADD(&func, Xp, t1, brw_imm_w(1)); 1216 brw_ADD(&func, Yp, t2, brw_imm_w(1)); 1217 SWAP_XY_AND_XPYP(); 1218} 1219 1220 1221/** 1222 * Count the number of trailing 1 bits in the given value. For example: 1223 * 1224 * count_trailing_one_bits(0) == 0 1225 * count_trailing_one_bits(7) == 3 1226 * count_trailing_one_bits(11) == 2 1227 */ 1228inline int count_trailing_one_bits(unsigned value) 1229{ 1230#if defined(__GNUC__) && ((__GNUC__ * 100 + __GNUC_MINOR__) >= 304) /* gcc 3.4 or later */ 1231 return __builtin_ctz(~value); 1232#else 1233 return _mesa_bitcount(value & ~(value + 1)); 1234#endif 1235} 1236 1237 1238void 1239brw_blorp_blit_program::manual_blend(unsigned num_samples) 1240{ 1241 if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS) 1242 mcs_fetch(); 1243 1244 /* We add together samples using a binary tree structure, e.g. for 4x MSAA: 1245 * 1246 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4 1247 * 1248 * This ensures that when all samples have the same value, no numerical 1249 * precision is lost, since each addition operation always adds two equal 1250 * values, and summing two equal floating point values does not lose 1251 * precision. 1252 * 1253 * We perform this computation by treating the texture_data array as a 1254 * stack and performing the following operations: 1255 * 1256 * - push sample 0 onto stack 1257 * - push sample 1 onto stack 1258 * - add top two stack entries 1259 * - push sample 2 onto stack 1260 * - push sample 3 onto stack 1261 * - add top two stack entries 1262 * - add top two stack entries 1263 * - divide top stack entry by 4 1264 * 1265 * Note that after pushing sample i onto the stack, the number of add 1266 * operations we do is equal to the number of trailing 1 bits in i. This 1267 * works provided the total number of samples is a power of two, which it 1268 * always is for i965. 1269 * 1270 * For integer formats, we replace the add operations with average 1271 * operations and skip the final division. 1272 */ 1273 typedef struct brw_instruction *(*brw_op2_ptr)(struct brw_compile *, 1274 struct brw_reg, 1275 struct brw_reg, 1276 struct brw_reg); 1277 brw_op2_ptr combine_op = 1278 key->texture_data_type == BRW_REGISTER_TYPE_F ? brw_ADD : brw_AVG; 1279 unsigned stack_depth = 0; 1280 for (unsigned i = 0; i < num_samples; ++i) { 1281 assert(stack_depth == _mesa_bitcount(i)); /* Loop invariant */ 1282 1283 /* Push sample i onto the stack */ 1284 assert(stack_depth < ARRAY_SIZE(texture_data)); 1285 if (i == 0) { 1286 s_is_zero = true; 1287 } else { 1288 s_is_zero = false; 1289 brw_MOV(&func, S, brw_imm_uw(i)); 1290 } 1291 texel_fetch(texture_data[stack_depth++]); 1292 1293 if (i == 0 && key->tex_layout == INTEL_MSAA_LAYOUT_CMS) { 1294 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface) 1295 * suggests an optimization: 1296 * 1297 * "A simple optimization with probable large return in 1298 * performance is to compare the MCS value to zero (indicating 1299 * all samples are on sample slice 0), and sample only from 1300 * sample slice 0 using ld2dss if MCS is zero." 1301 * 1302 * Note that in the case where the MCS value is zero, sampling from 1303 * sample slice 0 using ld2dss and sampling from sample 0 using 1304 * ld2dms are equivalent (since all samples are on sample slice 0). 1305 * Since we have already sampled from sample 0, all we need to do is 1306 * skip the remaining fetches and averaging if MCS is zero. 1307 */ 1308 brw_CMP(&func, vec16(brw_null_reg()), BRW_CONDITIONAL_NZ, 1309 mcs_data, brw_imm_ud(0)); 1310 brw_IF(&func, BRW_EXECUTE_16); 1311 } 1312 1313 /* Do count_trailing_one_bits(i) times */ 1314 for (int j = count_trailing_one_bits(i); j-- > 0; ) { 1315 assert(stack_depth >= 2); 1316 --stack_depth; 1317 1318 /* TODO: should use a smaller loop bound for non_RGBA formats */ 1319 for (int k = 0; k < 4; ++k) { 1320 combine_op(&func, offset(texture_data[stack_depth - 1], 2*k), 1321 offset(vec8(texture_data[stack_depth - 1]), 2*k), 1322 offset(vec8(texture_data[stack_depth]), 2*k)); 1323 } 1324 } 1325 } 1326 1327 /* We should have just 1 sample on the stack now. */ 1328 assert(stack_depth == 1); 1329 1330 if (key->texture_data_type == BRW_REGISTER_TYPE_F) { 1331 /* Scale the result down by a factor of num_samples */ 1332 /* TODO: should use a smaller loop bound for non-RGBA formats */ 1333 for (int j = 0; j < 4; ++j) { 1334 brw_MUL(&func, offset(texture_data[0], 2*j), 1335 offset(vec8(texture_data[0]), 2*j), 1336 brw_imm_f(1.0/num_samples)); 1337 } 1338 } 1339 1340 if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS) 1341 brw_ENDIF(&func); 1342} 1343 1344/** 1345 * Emit code to look up a value in the texture using the SAMPLE message (which 1346 * does blending of MSAA surfaces). 1347 */ 1348void 1349brw_blorp_blit_program::sample(struct brw_reg dst) 1350{ 1351 static const sampler_message_arg args[2] = { 1352 SAMPLER_MESSAGE_ARG_U_FLOAT, 1353 SAMPLER_MESSAGE_ARG_V_FLOAT 1354 }; 1355 1356 texture_lookup(dst, GEN5_SAMPLER_MESSAGE_SAMPLE, args, ARRAY_SIZE(args)); 1357} 1358 1359/** 1360 * Emit code to look up a value in the texture using the SAMPLE_LD message 1361 * (which does a simple texel fetch). 1362 */ 1363void 1364brw_blorp_blit_program::texel_fetch(struct brw_reg dst) 1365{ 1366 static const sampler_message_arg gen6_args[5] = { 1367 SAMPLER_MESSAGE_ARG_U_INT, 1368 SAMPLER_MESSAGE_ARG_V_INT, 1369 SAMPLER_MESSAGE_ARG_ZERO_INT, /* R */ 1370 SAMPLER_MESSAGE_ARG_ZERO_INT, /* LOD */ 1371 SAMPLER_MESSAGE_ARG_SI_INT 1372 }; 1373 static const sampler_message_arg gen7_ld_args[3] = { 1374 SAMPLER_MESSAGE_ARG_U_INT, 1375 SAMPLER_MESSAGE_ARG_ZERO_INT, /* LOD */ 1376 SAMPLER_MESSAGE_ARG_V_INT 1377 }; 1378 static const sampler_message_arg gen7_ld2dss_args[3] = { 1379 SAMPLER_MESSAGE_ARG_SI_INT, 1380 SAMPLER_MESSAGE_ARG_U_INT, 1381 SAMPLER_MESSAGE_ARG_V_INT 1382 }; 1383 static const sampler_message_arg gen7_ld2dms_args[4] = { 1384 SAMPLER_MESSAGE_ARG_SI_INT, 1385 SAMPLER_MESSAGE_ARG_MCS_INT, 1386 SAMPLER_MESSAGE_ARG_U_INT, 1387 SAMPLER_MESSAGE_ARG_V_INT 1388 }; 1389 1390 switch (brw->intel.gen) { 1391 case 6: 1392 texture_lookup(dst, GEN5_SAMPLER_MESSAGE_SAMPLE_LD, gen6_args, 1393 s_is_zero ? 2 : 5); 1394 break; 1395 case 7: 1396 switch (key->tex_layout) { 1397 case INTEL_MSAA_LAYOUT_IMS: 1398 /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage 1399 * Format): 1400 * 1401 * If this field is MSFMT_DEPTH_STENCIL 1402 * [a.k.a. INTEL_MSAA_LAYOUT_IMS], the only sampling engine 1403 * messages allowed are "ld2dms", "resinfo", and "sampleinfo". 1404 * 1405 * So fall through to emit the same message as we use for 1406 * INTEL_MSAA_LAYOUT_CMS. 1407 */ 1408 case INTEL_MSAA_LAYOUT_CMS: 1409 texture_lookup(dst, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS, 1410 gen7_ld2dms_args, ARRAY_SIZE(gen7_ld2dms_args)); 1411 break; 1412 case INTEL_MSAA_LAYOUT_UMS: 1413 texture_lookup(dst, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS, 1414 gen7_ld2dss_args, ARRAY_SIZE(gen7_ld2dss_args)); 1415 break; 1416 case INTEL_MSAA_LAYOUT_NONE: 1417 assert(s_is_zero); 1418 texture_lookup(dst, GEN5_SAMPLER_MESSAGE_SAMPLE_LD, gen7_ld_args, 1419 ARRAY_SIZE(gen7_ld_args)); 1420 break; 1421 } 1422 break; 1423 default: 1424 assert(!"Should not get here."); 1425 break; 1426 }; 1427} 1428 1429void 1430brw_blorp_blit_program::mcs_fetch() 1431{ 1432 static const sampler_message_arg gen7_ld_mcs_args[2] = { 1433 SAMPLER_MESSAGE_ARG_U_INT, 1434 SAMPLER_MESSAGE_ARG_V_INT 1435 }; 1436 texture_lookup(vec16(mcs_data), GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS, 1437 gen7_ld_mcs_args, ARRAY_SIZE(gen7_ld_mcs_args)); 1438} 1439 1440void 1441brw_blorp_blit_program::expand_to_32_bits(struct brw_reg src, 1442 struct brw_reg dst) 1443{ 1444 brw_MOV(&func, vec8(dst), vec8(src)); 1445 brw_set_compression_control(&func, BRW_COMPRESSION_2NDHALF); 1446 brw_MOV(&func, offset(vec8(dst), 1), suboffset(vec8(src), 8)); 1447 brw_set_compression_control(&func, BRW_COMPRESSION_NONE); 1448} 1449 1450void 1451brw_blorp_blit_program::texture_lookup(struct brw_reg dst, 1452 GLuint msg_type, 1453 const sampler_message_arg *args, 1454 int num_args) 1455{ 1456 struct brw_reg mrf = 1457 retype(vec16(brw_message_reg(base_mrf)), BRW_REGISTER_TYPE_UD); 1458 for (int arg = 0; arg < num_args; ++arg) { 1459 switch (args[arg]) { 1460 case SAMPLER_MESSAGE_ARG_U_FLOAT: 1461 expand_to_32_bits(X, retype(mrf, BRW_REGISTER_TYPE_F)); 1462 break; 1463 case SAMPLER_MESSAGE_ARG_V_FLOAT: 1464 expand_to_32_bits(Y, retype(mrf, BRW_REGISTER_TYPE_F)); 1465 break; 1466 case SAMPLER_MESSAGE_ARG_U_INT: 1467 expand_to_32_bits(X, mrf); 1468 break; 1469 case SAMPLER_MESSAGE_ARG_V_INT: 1470 expand_to_32_bits(Y, mrf); 1471 break; 1472 case SAMPLER_MESSAGE_ARG_SI_INT: 1473 /* Note: on Gen7, this code may be reached with s_is_zero==true 1474 * because in Gen7's ld2dss message, the sample index is the first 1475 * argument. When this happens, we need to move a 0 into the 1476 * appropriate message register. 1477 */ 1478 if (s_is_zero) 1479 brw_MOV(&func, mrf, brw_imm_ud(0)); 1480 else 1481 expand_to_32_bits(S, mrf); 1482 break; 1483 case SAMPLER_MESSAGE_ARG_MCS_INT: 1484 switch (key->tex_layout) { 1485 case INTEL_MSAA_LAYOUT_CMS: 1486 brw_MOV(&func, mrf, mcs_data); 1487 break; 1488 case INTEL_MSAA_LAYOUT_IMS: 1489 /* When sampling from an IMS surface, MCS data is not relevant, 1490 * and the hardware ignores it. So don't bother populating it. 1491 */ 1492 break; 1493 default: 1494 /* We shouldn't be trying to send MCS data with any other 1495 * layouts. 1496 */ 1497 assert (!"Unsupported layout for MCS data"); 1498 break; 1499 } 1500 break; 1501 case SAMPLER_MESSAGE_ARG_ZERO_INT: 1502 brw_MOV(&func, mrf, brw_imm_ud(0)); 1503 break; 1504 } 1505 mrf.nr += 2; 1506 } 1507 1508 brw_SAMPLE(&func, 1509 retype(dst, BRW_REGISTER_TYPE_UW) /* dest */, 1510 base_mrf /* msg_reg_nr */, 1511 brw_message_reg(base_mrf) /* src0 */, 1512 BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX, 1513 0 /* sampler */, 1514 WRITEMASK_XYZW, 1515 msg_type, 1516 8 /* response_length. TODO: should be smaller for non-RGBA formats? */, 1517 mrf.nr - base_mrf /* msg_length */, 1518 0 /* header_present */, 1519 BRW_SAMPLER_SIMD_MODE_SIMD16, 1520 BRW_SAMPLER_RETURN_FORMAT_FLOAT32); 1521} 1522 1523#undef X 1524#undef Y 1525#undef U 1526#undef V 1527#undef S 1528#undef SWAP_XY_AND_XPYP 1529 1530void 1531brw_blorp_blit_program::render_target_write() 1532{ 1533 struct brw_reg mrf_rt_write = 1534 retype(vec16(brw_message_reg(base_mrf)), key->texture_data_type); 1535 int mrf_offset = 0; 1536 1537 /* If we may have killed pixels, then we need to send R0 and R1 in a header 1538 * so that the render target knows which pixels we killed. 1539 */ 1540 bool use_header = key->use_kill; 1541 if (use_header) { 1542 /* Copy R0/1 to MRF */ 1543 brw_MOV(&func, retype(mrf_rt_write, BRW_REGISTER_TYPE_UD), 1544 retype(R0, BRW_REGISTER_TYPE_UD)); 1545 mrf_offset += 2; 1546 } 1547 1548 /* Copy texture data to MRFs */ 1549 for (int i = 0; i < 4; ++i) { 1550 /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */ 1551 brw_MOV(&func, offset(mrf_rt_write, mrf_offset), 1552 offset(vec8(texture_data[0]), 2*i)); 1553 mrf_offset += 2; 1554 } 1555 1556 /* Now write to the render target and terminate the thread */ 1557 brw_fb_WRITE(&func, 1558 16 /* dispatch_width */, 1559 base_mrf /* msg_reg_nr */, 1560 mrf_rt_write /* src0 */, 1561 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE, 1562 BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX, 1563 mrf_offset /* msg_length. TODO: Should be smaller for non-RGBA formats. */, 1564 0 /* response_length */, 1565 true /* eot */, 1566 use_header); 1567} 1568 1569 1570void 1571brw_blorp_coord_transform_params::setup(GLuint src0, GLuint dst0, GLuint dst1, 1572 bool mirror) 1573{ 1574 if (!mirror) { 1575 /* When not mirroring a coordinate (say, X), we need: 1576 * x' - src_x0 = x - dst_x0 1577 * Therefore: 1578 * x' = 1*x + (src_x0 - dst_x0) 1579 */ 1580 multiplier = 1; 1581 offset = src0 - dst0; 1582 } else { 1583 /* When mirroring X we need: 1584 * x' - src_x0 = dst_x1 - x - 1 1585 * Therefore: 1586 * x' = -1*x + (src_x0 + dst_x1 - 1) 1587 */ 1588 multiplier = -1; 1589 offset = src0 + dst1 - 1; 1590 } 1591} 1592 1593 1594/** 1595 * Determine which MSAA layout the GPU pipeline should be configured for, 1596 * based on the chip generation, the number of samples, and the true layout of 1597 * the image in memory. 1598 */ 1599inline intel_msaa_layout 1600compute_msaa_layout_for_pipeline(struct brw_context *brw, unsigned num_samples, 1601 intel_msaa_layout true_layout) 1602{ 1603 if (num_samples <= 1) { 1604 /* When configuring the GPU for non-MSAA, we can still accommodate IMS 1605 * format buffers, by transforming coordinates appropriately. 1606 */ 1607 assert(true_layout == INTEL_MSAA_LAYOUT_NONE || 1608 true_layout == INTEL_MSAA_LAYOUT_IMS); 1609 return INTEL_MSAA_LAYOUT_NONE; 1610 } else { 1611 assert(true_layout != INTEL_MSAA_LAYOUT_NONE); 1612 } 1613 1614 /* Prior to Gen7, all MSAA surfaces use IMS layout. */ 1615 if (brw->intel.gen == 6) { 1616 assert(true_layout == INTEL_MSAA_LAYOUT_IMS); 1617 } 1618 1619 return true_layout; 1620} 1621 1622 1623brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context *brw, 1624 struct intel_mipmap_tree *src_mt, 1625 struct intel_mipmap_tree *dst_mt, 1626 GLuint src_x0, GLuint src_y0, 1627 GLuint dst_x0, GLuint dst_y0, 1628 GLuint dst_x1, GLuint dst_y1, 1629 bool mirror_x, bool mirror_y) 1630{ 1631 src.set(brw, src_mt, 0, 0); 1632 dst.set(brw, dst_mt, 0, 0); 1633 1634 use_wm_prog = true; 1635 memset(&wm_prog_key, 0, sizeof(wm_prog_key)); 1636 1637 /* texture_data_type indicates the register type that should be used to 1638 * manipulate texture data. 1639 */ 1640 switch (_mesa_get_format_datatype(src_mt->format)) { 1641 case GL_UNSIGNED_NORMALIZED: 1642 case GL_SIGNED_NORMALIZED: 1643 case GL_FLOAT: 1644 wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_F; 1645 break; 1646 case GL_UNSIGNED_INT: 1647 if (src_mt->format == MESA_FORMAT_S8) { 1648 /* We process stencil as though it's an unsigned normalized color */ 1649 wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_F; 1650 } else { 1651 wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_UD; 1652 } 1653 break; 1654 case GL_INT: 1655 wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_D; 1656 break; 1657 default: 1658 assert(!"Unrecognized blorp format"); 1659 break; 1660 } 1661 1662 if (brw->intel.gen > 6) { 1663 /* Gen7's rendering hardware only supports the IMS layout for depth and 1664 * stencil render targets. Blorp always maps its destination surface as 1665 * a color render target (even if it's actually a depth or stencil 1666 * buffer). So if the destination is IMS, we'll have to map it as a 1667 * single-sampled texture and interleave the samples ourselves. 1668 */ 1669 if (dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) 1670 dst.num_samples = 0; 1671 } 1672 1673 if (dst.map_stencil_as_y_tiled && dst.num_samples > 1) { 1674 /* If the destination surface is a W-tiled multisampled stencil buffer 1675 * that we're mapping as Y tiled, then we need to arrange for the WM 1676 * program to run once per sample rather than once per pixel, because 1677 * the memory layout of related samples doesn't match between W and Y 1678 * tiling. 1679 */ 1680 wm_prog_key.persample_msaa_dispatch = true; 1681 } 1682 1683 if (src.num_samples > 0 && dst.num_samples > 1) { 1684 /* We are blitting from a multisample buffer to a multisample buffer, so 1685 * we must preserve samples within a pixel. This means we have to 1686 * arrange for the WM program to run once per sample rather than once 1687 * per pixel. 1688 */ 1689 wm_prog_key.persample_msaa_dispatch = true; 1690 } 1691 1692 /* The render path must be configured to use the same number of samples as 1693 * the destination buffer. 1694 */ 1695 num_samples = dst.num_samples; 1696 1697 GLenum base_format = _mesa_get_format_base_format(src_mt->format); 1698 if (base_format != GL_DEPTH_COMPONENT && /* TODO: what about depth/stencil? */ 1699 base_format != GL_STENCIL_INDEX && 1700 src_mt->num_samples > 1 && dst_mt->num_samples <= 1) { 1701 /* We are downsampling a color buffer, so blend. */ 1702 wm_prog_key.blend = true; 1703 } 1704 1705 /* src_samples and dst_samples are the true sample counts */ 1706 wm_prog_key.src_samples = src_mt->num_samples; 1707 wm_prog_key.dst_samples = dst_mt->num_samples; 1708 1709 /* tex_samples and rt_samples are the sample counts that are set up in 1710 * SURFACE_STATE. 1711 */ 1712 wm_prog_key.tex_samples = src.num_samples; 1713 wm_prog_key.rt_samples = dst.num_samples; 1714 1715 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will 1716 * use to access the source and destination surfaces. 1717 */ 1718 wm_prog_key.tex_layout = 1719 compute_msaa_layout_for_pipeline(brw, src.num_samples, src.msaa_layout); 1720 wm_prog_key.rt_layout = 1721 compute_msaa_layout_for_pipeline(brw, dst.num_samples, dst.msaa_layout); 1722 1723 /* src_layout and dst_layout indicate the true MSAA layout used by src and 1724 * dst. 1725 */ 1726 wm_prog_key.src_layout = src_mt->msaa_layout; 1727 wm_prog_key.dst_layout = dst_mt->msaa_layout; 1728 1729 wm_prog_key.src_tiled_w = src.map_stencil_as_y_tiled; 1730 wm_prog_key.dst_tiled_w = dst.map_stencil_as_y_tiled; 1731 x0 = wm_push_consts.dst_x0 = dst_x0; 1732 y0 = wm_push_consts.dst_y0 = dst_y0; 1733 x1 = wm_push_consts.dst_x1 = dst_x1; 1734 y1 = wm_push_consts.dst_y1 = dst_y1; 1735 wm_push_consts.x_transform.setup(src_x0, dst_x0, dst_x1, mirror_x); 1736 wm_push_consts.y_transform.setup(src_y0, dst_y0, dst_y1, mirror_y); 1737 1738 if (dst.num_samples <= 1 && dst_mt->num_samples > 1) { 1739 /* We must expand the rectangle we send through the rendering pipeline, 1740 * to account for the fact that we are mapping the destination region as 1741 * single-sampled when it is in fact multisampled. We must also align 1742 * it to a multiple of the multisampling pattern, because the 1743 * differences between multisampled and single-sampled surface formats 1744 * will mean that pixels are scrambled within the multisampling pattern. 1745 * TODO: what if this makes the coordinates too large? 1746 * 1747 * Note: this only works if the destination surface uses the IMS layout. 1748 * If it's UMS, then we have no choice but to set up the rendering 1749 * pipeline as multisampled. 1750 */ 1751 assert(dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS); 1752 switch (dst_mt->num_samples) { 1753 case 4: 1754 x0 = ROUND_DOWN_TO(x0 * 2, 4); 1755 y0 = ROUND_DOWN_TO(y0 * 2, 4); 1756 x1 = ALIGN(x1 * 2, 4); 1757 y1 = ALIGN(y1 * 2, 4); 1758 break; 1759 case 8: 1760 x0 = ROUND_DOWN_TO(x0 * 4, 8); 1761 y0 = ROUND_DOWN_TO(y0 * 2, 4); 1762 x1 = ALIGN(x1 * 4, 8); 1763 y1 = ALIGN(y1 * 2, 4); 1764 break; 1765 default: 1766 assert(!"Unrecognized sample count in brw_blorp_blit_params ctor"); 1767 break; 1768 } 1769 wm_prog_key.use_kill = true; 1770 } 1771 1772 if (dst.map_stencil_as_y_tiled) { 1773 /* We must modify the rectangle we send through the rendering pipeline 1774 * (and the size of the destination surface), to account for the fact 1775 * that we are mapping it as Y-tiled when it is in fact W-tiled. Y 1776 * tiles have dimensions 128x32 whereas W tiles have dimensions 64x64. 1777 * We must also align it to a multiple of the tile size, because the 1778 * differences between W and Y tiling formats will mean that pixels are 1779 * scrambled within the tile. 1780 * 1781 * Note: if the destination surface configured to use IMS layout, then 1782 * the effective tile size we need to align it to is smaller, because 1783 * each pixel covers a 2x2 or a 4x2 block of samples. 1784 * 1785 * TODO: what if this makes the coordinates (or the texture size) too 1786 * large? 1787 */ 1788 unsigned x_align = 64, y_align = 64; 1789 if (dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) { 1790 x_align /= (dst_mt->num_samples == 4 ? 2 : 4); 1791 y_align /= 2; 1792 } 1793 x0 = ROUND_DOWN_TO(x0, x_align) * 2; 1794 y0 = ROUND_DOWN_TO(y0, y_align) / 2; 1795 x1 = ALIGN(x1, x_align) * 2; 1796 y1 = ALIGN(y1, y_align) / 2; 1797 dst.width *= 2; 1798 dst.height /= 2; 1799 wm_prog_key.use_kill = true; 1800 } 1801 1802 if (src.map_stencil_as_y_tiled) { 1803 /* We must modify the size of the source surface to account for the fact 1804 * that we are mapping it as Y-tiled when it is in fact W tiled. 1805 * 1806 * TODO: what if this makes the texture size too large? 1807 */ 1808 src.width *= 2; 1809 src.height /= 2; 1810 } 1811} 1812 1813uint32_t 1814brw_blorp_blit_params::get_wm_prog(struct brw_context *brw, 1815 brw_blorp_prog_data **prog_data) const 1816{ 1817 uint32_t prog_offset; 1818 if (!brw_search_cache(&brw->cache, BRW_BLORP_BLIT_PROG, 1819 &this->wm_prog_key, sizeof(this->wm_prog_key), 1820 &prog_offset, prog_data)) { 1821 brw_blorp_blit_program prog(brw, &this->wm_prog_key); 1822 GLuint program_size; 1823 const GLuint *program = prog.compile(brw, &program_size); 1824 brw_upload_cache(&brw->cache, BRW_BLORP_BLIT_PROG, 1825 &this->wm_prog_key, sizeof(this->wm_prog_key), 1826 program, program_size, 1827 &prog.prog_data, sizeof(prog.prog_data), 1828 &prog_offset, prog_data); 1829 } 1830 return prog_offset; 1831} 1832