brw_blorp_blit.cpp revision 62bc4af0e18f76dd30a4d5ae6d45a365a1fa226f
1/* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#include "main/teximage.h" 25#include "main/fbobject.h" 26 27#include "glsl/ralloc.h" 28 29#include "intel_fbo.h" 30 31#include "brw_blorp.h" 32#include "brw_context.h" 33#include "brw_eu.h" 34#include "brw_state.h" 35 36 37/** 38 * Helper function for handling mirror image blits. 39 * 40 * If coord0 > coord1, swap them and invert the "mirror" boolean. 41 */ 42static inline void 43fixup_mirroring(bool &mirror, GLint &coord0, GLint &coord1) 44{ 45 if (coord0 > coord1) { 46 mirror = !mirror; 47 GLint tmp = coord0; 48 coord0 = coord1; 49 coord1 = tmp; 50 } 51} 52 53 54/** 55 * Adjust {src,dst}_x{0,1} to account for clipping and scissoring of 56 * destination coordinates. 57 * 58 * Return true if there is still blitting to do, false if all pixels got 59 * rejected by the clip and/or scissor. 60 * 61 * For clarity, the nomenclature of this function assumes we are clipping and 62 * scissoring the X coordinate; the exact same logic applies for Y 63 * coordinates. 64 * 65 * Note: this function may also be used to account for clipping of source 66 * coordinates, by swapping the roles of src and dst. 67 */ 68static inline bool 69clip_or_scissor(bool mirror, GLint &src_x0, GLint &src_x1, GLint &dst_x0, 70 GLint &dst_x1, GLint fb_xmin, GLint fb_xmax) 71{ 72 /* If we are going to scissor everything away, stop. */ 73 if (!(fb_xmin < fb_xmax && 74 dst_x0 < fb_xmax && 75 fb_xmin < dst_x1 && 76 dst_x0 < dst_x1)) { 77 return false; 78 } 79 80 /* Clip the destination rectangle, and keep track of how many pixels we 81 * clipped off of the left and right sides of it. 82 */ 83 GLint pixels_clipped_left = 0; 84 GLint pixels_clipped_right = 0; 85 if (dst_x0 < fb_xmin) { 86 pixels_clipped_left = fb_xmin - dst_x0; 87 dst_x0 = fb_xmin; 88 } 89 if (fb_xmax < dst_x1) { 90 pixels_clipped_right = dst_x1 - fb_xmax; 91 dst_x1 = fb_xmax; 92 } 93 94 /* If we are mirrored, then before applying pixels_clipped_{left,right} to 95 * the source coordinates, we need to flip them to account for the 96 * mirroring. 97 */ 98 if (mirror) { 99 GLint tmp = pixels_clipped_left; 100 pixels_clipped_left = pixels_clipped_right; 101 pixels_clipped_right = tmp; 102 } 103 104 /* Adjust the source rectangle to remove the pixels corresponding to those 105 * that were clipped/scissored out of the destination rectangle. 106 */ 107 src_x0 += pixels_clipped_left; 108 src_x1 -= pixels_clipped_right; 109 110 return true; 111} 112 113 114static struct intel_mipmap_tree * 115find_miptree(GLbitfield buffer_bit, struct intel_renderbuffer *irb) 116{ 117 struct intel_mipmap_tree *mt = irb->mt; 118 if (buffer_bit == GL_STENCIL_BUFFER_BIT && mt->stencil_mt) 119 mt = mt->stencil_mt; 120 return mt; 121} 122 123void 124brw_blorp_blit_miptrees(struct intel_context *intel, 125 struct intel_mipmap_tree *src_mt, 126 unsigned src_level, unsigned src_layer, 127 struct intel_mipmap_tree *dst_mt, 128 unsigned dst_level, unsigned dst_layer, 129 int src_x0, int src_y0, 130 int dst_x0, int dst_y0, 131 int dst_x1, int dst_y1, 132 bool mirror_x, bool mirror_y) 133{ 134 brw_blorp_blit_params params(brw_context(&intel->ctx), 135 src_mt, src_level, src_layer, 136 dst_mt, dst_level, dst_layer, 137 src_x0, src_y0, 138 dst_x0, dst_y0, 139 dst_x1, dst_y1, 140 mirror_x, mirror_y); 141 brw_blorp_exec(intel, ¶ms); 142} 143 144static void 145do_blorp_blit(struct intel_context *intel, GLbitfield buffer_bit, 146 struct intel_renderbuffer *src_irb, 147 struct intel_renderbuffer *dst_irb, 148 GLint srcX0, GLint srcY0, 149 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1, 150 bool mirror_x, bool mirror_y) 151{ 152 /* Find source/dst miptrees */ 153 struct intel_mipmap_tree *src_mt = find_miptree(buffer_bit, src_irb); 154 struct intel_mipmap_tree *dst_mt = find_miptree(buffer_bit, dst_irb); 155 156 /* Get ready to blit. This includes depth resolving the src and dst 157 * buffers if necessary. 158 */ 159 intel_renderbuffer_resolve_depth(intel, src_irb); 160 intel_renderbuffer_resolve_depth(intel, dst_irb); 161 162 /* Do the blit */ 163 brw_blorp_blit_miptrees(intel, 164 src_mt, src_irb->mt_level, src_irb->mt_layer, 165 dst_mt, dst_irb->mt_level, dst_irb->mt_layer, 166 srcX0, srcY0, dstX0, dstY0, dstX1, dstY1, 167 mirror_x, mirror_y); 168 169 intel_renderbuffer_set_needs_hiz_resolve(dst_irb); 170 intel_renderbuffer_set_needs_downsample(dst_irb); 171} 172 173 174static bool 175formats_match(GLbitfield buffer_bit, struct intel_renderbuffer *src_irb, 176 struct intel_renderbuffer *dst_irb) 177{ 178 /* Note: don't just check gl_renderbuffer::Format, because in some cases 179 * multiple gl_formats resolve to the same native type in the miptree (for 180 * example MESA_FORMAT_X8_Z24 and MESA_FORMAT_S8_Z24), and we can blit 181 * between those formats. 182 */ 183 return find_miptree(buffer_bit, src_irb)->format == 184 find_miptree(buffer_bit, dst_irb)->format; 185} 186 187 188static bool 189try_blorp_blit(struct intel_context *intel, 190 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1, 191 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1, 192 GLenum filter, GLbitfield buffer_bit) 193{ 194 struct gl_context *ctx = &intel->ctx; 195 196 /* Sync up the state of window system buffers. We need to do this before 197 * we go looking for the buffers. 198 */ 199 intel_prepare_render(intel); 200 201 const struct gl_framebuffer *read_fb = ctx->ReadBuffer; 202 const struct gl_framebuffer *draw_fb = ctx->DrawBuffer; 203 204 /* Detect if the blit needs to be mirrored */ 205 bool mirror_x = false, mirror_y = false; 206 fixup_mirroring(mirror_x, srcX0, srcX1); 207 fixup_mirroring(mirror_x, dstX0, dstX1); 208 fixup_mirroring(mirror_y, srcY0, srcY1); 209 fixup_mirroring(mirror_y, dstY0, dstY1); 210 211 /* Make sure width and height match */ 212 if (srcX1 - srcX0 != dstX1 - dstX0) return false; 213 if (srcY1 - srcY0 != dstY1 - dstY0) return false; 214 215 /* If the destination rectangle needs to be clipped or scissored, do so. 216 */ 217 if (!(clip_or_scissor(mirror_x, srcX0, srcX1, dstX0, dstX1, 218 draw_fb->_Xmin, draw_fb->_Xmax) && 219 clip_or_scissor(mirror_y, srcY0, srcY1, dstY0, dstY1, 220 draw_fb->_Ymin, draw_fb->_Ymax))) { 221 /* Everything got clipped/scissored away, so the blit was successful. */ 222 return true; 223 } 224 225 /* If the source rectangle needs to be clipped or scissored, do so. */ 226 if (!(clip_or_scissor(mirror_x, dstX0, dstX1, srcX0, srcX1, 227 0, read_fb->Width) && 228 clip_or_scissor(mirror_y, dstY0, dstY1, srcY0, srcY1, 229 0, read_fb->Height))) { 230 /* Everything got clipped/scissored away, so the blit was successful. */ 231 return true; 232 } 233 234 /* Account for the fact that in the system framebuffer, the origin is at 235 * the lower left. 236 */ 237 if (_mesa_is_winsys_fbo(read_fb)) { 238 GLint tmp = read_fb->Height - srcY0; 239 srcY0 = read_fb->Height - srcY1; 240 srcY1 = tmp; 241 mirror_y = !mirror_y; 242 } 243 if (_mesa_is_winsys_fbo(draw_fb)) { 244 GLint tmp = draw_fb->Height - dstY0; 245 dstY0 = draw_fb->Height - dstY1; 246 dstY1 = tmp; 247 mirror_y = !mirror_y; 248 } 249 250 /* Find buffers */ 251 struct intel_renderbuffer *src_irb; 252 struct intel_renderbuffer *dst_irb; 253 switch (buffer_bit) { 254 case GL_COLOR_BUFFER_BIT: 255 src_irb = intel_renderbuffer(read_fb->_ColorReadBuffer); 256 for (unsigned i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; ++i) { 257 dst_irb = intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i]); 258 if (dst_irb && !formats_match(buffer_bit, src_irb, dst_irb)) 259 return false; 260 } 261 for (unsigned i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; ++i) { 262 dst_irb = intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i]); 263 do_blorp_blit(intel, buffer_bit, src_irb, dst_irb, srcX0, srcY0, 264 dstX0, dstY0, dstX1, dstY1, mirror_x, mirror_y); 265 } 266 break; 267 case GL_DEPTH_BUFFER_BIT: 268 src_irb = 269 intel_renderbuffer(read_fb->Attachment[BUFFER_DEPTH].Renderbuffer); 270 dst_irb = 271 intel_renderbuffer(draw_fb->Attachment[BUFFER_DEPTH].Renderbuffer); 272 if (!formats_match(buffer_bit, src_irb, dst_irb)) 273 return false; 274 do_blorp_blit(intel, buffer_bit, src_irb, dst_irb, srcX0, srcY0, 275 dstX0, dstY0, dstX1, dstY1, mirror_x, mirror_y); 276 break; 277 case GL_STENCIL_BUFFER_BIT: 278 src_irb = 279 intel_renderbuffer(read_fb->Attachment[BUFFER_STENCIL].Renderbuffer); 280 dst_irb = 281 intel_renderbuffer(draw_fb->Attachment[BUFFER_STENCIL].Renderbuffer); 282 if (!formats_match(buffer_bit, src_irb, dst_irb)) 283 return false; 284 do_blorp_blit(intel, buffer_bit, src_irb, dst_irb, srcX0, srcY0, 285 dstX0, dstY0, dstX1, dstY1, mirror_x, mirror_y); 286 break; 287 default: 288 assert(false); 289 } 290 291 return true; 292} 293 294GLbitfield 295brw_blorp_framebuffer(struct intel_context *intel, 296 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1, 297 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1, 298 GLbitfield mask, GLenum filter) 299{ 300 /* BLORP is not supported before Gen6. */ 301 if (intel->gen < 6) 302 return mask; 303 304 static GLbitfield buffer_bits[] = { 305 GL_COLOR_BUFFER_BIT, 306 GL_DEPTH_BUFFER_BIT, 307 GL_STENCIL_BUFFER_BIT, 308 }; 309 310 for (unsigned int i = 0; i < ARRAY_SIZE(buffer_bits); ++i) { 311 if ((mask & buffer_bits[i]) && 312 try_blorp_blit(intel, 313 srcX0, srcY0, srcX1, srcY1, 314 dstX0, dstY0, dstX1, dstY1, 315 filter, buffer_bits[i])) { 316 mask &= ~buffer_bits[i]; 317 } 318 } 319 320 return mask; 321} 322 323 324/** 325 * Enum to specify the order of arguments in a sampler message 326 */ 327enum sampler_message_arg 328{ 329 SAMPLER_MESSAGE_ARG_U_FLOAT, 330 SAMPLER_MESSAGE_ARG_V_FLOAT, 331 SAMPLER_MESSAGE_ARG_U_INT, 332 SAMPLER_MESSAGE_ARG_V_INT, 333 SAMPLER_MESSAGE_ARG_SI_INT, 334 SAMPLER_MESSAGE_ARG_MCS_INT, 335 SAMPLER_MESSAGE_ARG_ZERO_INT, 336}; 337 338/** 339 * Generator for WM programs used in BLORP blits. 340 * 341 * The bulk of the work done by the WM program is to wrap and unwrap the 342 * coordinate transformations used by the hardware to store surfaces in 343 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the 344 * sample index for a multisampled surface) to a memory offset by the 345 * following formulas: 346 * 347 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S)) 348 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset)) 349 * 350 * For a single-sampled surface, or for a multisampled surface using 351 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity 352 * function: 353 * 354 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0) 355 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0) 356 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S) 357 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S) 358 * 359 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa() 360 * embeds the sample number into bit 1 of the X and Y coordinates: 361 * 362 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0) 363 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1) 364 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1) 365 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S) 366 * where X' = (X & ~0b11) >> 1 | (X & 0b1) 367 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1) 368 * S = (Y & 0b10) | (X & 0b10) >> 1 369 * 370 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa() 371 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of 372 * the Y coordinate: 373 * 374 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0) 375 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1) 376 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1) 377 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S) 378 * where X' = (X & ~0b111) >> 2 | (X & 0b1) 379 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1) 380 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1 381 * 382 * For X tiling, tile() combines together the low-order bits of the X and Y 383 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512 384 * bytes wide and 8 rows high: 385 * 386 * tile(x_tiled, X, Y, S) = A 387 * where A = tile_num << 12 | offset 388 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9) 389 * offset = (Y' & 0b111) << 9 390 * | (X & 0b111111111) 391 * X' = X * cpp 392 * Y' = Y + S * qpitch 393 * detile(x_tiled, A) = (X, Y, S) 394 * where X = X' / cpp 395 * Y = Y' % qpitch 396 * S = Y' / qpitch 397 * Y' = (tile_num / tile_pitch) << 3 398 * | (A & 0b111000000000) >> 9 399 * X' = (tile_num % tile_pitch) << 9 400 * | (A & 0b111111111) 401 * 402 * (In all tiling formulas, cpp is the number of bytes occupied by a single 403 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required 404 * to fill the width of the surface, and qpitch is the spacing (in rows) 405 * between array slices). 406 * 407 * For Y tiling, tile() combines together the low-order bits of the X and Y 408 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128 409 * bytes wide and 32 rows high: 410 * 411 * tile(y_tiled, X, Y, S) = A 412 * where A = tile_num << 12 | offset 413 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7) 414 * offset = (X' & 0b1110000) << 5 415 * | (Y' & 0b11111) << 4 416 * | (X' & 0b1111) 417 * X' = X * cpp 418 * Y' = Y + S * qpitch 419 * detile(y_tiled, A) = (X, Y, S) 420 * where X = X' / cpp 421 * Y = Y' % qpitch 422 * S = Y' / qpitch 423 * Y' = (tile_num / tile_pitch) << 5 424 * | (A & 0b111110000) >> 4 425 * X' = (tile_num % tile_pitch) << 7 426 * | (A & 0b111000000000) >> 5 427 * | (A & 0b1111) 428 * 429 * For W tiling, tile() combines together the low-order bits of the X and Y 430 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64 431 * bytes wide and 64 rows high (note that W tiling is only used for stencil 432 * buffers, which always have cpp = 1 and S=0): 433 * 434 * tile(w_tiled, X, Y, S) = A 435 * where A = tile_num << 12 | offset 436 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6) 437 * offset = (X' & 0b111000) << 6 438 * | (Y' & 0b111100) << 3 439 * | (X' & 0b100) << 2 440 * | (Y' & 0b10) << 2 441 * | (X' & 0b10) << 1 442 * | (Y' & 0b1) << 1 443 * | (X' & 0b1) 444 * X' = X * cpp = X 445 * Y' = Y + S * qpitch 446 * detile(w_tiled, A) = (X, Y, S) 447 * where X = X' / cpp = X' 448 * Y = Y' % qpitch = Y' 449 * S = Y / qpitch = 0 450 * Y' = (tile_num / tile_pitch) << 6 451 * | (A & 0b111100000) >> 3 452 * | (A & 0b1000) >> 2 453 * | (A & 0b10) >> 1 454 * X' = (tile_num % tile_pitch) << 6 455 * | (A & 0b111000000000) >> 6 456 * | (A & 0b10000) >> 2 457 * | (A & 0b100) >> 1 458 * | (A & 0b1) 459 * 460 * Finally, for a non-tiled surface, tile() simply combines together the X and 461 * Y coordinates in the natural way: 462 * 463 * tile(untiled, X, Y, S) = A 464 * where A = Y * pitch + X' 465 * X' = X * cpp 466 * Y' = Y + S * qpitch 467 * detile(untiled, A) = (X, Y, S) 468 * where X = X' / cpp 469 * Y = Y' % qpitch 470 * S = Y' / qpitch 471 * X' = A % pitch 472 * Y' = A / pitch 473 * 474 * (In these formulas, pitch is the number of bytes occupied by a single row 475 * of samples). 476 */ 477class brw_blorp_blit_program 478{ 479public: 480 brw_blorp_blit_program(struct brw_context *brw, 481 const brw_blorp_blit_prog_key *key); 482 ~brw_blorp_blit_program(); 483 484 const GLuint *compile(struct brw_context *brw, GLuint *program_size); 485 486 brw_blorp_prog_data prog_data; 487 488private: 489 void alloc_regs(); 490 void alloc_push_const_regs(int base_reg); 491 void compute_frag_coords(); 492 void translate_tiling(bool old_tiled_w, bool new_tiled_w); 493 void encode_msaa(unsigned num_samples, intel_msaa_layout layout); 494 void decode_msaa(unsigned num_samples, intel_msaa_layout layout); 495 void kill_if_outside_dst_rect(); 496 void translate_dst_to_src(); 497 void single_to_blend(); 498 void manual_blend(unsigned num_samples); 499 void sample(struct brw_reg dst); 500 void texel_fetch(struct brw_reg dst); 501 void mcs_fetch(); 502 void expand_to_32_bits(struct brw_reg src, struct brw_reg dst); 503 void texture_lookup(struct brw_reg dst, GLuint msg_type, 504 const sampler_message_arg *args, int num_args); 505 void render_target_write(); 506 507 /** 508 * Base-2 logarithm of the maximum number of samples that can be blended. 509 */ 510 static const unsigned LOG2_MAX_BLEND_SAMPLES = 3; 511 512 void *mem_ctx; 513 struct brw_context *brw; 514 const brw_blorp_blit_prog_key *key; 515 struct brw_compile func; 516 517 /* Thread dispatch header */ 518 struct brw_reg R0; 519 520 /* Pixel X/Y coordinates (always in R1). */ 521 struct brw_reg R1; 522 523 /* Push constants */ 524 struct brw_reg dst_x0; 525 struct brw_reg dst_x1; 526 struct brw_reg dst_y0; 527 struct brw_reg dst_y1; 528 struct { 529 struct brw_reg multiplier; 530 struct brw_reg offset; 531 } x_transform, y_transform; 532 533 /* Data read from texture (4 vec16's per array element) */ 534 struct brw_reg texture_data[LOG2_MAX_BLEND_SAMPLES + 1]; 535 536 /* Auxiliary storage for the contents of the MCS surface. 537 * 538 * Since the sampler always returns 8 registers worth of data, this is 8 539 * registers wide, even though we only use the first 2 registers of it. 540 */ 541 struct brw_reg mcs_data; 542 543 /* X coordinates. We have two of them so that we can perform coordinate 544 * transformations easily. 545 */ 546 struct brw_reg x_coords[2]; 547 548 /* Y coordinates. We have two of them so that we can perform coordinate 549 * transformations easily. 550 */ 551 struct brw_reg y_coords[2]; 552 553 /* Which element of x_coords and y_coords is currently in use. 554 */ 555 int xy_coord_index; 556 557 /* True if, at the point in the program currently being compiled, the 558 * sample index is known to be zero. 559 */ 560 bool s_is_zero; 561 562 /* Register storing the sample index when s_is_zero is false. */ 563 struct brw_reg sample_index; 564 565 /* Temporaries */ 566 struct brw_reg t1; 567 struct brw_reg t2; 568 569 /* MRF used for sampling and render target writes */ 570 GLuint base_mrf; 571}; 572 573brw_blorp_blit_program::brw_blorp_blit_program( 574 struct brw_context *brw, 575 const brw_blorp_blit_prog_key *key) 576 : mem_ctx(ralloc_context(NULL)), 577 brw(brw), 578 key(key) 579{ 580 brw_init_compile(brw, &func, mem_ctx); 581} 582 583brw_blorp_blit_program::~brw_blorp_blit_program() 584{ 585 ralloc_free(mem_ctx); 586} 587 588const GLuint * 589brw_blorp_blit_program::compile(struct brw_context *brw, 590 GLuint *program_size) 591{ 592 /* Sanity checks */ 593 if (key->dst_tiled_w && key->rt_samples > 0) { 594 /* If the destination image is W tiled and multisampled, then the thread 595 * must be dispatched once per sample, not once per pixel. This is 596 * necessary because after conversion between W and Y tiling, there's no 597 * guarantee that all samples corresponding to a single pixel will still 598 * be together. 599 */ 600 assert(key->persample_msaa_dispatch); 601 } 602 603 if (key->blend) { 604 /* We are blending, which means we won't have an opportunity to 605 * translate the tiling and sample count for the texture surface. So 606 * the surface state for the texture must be configured with the correct 607 * tiling and sample count. 608 */ 609 assert(!key->src_tiled_w); 610 assert(key->tex_samples == key->src_samples); 611 assert(key->tex_layout == key->src_layout); 612 assert(key->tex_samples > 0); 613 } 614 615 if (key->persample_msaa_dispatch) { 616 /* It only makes sense to do persample dispatch if the render target is 617 * configured as multisampled. 618 */ 619 assert(key->rt_samples > 0); 620 } 621 622 /* Make sure layout is consistent with sample count */ 623 assert((key->tex_layout == INTEL_MSAA_LAYOUT_NONE) == 624 (key->tex_samples == 0)); 625 assert((key->rt_layout == INTEL_MSAA_LAYOUT_NONE) == 626 (key->rt_samples == 0)); 627 assert((key->src_layout == INTEL_MSAA_LAYOUT_NONE) == 628 (key->src_samples == 0)); 629 assert((key->dst_layout == INTEL_MSAA_LAYOUT_NONE) == 630 (key->dst_samples == 0)); 631 632 /* Set up prog_data */ 633 memset(&prog_data, 0, sizeof(prog_data)); 634 prog_data.persample_msaa_dispatch = key->persample_msaa_dispatch; 635 636 brw_set_compression_control(&func, BRW_COMPRESSION_NONE); 637 638 alloc_regs(); 639 compute_frag_coords(); 640 641 /* Render target and texture hardware don't support W tiling. */ 642 const bool rt_tiled_w = false; 643 const bool tex_tiled_w = false; 644 645 /* The address that data will be written to is determined by the 646 * coordinates supplied to the WM thread and the tiling and sample count of 647 * the render target, according to the formula: 648 * 649 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset)) 650 * 651 * If the actual tiling and sample count of the destination surface are not 652 * the same as the configuration of the render target, then these 653 * coordinates are wrong and we have to adjust them to compensate for the 654 * difference. 655 */ 656 if (rt_tiled_w != key->dst_tiled_w || 657 key->rt_samples != key->dst_samples || 658 key->rt_layout != key->dst_layout) { 659 encode_msaa(key->rt_samples, key->rt_layout); 660 /* Now (X, Y, S) = detile(rt_tiling, offset) */ 661 translate_tiling(rt_tiled_w, key->dst_tiled_w); 662 /* Now (X, Y, S) = detile(dst_tiling, offset) */ 663 decode_msaa(key->dst_samples, key->dst_layout); 664 } 665 666 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)). 667 * 668 * That is: X, Y and S now contain the true coordinates and sample index of 669 * the data that the WM thread should output. 670 * 671 * If we need to kill pixels that are outside the destination rectangle, 672 * now is the time to do it. 673 */ 674 675 if (key->use_kill) 676 kill_if_outside_dst_rect(); 677 678 /* Next, apply a translation to obtain coordinates in the source image. */ 679 translate_dst_to_src(); 680 681 /* If the source image is not multisampled, then we want to fetch sample 682 * number 0, because that's the only sample there is. 683 */ 684 if (key->src_samples == 0) 685 s_is_zero = true; 686 687 /* X, Y, and S are now the coordinates of the pixel in the source image 688 * that we want to texture from. Exception: if we are blending, then S is 689 * irrelevant, because we are going to fetch all samples. 690 */ 691 if (key->blend) { 692 if (brw->intel.gen == 6) { 693 /* Gen6 hardware an automatically blend using the SAMPLE message */ 694 single_to_blend(); 695 sample(texture_data[0]); 696 } else { 697 /* Gen7+ hardware doesn't automaticaly blend. */ 698 manual_blend(key->src_samples); 699 } 700 } else { 701 /* We aren't blending, which means we just want to fetch a single sample 702 * from the source surface. The address that we want to fetch from is 703 * related to the X, Y and S values according to the formula: 704 * 705 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)). 706 * 707 * If the actual tiling and sample count of the source surface are not 708 * the same as the configuration of the texture, then we need to adjust 709 * the coordinates to compensate for the difference. 710 */ 711 if (tex_tiled_w != key->src_tiled_w || 712 key->tex_samples != key->src_samples || 713 key->tex_layout != key->src_layout) { 714 encode_msaa(key->src_samples, key->src_layout); 715 /* Now (X, Y, S) = detile(src_tiling, offset) */ 716 translate_tiling(key->src_tiled_w, tex_tiled_w); 717 /* Now (X, Y, S) = detile(tex_tiling, offset) */ 718 decode_msaa(key->tex_samples, key->tex_layout); 719 } 720 721 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)). 722 * 723 * In other words: X, Y, and S now contain values which, when passed to 724 * the texturing unit, will cause data to be read from the correct 725 * memory location. So we can fetch the texel now. 726 */ 727 if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS) 728 mcs_fetch(); 729 texel_fetch(texture_data[0]); 730 } 731 732 /* Finally, write the fetched (or blended) value to the render target and 733 * terminate the thread. 734 */ 735 render_target_write(); 736 return brw_get_program(&func, program_size); 737} 738 739void 740brw_blorp_blit_program::alloc_push_const_regs(int base_reg) 741{ 742#define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name) 743#define ALLOC_REG(name) \ 744 this->name = \ 745 brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, base_reg, CONST_LOC(name) / 2) 746 747 ALLOC_REG(dst_x0); 748 ALLOC_REG(dst_x1); 749 ALLOC_REG(dst_y0); 750 ALLOC_REG(dst_y1); 751 ALLOC_REG(x_transform.multiplier); 752 ALLOC_REG(x_transform.offset); 753 ALLOC_REG(y_transform.multiplier); 754 ALLOC_REG(y_transform.offset); 755#undef CONST_LOC 756#undef ALLOC_REG 757} 758 759void 760brw_blorp_blit_program::alloc_regs() 761{ 762 int reg = 0; 763 this->R0 = retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW); 764 this->R1 = retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW); 765 prog_data.first_curbe_grf = reg; 766 alloc_push_const_regs(reg); 767 reg += BRW_BLORP_NUM_PUSH_CONST_REGS; 768 for (unsigned i = 0; i < ARRAY_SIZE(texture_data); ++i) { 769 this->texture_data[i] = 770 retype(vec16(brw_vec8_grf(reg, 0)), key->texture_data_type); 771 reg += 8; 772 } 773 this->mcs_data = 774 retype(brw_vec8_grf(reg, 0), BRW_REGISTER_TYPE_UD); reg += 8; 775 for (int i = 0; i < 2; ++i) { 776 this->x_coords[i] 777 = vec16(retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW)); 778 this->y_coords[i] 779 = vec16(retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW)); 780 } 781 this->xy_coord_index = 0; 782 this->sample_index 783 = vec16(retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW)); 784 this->t1 = vec16(retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW)); 785 this->t2 = vec16(retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW)); 786 787 /* Make sure we didn't run out of registers */ 788 assert(reg <= GEN7_MRF_HACK_START); 789 790 int mrf = 2; 791 this->base_mrf = mrf; 792} 793 794/* In the code that follows, X and Y can be used to quickly refer to the 795 * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y 796 * prime") to the inactive elements. 797 * 798 * S can be used to quickly refer to sample_index. 799 */ 800#define X x_coords[xy_coord_index] 801#define Y y_coords[xy_coord_index] 802#define Xp x_coords[!xy_coord_index] 803#define Yp y_coords[!xy_coord_index] 804#define S sample_index 805 806/* Quickly swap the roles of (X, Y) and (Xp, Yp). Saves us from having to do 807 * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation. 808 */ 809#define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index; 810 811/** 812 * Emit code to compute the X and Y coordinates of the pixels being rendered 813 * by this WM invocation. 814 * 815 * Assuming the render target is set up for Y tiling, these (X, Y) values are 816 * related to the address offset where outputs will be written by the formula: 817 * 818 * (X, Y, S) = decode_msaa(detile(offset)). 819 * 820 * (See brw_blorp_blit_program). 821 */ 822void 823brw_blorp_blit_program::compute_frag_coords() 824{ 825 /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0) 826 * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4) 827 * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8) 828 * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12) 829 * 830 * Pixels within a subspan are laid out in this arrangement: 831 * 0 1 832 * 2 3 833 * 834 * So, to compute the coordinates of each pixel, we need to read every 2nd 835 * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value 836 * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4). 837 * In other words, the data we want to access is R1.4<2;4,0>UW. 838 * 839 * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the 840 * result, since pixels n+1 and n+3 are in the right half of the subspan. 841 */ 842 brw_ADD(&func, X, stride(suboffset(R1, 4), 2, 4, 0), brw_imm_v(0x10101010)); 843 844 /* Similarly, Y coordinates for subspans come from R1.2[31:16] through 845 * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th 846 * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of 847 * R1.4<2;4,0>UW). 848 * 849 * And we need to add the repeating sequence (0, 0, 1, 1, ...), since 850 * pixels n+2 and n+3 are in the bottom half of the subspan. 851 */ 852 brw_ADD(&func, Y, stride(suboffset(R1, 5), 2, 4, 0), brw_imm_v(0x11001100)); 853 854 if (key->persample_msaa_dispatch) { 855 switch (key->rt_samples) { 856 case 4: 857 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 4. 858 * Therefore, subspan 0 will represent sample 0, subspan 1 will 859 * represent sample 1, and so on. 860 * 861 * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1, 862 * 1, 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to 863 * populate a temporary variable with the sequence (0, 1, 2, 3), and 864 * then copy from it using vstride=1, width=4, hstride=0. 865 */ 866 brw_MOV(&func, t1, brw_imm_v(0x3210)); 867 brw_MOV(&func, S, stride(t1, 1, 4, 0)); 868 break; 869 case 8: { 870 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 8. 871 * Therefore, subspan 0 will represent sample N (where N is 0 or 4), 872 * subspan 1 will represent sample 1, and so on. We can find the 873 * value of N by looking at R0.0 bits 7:6 ("Starting Sample Pair 874 * Index") and multiplying by two (since samples are always delivered 875 * in pairs). That is, we compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 876 * 0xc0) >> 5. 877 * 878 * Then we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 879 * 2, 2, 2, 3, 3, 3, 3), which we compute by populating a temporary 880 * variable with the sequence (0, 1, 2, 3), and then reading from it 881 * using vstride=1, width=4, hstride=0. 882 */ 883 struct brw_reg t1_ud1 = vec1(retype(t1, BRW_REGISTER_TYPE_UD)); 884 struct brw_reg r0_ud1 = vec1(retype(R0, BRW_REGISTER_TYPE_UD)); 885 brw_AND(&func, t1_ud1, r0_ud1, brw_imm_ud(0xc0)); 886 brw_SHR(&func, t1_ud1, t1_ud1, brw_imm_ud(5)); 887 brw_MOV(&func, t2, brw_imm_v(0x3210)); 888 brw_ADD(&func, S, retype(t1_ud1, BRW_REGISTER_TYPE_UW), 889 stride(t2, 1, 4, 0)); 890 break; 891 } 892 default: 893 assert(!"Unrecognized sample count in " 894 "brw_blorp_blit_program::compute_frag_coords()"); 895 break; 896 } 897 s_is_zero = false; 898 } else { 899 /* Either the destination surface is single-sampled, or the WM will be 900 * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch 901 * per pixel). In either case, it's not meaningful to compute a sample 902 * value. Just set it to 0. 903 */ 904 s_is_zero = true; 905 } 906} 907 908/** 909 * Emit code to compensate for the difference between Y and W tiling. 910 * 911 * This code modifies the X and Y coordinates according to the formula: 912 * 913 * (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S)) 914 * 915 * (See brw_blorp_blit_program). 916 * 917 * It can only translate between W and Y tiling, so new_tiling and old_tiling 918 * are booleans where true represents W tiling and false represents Y tiling. 919 */ 920void 921brw_blorp_blit_program::translate_tiling(bool old_tiled_w, bool new_tiled_w) 922{ 923 if (old_tiled_w == new_tiled_w) 924 return; 925 926 /* In the code that follows, we can safely assume that S = 0, because W 927 * tiling formats always use IMS layout. 928 */ 929 assert(s_is_zero); 930 931 if (new_tiled_w) { 932 /* Given X and Y coordinates that describe an address using Y tiling, 933 * translate to the X and Y coordinates that describe the same address 934 * using W tiling. 935 * 936 * If we break down the low order bits of X and Y, using a 937 * single letter to represent each low-order bit: 938 * 939 * X = A << 7 | 0bBCDEFGH 940 * Y = J << 5 | 0bKLMNP (1) 941 * 942 * Then we can apply the Y tiling formula to see the memory offset being 943 * addressed: 944 * 945 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2) 946 * 947 * If we apply the W detiling formula to this memory location, that the 948 * corresponding X' and Y' coordinates are: 949 * 950 * X' = A << 6 | 0bBCDPFH (3) 951 * Y' = J << 6 | 0bKLMNEG 952 * 953 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'), 954 * we need to make the following computation: 955 * 956 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4) 957 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1 958 */ 959 brw_AND(&func, t1, X, brw_imm_uw(0xfff4)); /* X & ~0b1011 */ 960 brw_SHR(&func, t1, t1, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */ 961 brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */ 962 brw_SHL(&func, t2, t2, brw_imm_uw(2)); /* (Y & 0b1) << 2 */ 963 brw_OR(&func, t1, t1, t2); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */ 964 brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */ 965 brw_OR(&func, Xp, t1, t2); 966 brw_AND(&func, t1, Y, brw_imm_uw(0xfffe)); /* Y & ~0b1 */ 967 brw_SHL(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */ 968 brw_AND(&func, t2, X, brw_imm_uw(8)); /* X & 0b1000 */ 969 brw_SHR(&func, t2, t2, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */ 970 brw_OR(&func, t1, t1, t2); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */ 971 brw_AND(&func, t2, X, brw_imm_uw(2)); /* X & 0b10 */ 972 brw_SHR(&func, t2, t2, brw_imm_uw(1)); /* (X & 0b10) >> 1 */ 973 brw_OR(&func, Yp, t1, t2); 974 SWAP_XY_AND_XPYP(); 975 } else { 976 /* Applying the same logic as above, but in reverse, we obtain the 977 * formulas: 978 * 979 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1 980 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2 981 */ 982 brw_AND(&func, t1, X, brw_imm_uw(0xfffa)); /* X & ~0b101 */ 983 brw_SHL(&func, t1, t1, brw_imm_uw(1)); /* (X & ~0b101) << 1 */ 984 brw_AND(&func, t2, Y, brw_imm_uw(2)); /* Y & 0b10 */ 985 brw_SHL(&func, t2, t2, brw_imm_uw(2)); /* (Y & 0b10) << 2 */ 986 brw_OR(&func, t1, t1, t2); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */ 987 brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */ 988 brw_SHL(&func, t2, t2, brw_imm_uw(1)); /* (Y & 0b1) << 1 */ 989 brw_OR(&func, t1, t1, t2); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 990 | (Y & 0b1) << 1 */ 991 brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */ 992 brw_OR(&func, Xp, t1, t2); 993 brw_AND(&func, t1, Y, brw_imm_uw(0xfffc)); /* Y & ~0b11 */ 994 brw_SHR(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */ 995 brw_AND(&func, t2, X, brw_imm_uw(4)); /* X & 0b100 */ 996 brw_SHR(&func, t2, t2, brw_imm_uw(2)); /* (X & 0b100) >> 2 */ 997 brw_OR(&func, Yp, t1, t2); 998 SWAP_XY_AND_XPYP(); 999 } 1000} 1001 1002/** 1003 * Emit code to compensate for the difference between MSAA and non-MSAA 1004 * surfaces. 1005 * 1006 * This code modifies the X and Y coordinates according to the formula: 1007 * 1008 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S) 1009 * 1010 * (See brw_blorp_blit_program). 1011 */ 1012void 1013brw_blorp_blit_program::encode_msaa(unsigned num_samples, 1014 intel_msaa_layout layout) 1015{ 1016 switch (layout) { 1017 case INTEL_MSAA_LAYOUT_NONE: 1018 /* No translation necessary, and S should already be zero. */ 1019 assert(s_is_zero); 1020 break; 1021 case INTEL_MSAA_LAYOUT_CMS: 1022 /* We can't compensate for compressed layout since at this point in the 1023 * program we haven't read from the MCS buffer. 1024 */ 1025 assert(!"Bad layout in encode_msaa"); 1026 break; 1027 case INTEL_MSAA_LAYOUT_UMS: 1028 /* No translation necessary. */ 1029 break; 1030 case INTEL_MSAA_LAYOUT_IMS: 1031 switch (num_samples) { 1032 case 4: 1033 /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0) 1034 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1) 1035 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1) 1036 */ 1037 brw_AND(&func, t1, X, brw_imm_uw(0xfffe)); /* X & ~0b1 */ 1038 if (!s_is_zero) { 1039 brw_AND(&func, t2, S, brw_imm_uw(1)); /* S & 0b1 */ 1040 brw_OR(&func, t1, t1, t2); /* (X & ~0b1) | (S & 0b1) */ 1041 } 1042 brw_SHL(&func, t1, t1, brw_imm_uw(1)); /* (X & ~0b1) << 1 1043 | (S & 0b1) << 1 */ 1044 brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */ 1045 brw_OR(&func, Xp, t1, t2); 1046 brw_AND(&func, t1, Y, brw_imm_uw(0xfffe)); /* Y & ~0b1 */ 1047 brw_SHL(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */ 1048 if (!s_is_zero) { 1049 brw_AND(&func, t2, S, brw_imm_uw(2)); /* S & 0b10 */ 1050 brw_OR(&func, t1, t1, t2); /* (Y & ~0b1) << 1 | (S & 0b10) */ 1051 } 1052 brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */ 1053 brw_OR(&func, Yp, t1, t2); 1054 break; 1055 case 8: 1056 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0) 1057 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 1058 * | (X & 0b1) 1059 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1) 1060 */ 1061 brw_AND(&func, t1, X, brw_imm_uw(0xfffe)); /* X & ~0b1 */ 1062 brw_SHL(&func, t1, t1, brw_imm_uw(2)); /* (X & ~0b1) << 2 */ 1063 if (!s_is_zero) { 1064 brw_AND(&func, t2, S, brw_imm_uw(4)); /* S & 0b100 */ 1065 brw_OR(&func, t1, t1, t2); /* (X & ~0b1) << 2 | (S & 0b100) */ 1066 brw_AND(&func, t2, S, brw_imm_uw(1)); /* S & 0b1 */ 1067 brw_SHL(&func, t2, t2, brw_imm_uw(1)); /* (S & 0b1) << 1 */ 1068 brw_OR(&func, t1, t1, t2); /* (X & ~0b1) << 2 | (S & 0b100) 1069 | (S & 0b1) << 1 */ 1070 } 1071 brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */ 1072 brw_OR(&func, Xp, t1, t2); 1073 brw_AND(&func, t1, Y, brw_imm_uw(0xfffe)); /* Y & ~0b1 */ 1074 brw_SHL(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */ 1075 if (!s_is_zero) { 1076 brw_AND(&func, t2, S, brw_imm_uw(2)); /* S & 0b10 */ 1077 brw_OR(&func, t1, t1, t2); /* (Y & ~0b1) << 1 | (S & 0b10) */ 1078 } 1079 brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */ 1080 brw_OR(&func, Yp, t1, t2); 1081 break; 1082 } 1083 SWAP_XY_AND_XPYP(); 1084 s_is_zero = true; 1085 break; 1086 } 1087} 1088 1089/** 1090 * Emit code to compensate for the difference between MSAA and non-MSAA 1091 * surfaces. 1092 * 1093 * This code modifies the X and Y coordinates according to the formula: 1094 * 1095 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S) 1096 * 1097 * (See brw_blorp_blit_program). 1098 */ 1099void 1100brw_blorp_blit_program::decode_msaa(unsigned num_samples, 1101 intel_msaa_layout layout) 1102{ 1103 switch (layout) { 1104 case INTEL_MSAA_LAYOUT_NONE: 1105 /* No translation necessary, and S should already be zero. */ 1106 assert(s_is_zero); 1107 break; 1108 case INTEL_MSAA_LAYOUT_CMS: 1109 /* We can't compensate for compressed layout since at this point in the 1110 * program we don't have access to the MCS buffer. 1111 */ 1112 assert(!"Bad layout in encode_msaa"); 1113 break; 1114 case INTEL_MSAA_LAYOUT_UMS: 1115 /* No translation necessary. */ 1116 break; 1117 case INTEL_MSAA_LAYOUT_IMS: 1118 assert(s_is_zero); 1119 switch (num_samples) { 1120 case 4: 1121 /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S) 1122 * where X' = (X & ~0b11) >> 1 | (X & 0b1) 1123 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1) 1124 * S = (Y & 0b10) | (X & 0b10) >> 1 1125 */ 1126 brw_AND(&func, t1, X, brw_imm_uw(0xfffc)); /* X & ~0b11 */ 1127 brw_SHR(&func, t1, t1, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */ 1128 brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */ 1129 brw_OR(&func, Xp, t1, t2); 1130 brw_AND(&func, t1, Y, brw_imm_uw(0xfffc)); /* Y & ~0b11 */ 1131 brw_SHR(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */ 1132 brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */ 1133 brw_OR(&func, Yp, t1, t2); 1134 brw_AND(&func, t1, Y, brw_imm_uw(2)); /* Y & 0b10 */ 1135 brw_AND(&func, t2, X, brw_imm_uw(2)); /* X & 0b10 */ 1136 brw_SHR(&func, t2, t2, brw_imm_uw(1)); /* (X & 0b10) >> 1 */ 1137 brw_OR(&func, S, t1, t2); 1138 break; 1139 case 8: 1140 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S) 1141 * where X' = (X & ~0b111) >> 2 | (X & 0b1) 1142 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1) 1143 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1 1144 */ 1145 brw_AND(&func, t1, X, brw_imm_uw(0xfff8)); /* X & ~0b111 */ 1146 brw_SHR(&func, t1, t1, brw_imm_uw(2)); /* (X & ~0b111) >> 2 */ 1147 brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */ 1148 brw_OR(&func, Xp, t1, t2); 1149 brw_AND(&func, t1, Y, brw_imm_uw(0xfffc)); /* Y & ~0b11 */ 1150 brw_SHR(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */ 1151 brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */ 1152 brw_OR(&func, Yp, t1, t2); 1153 brw_AND(&func, t1, X, brw_imm_uw(4)); /* X & 0b100 */ 1154 brw_AND(&func, t2, Y, brw_imm_uw(2)); /* Y & 0b10 */ 1155 brw_OR(&func, t1, t1, t2); /* (X & 0b100) | (Y & 0b10) */ 1156 brw_AND(&func, t2, X, brw_imm_uw(2)); /* X & 0b10 */ 1157 brw_SHR(&func, t2, t2, brw_imm_uw(1)); /* (X & 0b10) >> 1 */ 1158 brw_OR(&func, S, t1, t2); 1159 break; 1160 } 1161 s_is_zero = false; 1162 SWAP_XY_AND_XPYP(); 1163 break; 1164 } 1165} 1166 1167/** 1168 * Emit code that kills pixels whose X and Y coordinates are outside the 1169 * boundary of the rectangle defined by the push constants (dst_x0, dst_y0, 1170 * dst_x1, dst_y1). 1171 */ 1172void 1173brw_blorp_blit_program::kill_if_outside_dst_rect() 1174{ 1175 struct brw_reg f0 = brw_flag_reg(); 1176 struct brw_reg g1 = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW); 1177 struct brw_reg null16 = vec16(retype(brw_null_reg(), BRW_REGISTER_TYPE_UW)); 1178 1179 brw_CMP(&func, null16, BRW_CONDITIONAL_GE, X, dst_x0); 1180 brw_CMP(&func, null16, BRW_CONDITIONAL_GE, Y, dst_y0); 1181 brw_CMP(&func, null16, BRW_CONDITIONAL_L, X, dst_x1); 1182 brw_CMP(&func, null16, BRW_CONDITIONAL_L, Y, dst_y1); 1183 1184 brw_set_predicate_control(&func, BRW_PREDICATE_NONE); 1185 brw_push_insn_state(&func); 1186 brw_set_mask_control(&func, BRW_MASK_DISABLE); 1187 brw_AND(&func, g1, f0, g1); 1188 brw_pop_insn_state(&func); 1189} 1190 1191/** 1192 * Emit code to translate from destination (X, Y) coordinates to source (X, Y) 1193 * coordinates. 1194 */ 1195void 1196brw_blorp_blit_program::translate_dst_to_src() 1197{ 1198 brw_MUL(&func, Xp, X, x_transform.multiplier); 1199 brw_MUL(&func, Yp, Y, y_transform.multiplier); 1200 brw_ADD(&func, Xp, Xp, x_transform.offset); 1201 brw_ADD(&func, Yp, Yp, y_transform.offset); 1202 SWAP_XY_AND_XPYP(); 1203} 1204 1205/** 1206 * Emit code to transform the X and Y coordinates as needed for blending 1207 * together the different samples in an MSAA texture. 1208 */ 1209void 1210brw_blorp_blit_program::single_to_blend() 1211{ 1212 /* When looking up samples in an MSAA texture using the SAMPLE message, 1213 * Gen6 requires the texture coordinates to be odd integers (so that they 1214 * correspond to the center of a 2x2 block representing the four samples 1215 * that maxe up a pixel). So we need to multiply our X and Y coordinates 1216 * each by 2 and then add 1. 1217 */ 1218 brw_SHL(&func, t1, X, brw_imm_w(1)); 1219 brw_SHL(&func, t2, Y, brw_imm_w(1)); 1220 brw_ADD(&func, Xp, t1, brw_imm_w(1)); 1221 brw_ADD(&func, Yp, t2, brw_imm_w(1)); 1222 SWAP_XY_AND_XPYP(); 1223} 1224 1225 1226/** 1227 * Count the number of trailing 1 bits in the given value. For example: 1228 * 1229 * count_trailing_one_bits(0) == 0 1230 * count_trailing_one_bits(7) == 3 1231 * count_trailing_one_bits(11) == 2 1232 */ 1233inline int count_trailing_one_bits(unsigned value) 1234{ 1235#if defined(__GNUC__) && ((__GNUC__ * 100 + __GNUC_MINOR__) >= 304) /* gcc 3.4 or later */ 1236 return __builtin_ctz(~value); 1237#else 1238 return _mesa_bitcount(value & ~(value + 1)); 1239#endif 1240} 1241 1242 1243void 1244brw_blorp_blit_program::manual_blend(unsigned num_samples) 1245{ 1246 if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS) 1247 mcs_fetch(); 1248 1249 /* We add together samples using a binary tree structure, e.g. for 4x MSAA: 1250 * 1251 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4 1252 * 1253 * This ensures that when all samples have the same value, no numerical 1254 * precision is lost, since each addition operation always adds two equal 1255 * values, and summing two equal floating point values does not lose 1256 * precision. 1257 * 1258 * We perform this computation by treating the texture_data array as a 1259 * stack and performing the following operations: 1260 * 1261 * - push sample 0 onto stack 1262 * - push sample 1 onto stack 1263 * - add top two stack entries 1264 * - push sample 2 onto stack 1265 * - push sample 3 onto stack 1266 * - add top two stack entries 1267 * - add top two stack entries 1268 * - divide top stack entry by 4 1269 * 1270 * Note that after pushing sample i onto the stack, the number of add 1271 * operations we do is equal to the number of trailing 1 bits in i. This 1272 * works provided the total number of samples is a power of two, which it 1273 * always is for i965. 1274 * 1275 * For integer formats, we replace the add operations with average 1276 * operations and skip the final division. 1277 */ 1278 typedef struct brw_instruction *(*brw_op2_ptr)(struct brw_compile *, 1279 struct brw_reg, 1280 struct brw_reg, 1281 struct brw_reg); 1282 brw_op2_ptr combine_op = 1283 key->texture_data_type == BRW_REGISTER_TYPE_F ? brw_ADD : brw_AVG; 1284 unsigned stack_depth = 0; 1285 for (unsigned i = 0; i < num_samples; ++i) { 1286 assert(stack_depth == _mesa_bitcount(i)); /* Loop invariant */ 1287 1288 /* Push sample i onto the stack */ 1289 assert(stack_depth < ARRAY_SIZE(texture_data)); 1290 if (i == 0) { 1291 s_is_zero = true; 1292 } else { 1293 s_is_zero = false; 1294 brw_MOV(&func, S, brw_imm_uw(i)); 1295 } 1296 texel_fetch(texture_data[stack_depth++]); 1297 1298 if (i == 0 && key->tex_layout == INTEL_MSAA_LAYOUT_CMS) { 1299 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface) 1300 * suggests an optimization: 1301 * 1302 * "A simple optimization with probable large return in 1303 * performance is to compare the MCS value to zero (indicating 1304 * all samples are on sample slice 0), and sample only from 1305 * sample slice 0 using ld2dss if MCS is zero." 1306 * 1307 * Note that in the case where the MCS value is zero, sampling from 1308 * sample slice 0 using ld2dss and sampling from sample 0 using 1309 * ld2dms are equivalent (since all samples are on sample slice 0). 1310 * Since we have already sampled from sample 0, all we need to do is 1311 * skip the remaining fetches and averaging if MCS is zero. 1312 */ 1313 brw_CMP(&func, vec16(brw_null_reg()), BRW_CONDITIONAL_NZ, 1314 mcs_data, brw_imm_ud(0)); 1315 brw_IF(&func, BRW_EXECUTE_16); 1316 } 1317 1318 /* Do count_trailing_one_bits(i) times */ 1319 for (int j = count_trailing_one_bits(i); j-- > 0; ) { 1320 assert(stack_depth >= 2); 1321 --stack_depth; 1322 1323 /* TODO: should use a smaller loop bound for non_RGBA formats */ 1324 for (int k = 0; k < 4; ++k) { 1325 combine_op(&func, offset(texture_data[stack_depth - 1], 2*k), 1326 offset(vec8(texture_data[stack_depth - 1]), 2*k), 1327 offset(vec8(texture_data[stack_depth]), 2*k)); 1328 } 1329 } 1330 } 1331 1332 /* We should have just 1 sample on the stack now. */ 1333 assert(stack_depth == 1); 1334 1335 if (key->texture_data_type == BRW_REGISTER_TYPE_F) { 1336 /* Scale the result down by a factor of num_samples */ 1337 /* TODO: should use a smaller loop bound for non-RGBA formats */ 1338 for (int j = 0; j < 4; ++j) { 1339 brw_MUL(&func, offset(texture_data[0], 2*j), 1340 offset(vec8(texture_data[0]), 2*j), 1341 brw_imm_f(1.0/num_samples)); 1342 } 1343 } 1344 1345 if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS) 1346 brw_ENDIF(&func); 1347} 1348 1349/** 1350 * Emit code to look up a value in the texture using the SAMPLE message (which 1351 * does blending of MSAA surfaces). 1352 */ 1353void 1354brw_blorp_blit_program::sample(struct brw_reg dst) 1355{ 1356 static const sampler_message_arg args[2] = { 1357 SAMPLER_MESSAGE_ARG_U_FLOAT, 1358 SAMPLER_MESSAGE_ARG_V_FLOAT 1359 }; 1360 1361 texture_lookup(dst, GEN5_SAMPLER_MESSAGE_SAMPLE, args, ARRAY_SIZE(args)); 1362} 1363 1364/** 1365 * Emit code to look up a value in the texture using the SAMPLE_LD message 1366 * (which does a simple texel fetch). 1367 */ 1368void 1369brw_blorp_blit_program::texel_fetch(struct brw_reg dst) 1370{ 1371 static const sampler_message_arg gen6_args[5] = { 1372 SAMPLER_MESSAGE_ARG_U_INT, 1373 SAMPLER_MESSAGE_ARG_V_INT, 1374 SAMPLER_MESSAGE_ARG_ZERO_INT, /* R */ 1375 SAMPLER_MESSAGE_ARG_ZERO_INT, /* LOD */ 1376 SAMPLER_MESSAGE_ARG_SI_INT 1377 }; 1378 static const sampler_message_arg gen7_ld_args[3] = { 1379 SAMPLER_MESSAGE_ARG_U_INT, 1380 SAMPLER_MESSAGE_ARG_ZERO_INT, /* LOD */ 1381 SAMPLER_MESSAGE_ARG_V_INT 1382 }; 1383 static const sampler_message_arg gen7_ld2dss_args[3] = { 1384 SAMPLER_MESSAGE_ARG_SI_INT, 1385 SAMPLER_MESSAGE_ARG_U_INT, 1386 SAMPLER_MESSAGE_ARG_V_INT 1387 }; 1388 static const sampler_message_arg gen7_ld2dms_args[4] = { 1389 SAMPLER_MESSAGE_ARG_SI_INT, 1390 SAMPLER_MESSAGE_ARG_MCS_INT, 1391 SAMPLER_MESSAGE_ARG_U_INT, 1392 SAMPLER_MESSAGE_ARG_V_INT 1393 }; 1394 1395 switch (brw->intel.gen) { 1396 case 6: 1397 texture_lookup(dst, GEN5_SAMPLER_MESSAGE_SAMPLE_LD, gen6_args, 1398 s_is_zero ? 2 : 5); 1399 break; 1400 case 7: 1401 switch (key->tex_layout) { 1402 case INTEL_MSAA_LAYOUT_IMS: 1403 /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage 1404 * Format): 1405 * 1406 * If this field is MSFMT_DEPTH_STENCIL 1407 * [a.k.a. INTEL_MSAA_LAYOUT_IMS], the only sampling engine 1408 * messages allowed are "ld2dms", "resinfo", and "sampleinfo". 1409 * 1410 * So fall through to emit the same message as we use for 1411 * INTEL_MSAA_LAYOUT_CMS. 1412 */ 1413 case INTEL_MSAA_LAYOUT_CMS: 1414 texture_lookup(dst, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS, 1415 gen7_ld2dms_args, ARRAY_SIZE(gen7_ld2dms_args)); 1416 break; 1417 case INTEL_MSAA_LAYOUT_UMS: 1418 texture_lookup(dst, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS, 1419 gen7_ld2dss_args, ARRAY_SIZE(gen7_ld2dss_args)); 1420 break; 1421 case INTEL_MSAA_LAYOUT_NONE: 1422 assert(s_is_zero); 1423 texture_lookup(dst, GEN5_SAMPLER_MESSAGE_SAMPLE_LD, gen7_ld_args, 1424 ARRAY_SIZE(gen7_ld_args)); 1425 break; 1426 } 1427 break; 1428 default: 1429 assert(!"Should not get here."); 1430 break; 1431 }; 1432} 1433 1434void 1435brw_blorp_blit_program::mcs_fetch() 1436{ 1437 static const sampler_message_arg gen7_ld_mcs_args[2] = { 1438 SAMPLER_MESSAGE_ARG_U_INT, 1439 SAMPLER_MESSAGE_ARG_V_INT 1440 }; 1441 texture_lookup(vec16(mcs_data), GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS, 1442 gen7_ld_mcs_args, ARRAY_SIZE(gen7_ld_mcs_args)); 1443} 1444 1445void 1446brw_blorp_blit_program::expand_to_32_bits(struct brw_reg src, 1447 struct brw_reg dst) 1448{ 1449 brw_MOV(&func, vec8(dst), vec8(src)); 1450 brw_set_compression_control(&func, BRW_COMPRESSION_2NDHALF); 1451 brw_MOV(&func, offset(vec8(dst), 1), suboffset(vec8(src), 8)); 1452 brw_set_compression_control(&func, BRW_COMPRESSION_NONE); 1453} 1454 1455void 1456brw_blorp_blit_program::texture_lookup(struct brw_reg dst, 1457 GLuint msg_type, 1458 const sampler_message_arg *args, 1459 int num_args) 1460{ 1461 struct brw_reg mrf = 1462 retype(vec16(brw_message_reg(base_mrf)), BRW_REGISTER_TYPE_UD); 1463 for (int arg = 0; arg < num_args; ++arg) { 1464 switch (args[arg]) { 1465 case SAMPLER_MESSAGE_ARG_U_FLOAT: 1466 expand_to_32_bits(X, retype(mrf, BRW_REGISTER_TYPE_F)); 1467 break; 1468 case SAMPLER_MESSAGE_ARG_V_FLOAT: 1469 expand_to_32_bits(Y, retype(mrf, BRW_REGISTER_TYPE_F)); 1470 break; 1471 case SAMPLER_MESSAGE_ARG_U_INT: 1472 expand_to_32_bits(X, mrf); 1473 break; 1474 case SAMPLER_MESSAGE_ARG_V_INT: 1475 expand_to_32_bits(Y, mrf); 1476 break; 1477 case SAMPLER_MESSAGE_ARG_SI_INT: 1478 /* Note: on Gen7, this code may be reached with s_is_zero==true 1479 * because in Gen7's ld2dss message, the sample index is the first 1480 * argument. When this happens, we need to move a 0 into the 1481 * appropriate message register. 1482 */ 1483 if (s_is_zero) 1484 brw_MOV(&func, mrf, brw_imm_ud(0)); 1485 else 1486 expand_to_32_bits(S, mrf); 1487 break; 1488 case SAMPLER_MESSAGE_ARG_MCS_INT: 1489 switch (key->tex_layout) { 1490 case INTEL_MSAA_LAYOUT_CMS: 1491 brw_MOV(&func, mrf, mcs_data); 1492 break; 1493 case INTEL_MSAA_LAYOUT_IMS: 1494 /* When sampling from an IMS surface, MCS data is not relevant, 1495 * and the hardware ignores it. So don't bother populating it. 1496 */ 1497 break; 1498 default: 1499 /* We shouldn't be trying to send MCS data with any other 1500 * layouts. 1501 */ 1502 assert (!"Unsupported layout for MCS data"); 1503 break; 1504 } 1505 break; 1506 case SAMPLER_MESSAGE_ARG_ZERO_INT: 1507 brw_MOV(&func, mrf, brw_imm_ud(0)); 1508 break; 1509 } 1510 mrf.nr += 2; 1511 } 1512 1513 brw_SAMPLE(&func, 1514 retype(dst, BRW_REGISTER_TYPE_UW) /* dest */, 1515 base_mrf /* msg_reg_nr */, 1516 brw_message_reg(base_mrf) /* src0 */, 1517 BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX, 1518 0 /* sampler */, 1519 WRITEMASK_XYZW, 1520 msg_type, 1521 8 /* response_length. TODO: should be smaller for non-RGBA formats? */, 1522 mrf.nr - base_mrf /* msg_length */, 1523 0 /* header_present */, 1524 BRW_SAMPLER_SIMD_MODE_SIMD16, 1525 BRW_SAMPLER_RETURN_FORMAT_FLOAT32); 1526} 1527 1528#undef X 1529#undef Y 1530#undef U 1531#undef V 1532#undef S 1533#undef SWAP_XY_AND_XPYP 1534 1535void 1536brw_blorp_blit_program::render_target_write() 1537{ 1538 struct brw_reg mrf_rt_write = 1539 retype(vec16(brw_message_reg(base_mrf)), key->texture_data_type); 1540 int mrf_offset = 0; 1541 1542 /* If we may have killed pixels, then we need to send R0 and R1 in a header 1543 * so that the render target knows which pixels we killed. 1544 */ 1545 bool use_header = key->use_kill; 1546 if (use_header) { 1547 /* Copy R0/1 to MRF */ 1548 brw_MOV(&func, retype(mrf_rt_write, BRW_REGISTER_TYPE_UD), 1549 retype(R0, BRW_REGISTER_TYPE_UD)); 1550 mrf_offset += 2; 1551 } 1552 1553 /* Copy texture data to MRFs */ 1554 for (int i = 0; i < 4; ++i) { 1555 /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */ 1556 brw_MOV(&func, offset(mrf_rt_write, mrf_offset), 1557 offset(vec8(texture_data[0]), 2*i)); 1558 mrf_offset += 2; 1559 } 1560 1561 /* Now write to the render target and terminate the thread */ 1562 brw_fb_WRITE(&func, 1563 16 /* dispatch_width */, 1564 base_mrf /* msg_reg_nr */, 1565 mrf_rt_write /* src0 */, 1566 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE, 1567 BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX, 1568 mrf_offset /* msg_length. TODO: Should be smaller for non-RGBA formats. */, 1569 0 /* response_length */, 1570 true /* eot */, 1571 use_header); 1572} 1573 1574 1575void 1576brw_blorp_coord_transform_params::setup(GLuint src0, GLuint dst0, GLuint dst1, 1577 bool mirror) 1578{ 1579 if (!mirror) { 1580 /* When not mirroring a coordinate (say, X), we need: 1581 * x' - src_x0 = x - dst_x0 1582 * Therefore: 1583 * x' = 1*x + (src_x0 - dst_x0) 1584 */ 1585 multiplier = 1; 1586 offset = src0 - dst0; 1587 } else { 1588 /* When mirroring X we need: 1589 * x' - src_x0 = dst_x1 - x - 1 1590 * Therefore: 1591 * x' = -1*x + (src_x0 + dst_x1 - 1) 1592 */ 1593 multiplier = -1; 1594 offset = src0 + dst1 - 1; 1595 } 1596} 1597 1598 1599/** 1600 * Determine which MSAA layout the GPU pipeline should be configured for, 1601 * based on the chip generation, the number of samples, and the true layout of 1602 * the image in memory. 1603 */ 1604inline intel_msaa_layout 1605compute_msaa_layout_for_pipeline(struct brw_context *brw, unsigned num_samples, 1606 intel_msaa_layout true_layout) 1607{ 1608 if (num_samples <= 1) { 1609 /* When configuring the GPU for non-MSAA, we can still accommodate IMS 1610 * format buffers, by transforming coordinates appropriately. 1611 */ 1612 assert(true_layout == INTEL_MSAA_LAYOUT_NONE || 1613 true_layout == INTEL_MSAA_LAYOUT_IMS); 1614 return INTEL_MSAA_LAYOUT_NONE; 1615 } else { 1616 assert(true_layout != INTEL_MSAA_LAYOUT_NONE); 1617 } 1618 1619 /* Prior to Gen7, all MSAA surfaces use IMS layout. */ 1620 if (brw->intel.gen == 6) { 1621 assert(true_layout == INTEL_MSAA_LAYOUT_IMS); 1622 } 1623 1624 return true_layout; 1625} 1626 1627 1628brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context *brw, 1629 struct intel_mipmap_tree *src_mt, 1630 unsigned src_level, unsigned src_layer, 1631 struct intel_mipmap_tree *dst_mt, 1632 unsigned dst_level, unsigned dst_layer, 1633 GLuint src_x0, GLuint src_y0, 1634 GLuint dst_x0, GLuint dst_y0, 1635 GLuint dst_x1, GLuint dst_y1, 1636 bool mirror_x, bool mirror_y) 1637{ 1638 src.set(brw, src_mt, src_level, src_layer); 1639 dst.set(brw, dst_mt, dst_level, dst_layer); 1640 1641 use_wm_prog = true; 1642 memset(&wm_prog_key, 0, sizeof(wm_prog_key)); 1643 1644 /* texture_data_type indicates the register type that should be used to 1645 * manipulate texture data. 1646 */ 1647 switch (_mesa_get_format_datatype(src_mt->format)) { 1648 case GL_UNSIGNED_NORMALIZED: 1649 case GL_SIGNED_NORMALIZED: 1650 case GL_FLOAT: 1651 wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_F; 1652 break; 1653 case GL_UNSIGNED_INT: 1654 if (src_mt->format == MESA_FORMAT_S8) { 1655 /* We process stencil as though it's an unsigned normalized color */ 1656 wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_F; 1657 } else { 1658 wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_UD; 1659 } 1660 break; 1661 case GL_INT: 1662 wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_D; 1663 break; 1664 default: 1665 assert(!"Unrecognized blorp format"); 1666 break; 1667 } 1668 1669 if (brw->intel.gen > 6) { 1670 /* Gen7's rendering hardware only supports the IMS layout for depth and 1671 * stencil render targets. Blorp always maps its destination surface as 1672 * a color render target (even if it's actually a depth or stencil 1673 * buffer). So if the destination is IMS, we'll have to map it as a 1674 * single-sampled texture and interleave the samples ourselves. 1675 */ 1676 if (dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) 1677 dst.num_samples = 0; 1678 } 1679 1680 if (dst.map_stencil_as_y_tiled && dst.num_samples > 1) { 1681 /* If the destination surface is a W-tiled multisampled stencil buffer 1682 * that we're mapping as Y tiled, then we need to arrange for the WM 1683 * program to run once per sample rather than once per pixel, because 1684 * the memory layout of related samples doesn't match between W and Y 1685 * tiling. 1686 */ 1687 wm_prog_key.persample_msaa_dispatch = true; 1688 } 1689 1690 if (src.num_samples > 0 && dst.num_samples > 1) { 1691 /* We are blitting from a multisample buffer to a multisample buffer, so 1692 * we must preserve samples within a pixel. This means we have to 1693 * arrange for the WM program to run once per sample rather than once 1694 * per pixel. 1695 */ 1696 wm_prog_key.persample_msaa_dispatch = true; 1697 } 1698 1699 /* The render path must be configured to use the same number of samples as 1700 * the destination buffer. 1701 */ 1702 num_samples = dst.num_samples; 1703 1704 GLenum base_format = _mesa_get_format_base_format(src_mt->format); 1705 if (base_format != GL_DEPTH_COMPONENT && /* TODO: what about depth/stencil? */ 1706 base_format != GL_STENCIL_INDEX && 1707 src_mt->num_samples > 1 && dst_mt->num_samples <= 1) { 1708 /* We are downsampling a color buffer, so blend. */ 1709 wm_prog_key.blend = true; 1710 } 1711 1712 /* src_samples and dst_samples are the true sample counts */ 1713 wm_prog_key.src_samples = src_mt->num_samples; 1714 wm_prog_key.dst_samples = dst_mt->num_samples; 1715 1716 /* tex_samples and rt_samples are the sample counts that are set up in 1717 * SURFACE_STATE. 1718 */ 1719 wm_prog_key.tex_samples = src.num_samples; 1720 wm_prog_key.rt_samples = dst.num_samples; 1721 1722 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will 1723 * use to access the source and destination surfaces. 1724 */ 1725 wm_prog_key.tex_layout = 1726 compute_msaa_layout_for_pipeline(brw, src.num_samples, src.msaa_layout); 1727 wm_prog_key.rt_layout = 1728 compute_msaa_layout_for_pipeline(brw, dst.num_samples, dst.msaa_layout); 1729 1730 /* src_layout and dst_layout indicate the true MSAA layout used by src and 1731 * dst. 1732 */ 1733 wm_prog_key.src_layout = src_mt->msaa_layout; 1734 wm_prog_key.dst_layout = dst_mt->msaa_layout; 1735 1736 wm_prog_key.src_tiled_w = src.map_stencil_as_y_tiled; 1737 wm_prog_key.dst_tiled_w = dst.map_stencil_as_y_tiled; 1738 x0 = wm_push_consts.dst_x0 = dst_x0; 1739 y0 = wm_push_consts.dst_y0 = dst_y0; 1740 x1 = wm_push_consts.dst_x1 = dst_x1; 1741 y1 = wm_push_consts.dst_y1 = dst_y1; 1742 wm_push_consts.x_transform.setup(src_x0, dst_x0, dst_x1, mirror_x); 1743 wm_push_consts.y_transform.setup(src_y0, dst_y0, dst_y1, mirror_y); 1744 1745 if (dst.num_samples <= 1 && dst_mt->num_samples > 1) { 1746 /* We must expand the rectangle we send through the rendering pipeline, 1747 * to account for the fact that we are mapping the destination region as 1748 * single-sampled when it is in fact multisampled. We must also align 1749 * it to a multiple of the multisampling pattern, because the 1750 * differences between multisampled and single-sampled surface formats 1751 * will mean that pixels are scrambled within the multisampling pattern. 1752 * TODO: what if this makes the coordinates too large? 1753 * 1754 * Note: this only works if the destination surface uses the IMS layout. 1755 * If it's UMS, then we have no choice but to set up the rendering 1756 * pipeline as multisampled. 1757 */ 1758 assert(dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS); 1759 switch (dst_mt->num_samples) { 1760 case 4: 1761 x0 = ROUND_DOWN_TO(x0 * 2, 4); 1762 y0 = ROUND_DOWN_TO(y0 * 2, 4); 1763 x1 = ALIGN(x1 * 2, 4); 1764 y1 = ALIGN(y1 * 2, 4); 1765 break; 1766 case 8: 1767 x0 = ROUND_DOWN_TO(x0 * 4, 8); 1768 y0 = ROUND_DOWN_TO(y0 * 2, 4); 1769 x1 = ALIGN(x1 * 4, 8); 1770 y1 = ALIGN(y1 * 2, 4); 1771 break; 1772 default: 1773 assert(!"Unrecognized sample count in brw_blorp_blit_params ctor"); 1774 break; 1775 } 1776 wm_prog_key.use_kill = true; 1777 } 1778 1779 if (dst.map_stencil_as_y_tiled) { 1780 /* We must modify the rectangle we send through the rendering pipeline 1781 * (and the size of the destination surface), to account for the fact 1782 * that we are mapping it as Y-tiled when it is in fact W-tiled. Y 1783 * tiles have dimensions 128x32 whereas W tiles have dimensions 64x64. 1784 * We must also align it to a multiple of the tile size, because the 1785 * differences between W and Y tiling formats will mean that pixels are 1786 * scrambled within the tile. 1787 * 1788 * TODO: what if this makes the coordinates (or the texture size) too 1789 * large? 1790 */ 1791 const unsigned x_align = 64, y_align = 64; 1792 x0 = ROUND_DOWN_TO(x0, x_align) * 2; 1793 y0 = ROUND_DOWN_TO(y0, y_align) / 2; 1794 x1 = ALIGN(x1, x_align) * 2; 1795 y1 = ALIGN(y1, y_align) / 2; 1796 dst.width *= 2; 1797 dst.height /= 2; 1798 wm_prog_key.use_kill = true; 1799 } 1800 1801 if (src.map_stencil_as_y_tiled) { 1802 /* We must modify the size of the source surface to account for the fact 1803 * that we are mapping it as Y-tiled when it is in fact W tiled. 1804 * 1805 * TODO: what if this makes the texture size too large? 1806 */ 1807 src.width *= 2; 1808 src.height /= 2; 1809 } 1810} 1811 1812uint32_t 1813brw_blorp_blit_params::get_wm_prog(struct brw_context *brw, 1814 brw_blorp_prog_data **prog_data) const 1815{ 1816 uint32_t prog_offset; 1817 if (!brw_search_cache(&brw->cache, BRW_BLORP_BLIT_PROG, 1818 &this->wm_prog_key, sizeof(this->wm_prog_key), 1819 &prog_offset, prog_data)) { 1820 brw_blorp_blit_program prog(brw, &this->wm_prog_key); 1821 GLuint program_size; 1822 const GLuint *program = prog.compile(brw, &program_size); 1823 brw_upload_cache(&brw->cache, BRW_BLORP_BLIT_PROG, 1824 &this->wm_prog_key, sizeof(this->wm_prog_key), 1825 program, program_size, 1826 &prog.prog_data, sizeof(prog.prog_data), 1827 &prog_offset, prog_data); 1828 } 1829 return prog_offset; 1830} 1831