brw_fs_visitor.cpp revision 2f0edc60f4bd2ae5999a6afa656e3bb3f181bf0f
1/* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24/** @file brw_fs_visitor.cpp 25 * 26 * This file supports generating the FS LIR from the GLSL IR. The LIR 27 * makes it easier to do backend-specific optimizations than doing so 28 * in the GLSL IR or in the native code. 29 */ 30extern "C" { 31 32#include <sys/types.h> 33 34#include "main/macros.h" 35#include "main/shaderobj.h" 36#include "main/uniforms.h" 37#include "program/prog_parameter.h" 38#include "program/prog_print.h" 39#include "program/prog_optimize.h" 40#include "program/register_allocate.h" 41#include "program/sampler.h" 42#include "program/hash_table.h" 43#include "brw_context.h" 44#include "brw_eu.h" 45#include "brw_wm.h" 46} 47#include "brw_shader.h" 48#include "brw_fs.h" 49#include "glsl/glsl_types.h" 50#include "glsl/ir_optimization.h" 51#include "glsl/ir_print_visitor.h" 52 53void 54fs_visitor::visit(ir_variable *ir) 55{ 56 fs_reg *reg = NULL; 57 58 if (variable_storage(ir)) 59 return; 60 61 if (strcmp(ir->name, "gl_FragColor") == 0) { 62 this->frag_color = ir; 63 } else if (strcmp(ir->name, "gl_FragData") == 0) { 64 this->frag_data = ir; 65 } else if (strcmp(ir->name, "gl_FragDepth") == 0) { 66 this->frag_depth = ir; 67 } 68 69 if (ir->mode == ir_var_in) { 70 if (!strcmp(ir->name, "gl_FragCoord")) { 71 reg = emit_fragcoord_interpolation(ir); 72 } else if (!strcmp(ir->name, "gl_FrontFacing")) { 73 reg = emit_frontfacing_interpolation(ir); 74 } else { 75 reg = emit_general_interpolation(ir); 76 } 77 assert(reg); 78 hash_table_insert(this->variable_ht, reg, ir); 79 return; 80 } 81 82 if (ir->mode == ir_var_uniform) { 83 int param_index = c->prog_data.nr_params; 84 85 if (c->dispatch_width == 16) { 86 if (!variable_storage(ir)) { 87 fail("Failed to find uniform '%s' in 16-wide\n", ir->name); 88 } 89 return; 90 } 91 92 if (!strncmp(ir->name, "gl_", 3)) { 93 setup_builtin_uniform_values(ir); 94 } else { 95 setup_uniform_values(ir->location, ir->type); 96 } 97 98 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index); 99 reg->type = brw_type_for_base_type(ir->type); 100 } 101 102 if (!reg) 103 reg = new(this->mem_ctx) fs_reg(this, ir->type); 104 105 hash_table_insert(this->variable_ht, reg, ir); 106} 107 108void 109fs_visitor::visit(ir_dereference_variable *ir) 110{ 111 fs_reg *reg = variable_storage(ir->var); 112 this->result = *reg; 113} 114 115void 116fs_visitor::visit(ir_dereference_record *ir) 117{ 118 const glsl_type *struct_type = ir->record->type; 119 120 ir->record->accept(this); 121 122 unsigned int offset = 0; 123 for (unsigned int i = 0; i < struct_type->length; i++) { 124 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0) 125 break; 126 offset += type_size(struct_type->fields.structure[i].type); 127 } 128 this->result.reg_offset += offset; 129 this->result.type = brw_type_for_base_type(ir->type); 130} 131 132void 133fs_visitor::visit(ir_dereference_array *ir) 134{ 135 ir_constant *index; 136 int element_size; 137 138 ir->array->accept(this); 139 index = ir->array_index->as_constant(); 140 141 element_size = type_size(ir->type); 142 this->result.type = brw_type_for_base_type(ir->type); 143 144 if (index) { 145 assert(this->result.file == UNIFORM || this->result.file == GRF); 146 this->result.reg_offset += index->value.i[0] * element_size; 147 } else { 148 assert(!"FINISHME: non-constant array element"); 149 } 150} 151 152/* Instruction selection: Produce a MOV.sat instead of 153 * MIN(MAX(val, 0), 1) when possible. 154 */ 155bool 156fs_visitor::try_emit_saturate(ir_expression *ir) 157{ 158 ir_rvalue *sat_val = ir->as_rvalue_to_saturate(); 159 160 if (!sat_val) 161 return false; 162 163 sat_val->accept(this); 164 fs_reg src = this->result; 165 166 this->result = fs_reg(this, ir->type); 167 fs_inst *inst = emit(BRW_OPCODE_MOV, this->result, src); 168 inst->saturate = true; 169 170 return true; 171} 172 173void 174fs_visitor::visit(ir_expression *ir) 175{ 176 unsigned int operand; 177 fs_reg op[2], temp; 178 fs_inst *inst; 179 180 assert(ir->get_num_operands() <= 2); 181 182 if (try_emit_saturate(ir)) 183 return; 184 185 for (operand = 0; operand < ir->get_num_operands(); operand++) { 186 ir->operands[operand]->accept(this); 187 if (this->result.file == BAD_FILE) { 188 ir_print_visitor v; 189 fail("Failed to get tree for expression operand:\n"); 190 ir->operands[operand]->accept(&v); 191 } 192 op[operand] = this->result; 193 194 /* Matrix expression operands should have been broken down to vector 195 * operations already. 196 */ 197 assert(!ir->operands[operand]->type->is_matrix()); 198 /* And then those vector operands should have been broken down to scalar. 199 */ 200 assert(!ir->operands[operand]->type->is_vector()); 201 } 202 203 /* Storage for our result. If our result goes into an assignment, it will 204 * just get copy-propagated out, so no worries. 205 */ 206 this->result = fs_reg(this, ir->type); 207 208 switch (ir->operation) { 209 case ir_unop_logic_not: 210 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is 211 * ones complement of the whole register, not just bit 0. 212 */ 213 emit(BRW_OPCODE_XOR, this->result, op[0], fs_reg(1)); 214 break; 215 case ir_unop_neg: 216 op[0].negate = !op[0].negate; 217 this->result = op[0]; 218 break; 219 case ir_unop_abs: 220 op[0].abs = true; 221 op[0].negate = false; 222 this->result = op[0]; 223 break; 224 case ir_unop_sign: 225 temp = fs_reg(this, ir->type); 226 227 emit(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)); 228 229 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 230 inst->conditional_mod = BRW_CONDITIONAL_G; 231 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)); 232 inst->predicated = true; 233 234 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 235 inst->conditional_mod = BRW_CONDITIONAL_L; 236 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)); 237 inst->predicated = true; 238 239 break; 240 case ir_unop_rcp: 241 emit_math(SHADER_OPCODE_RCP, this->result, op[0]); 242 break; 243 244 case ir_unop_exp2: 245 emit_math(SHADER_OPCODE_EXP2, this->result, op[0]); 246 break; 247 case ir_unop_log2: 248 emit_math(SHADER_OPCODE_LOG2, this->result, op[0]); 249 break; 250 case ir_unop_exp: 251 case ir_unop_log: 252 assert(!"not reached: should be handled by ir_explog_to_explog2"); 253 break; 254 case ir_unop_sin: 255 case ir_unop_sin_reduced: 256 emit_math(SHADER_OPCODE_SIN, this->result, op[0]); 257 break; 258 case ir_unop_cos: 259 case ir_unop_cos_reduced: 260 emit_math(SHADER_OPCODE_COS, this->result, op[0]); 261 break; 262 263 case ir_unop_dFdx: 264 emit(FS_OPCODE_DDX, this->result, op[0]); 265 break; 266 case ir_unop_dFdy: 267 emit(FS_OPCODE_DDY, this->result, op[0]); 268 break; 269 270 case ir_binop_add: 271 emit(BRW_OPCODE_ADD, this->result, op[0], op[1]); 272 break; 273 case ir_binop_sub: 274 assert(!"not reached: should be handled by ir_sub_to_add_neg"); 275 break; 276 277 case ir_binop_mul: 278 if (ir->type->is_integer()) { 279 /* For integer multiplication, the MUL uses the low 16 bits 280 * of one of the operands (src0 on gen6, src1 on gen7). The 281 * MACH accumulates in the contribution of the upper 16 bits 282 * of that operand. 283 * 284 * FINISHME: Emit just the MUL if we know an operand is small 285 * enough. 286 */ 287 struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_D); 288 289 emit(BRW_OPCODE_MUL, acc, op[0], op[1]); 290 emit(BRW_OPCODE_MACH, reg_null_d, op[0], op[1]); 291 emit(BRW_OPCODE_MOV, this->result, fs_reg(acc)); 292 } else { 293 emit(BRW_OPCODE_MUL, this->result, op[0], op[1]); 294 } 295 break; 296 case ir_binop_div: 297 assert(!"not reached: should be handled by ir_div_to_mul_rcp"); 298 break; 299 case ir_binop_mod: 300 assert(!"ir_binop_mod should have been converted to b * fract(a/b)"); 301 break; 302 303 case ir_binop_less: 304 case ir_binop_greater: 305 case ir_binop_lequal: 306 case ir_binop_gequal: 307 case ir_binop_equal: 308 case ir_binop_all_equal: 309 case ir_binop_nequal: 310 case ir_binop_any_nequal: 311 temp = this->result; 312 /* original gen4 does implicit conversion before comparison. */ 313 if (intel->gen < 5) 314 temp.type = op[0].type; 315 316 inst = emit(BRW_OPCODE_CMP, temp, op[0], op[1]); 317 inst->conditional_mod = brw_conditional_for_comparison(ir->operation); 318 emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)); 319 break; 320 321 case ir_binop_logic_xor: 322 emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 323 break; 324 325 case ir_binop_logic_or: 326 emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 327 break; 328 329 case ir_binop_logic_and: 330 emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 331 break; 332 333 case ir_binop_dot: 334 case ir_unop_any: 335 assert(!"not reached: should be handled by brw_fs_channel_expressions"); 336 break; 337 338 case ir_unop_noise: 339 assert(!"not reached: should be handled by lower_noise"); 340 break; 341 342 case ir_quadop_vector: 343 assert(!"not reached: should be handled by lower_quadop_vector"); 344 break; 345 346 case ir_unop_sqrt: 347 emit_math(SHADER_OPCODE_SQRT, this->result, op[0]); 348 break; 349 350 case ir_unop_rsq: 351 emit_math(SHADER_OPCODE_RSQ, this->result, op[0]); 352 break; 353 354 case ir_unop_i2u: 355 op[0].type = BRW_REGISTER_TYPE_UD; 356 this->result = op[0]; 357 break; 358 case ir_unop_u2i: 359 op[0].type = BRW_REGISTER_TYPE_D; 360 this->result = op[0]; 361 break; 362 case ir_unop_i2f: 363 case ir_unop_b2f: 364 case ir_unop_b2i: 365 case ir_unop_f2i: 366 emit(BRW_OPCODE_MOV, this->result, op[0]); 367 break; 368 case ir_unop_f2b: 369 case ir_unop_i2b: 370 temp = this->result; 371 /* original gen4 does implicit conversion before comparison. */ 372 if (intel->gen < 5) 373 temp.type = op[0].type; 374 375 inst = emit(BRW_OPCODE_CMP, temp, op[0], fs_reg(0.0f)); 376 inst->conditional_mod = BRW_CONDITIONAL_NZ; 377 inst = emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(1)); 378 break; 379 380 case ir_unop_trunc: 381 emit(BRW_OPCODE_RNDZ, this->result, op[0]); 382 break; 383 case ir_unop_ceil: 384 op[0].negate = !op[0].negate; 385 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 386 this->result.negate = true; 387 break; 388 case ir_unop_floor: 389 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 390 break; 391 case ir_unop_fract: 392 inst = emit(BRW_OPCODE_FRC, this->result, op[0]); 393 break; 394 case ir_unop_round_even: 395 emit(BRW_OPCODE_RNDE, this->result, op[0]); 396 break; 397 398 case ir_binop_min: 399 if (intel->gen >= 6) { 400 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 401 inst->conditional_mod = BRW_CONDITIONAL_L; 402 } else { 403 /* Unalias the destination */ 404 this->result = fs_reg(this, ir->type); 405 406 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 407 inst->conditional_mod = BRW_CONDITIONAL_L; 408 409 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 410 inst->predicated = true; 411 } 412 break; 413 case ir_binop_max: 414 if (intel->gen >= 6) { 415 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 416 inst->conditional_mod = BRW_CONDITIONAL_GE; 417 } else { 418 /* Unalias the destination */ 419 this->result = fs_reg(this, ir->type); 420 421 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 422 inst->conditional_mod = BRW_CONDITIONAL_G; 423 424 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 425 inst->predicated = true; 426 } 427 break; 428 429 case ir_binop_pow: 430 emit_math(SHADER_OPCODE_POW, this->result, op[0], op[1]); 431 break; 432 433 case ir_unop_bit_not: 434 inst = emit(BRW_OPCODE_NOT, this->result, op[0]); 435 break; 436 case ir_binop_bit_and: 437 inst = emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 438 break; 439 case ir_binop_bit_xor: 440 inst = emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 441 break; 442 case ir_binop_bit_or: 443 inst = emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 444 break; 445 446 case ir_unop_u2f: 447 case ir_binop_lshift: 448 case ir_binop_rshift: 449 assert(!"GLSL 1.30 features unsupported"); 450 break; 451 } 452} 453 454void 455fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r, 456 const glsl_type *type, bool predicated) 457{ 458 switch (type->base_type) { 459 case GLSL_TYPE_FLOAT: 460 case GLSL_TYPE_UINT: 461 case GLSL_TYPE_INT: 462 case GLSL_TYPE_BOOL: 463 for (unsigned int i = 0; i < type->components(); i++) { 464 l.type = brw_type_for_base_type(type); 465 r.type = brw_type_for_base_type(type); 466 467 if (predicated || !l.equals(&r)) { 468 fs_inst *inst = emit(BRW_OPCODE_MOV, l, r); 469 inst->predicated = predicated; 470 } 471 472 l.reg_offset++; 473 r.reg_offset++; 474 } 475 break; 476 case GLSL_TYPE_ARRAY: 477 for (unsigned int i = 0; i < type->length; i++) { 478 emit_assignment_writes(l, r, type->fields.array, predicated); 479 } 480 break; 481 482 case GLSL_TYPE_STRUCT: 483 for (unsigned int i = 0; i < type->length; i++) { 484 emit_assignment_writes(l, r, type->fields.structure[i].type, 485 predicated); 486 } 487 break; 488 489 case GLSL_TYPE_SAMPLER: 490 break; 491 492 default: 493 assert(!"not reached"); 494 break; 495 } 496} 497 498/* If the RHS processing resulted in an instruction generating a 499 * temporary value, and it would be easy to rewrite the instruction to 500 * generate its result right into the LHS instead, do so. This ends 501 * up reliably removing instructions where it can be tricky to do so 502 * later without real UD chain information. 503 */ 504bool 505fs_visitor::try_rewrite_rhs_to_dst(ir_assignment *ir, 506 fs_reg dst, 507 fs_reg src, 508 fs_inst *pre_rhs_inst, 509 fs_inst *last_rhs_inst) 510{ 511 if (pre_rhs_inst == last_rhs_inst) 512 return false; /* No instructions generated to work with. */ 513 514 /* Only attempt if we're doing a direct assignment. */ 515 if (ir->condition || 516 !(ir->lhs->type->is_scalar() || 517 (ir->lhs->type->is_vector() && 518 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1))) 519 return false; 520 521 /* Make sure the last instruction generated our source reg. */ 522 if (last_rhs_inst->predicated || 523 last_rhs_inst->force_uncompressed || 524 last_rhs_inst->force_sechalf || 525 !src.equals(&last_rhs_inst->dst)) 526 return false; 527 528 /* Success! Rewrite the instruction. */ 529 last_rhs_inst->dst = dst; 530 531 return true; 532} 533 534void 535fs_visitor::visit(ir_assignment *ir) 536{ 537 fs_reg l, r; 538 fs_inst *inst; 539 540 /* FINISHME: arrays on the lhs */ 541 ir->lhs->accept(this); 542 l = this->result; 543 544 fs_inst *pre_rhs_inst = (fs_inst *) this->instructions.get_tail(); 545 546 ir->rhs->accept(this); 547 r = this->result; 548 549 fs_inst *last_rhs_inst = (fs_inst *) this->instructions.get_tail(); 550 551 assert(l.file != BAD_FILE); 552 assert(r.file != BAD_FILE); 553 554 if (try_rewrite_rhs_to_dst(ir, l, r, pre_rhs_inst, last_rhs_inst)) 555 return; 556 557 if (ir->condition) { 558 emit_bool_to_cond_code(ir->condition); 559 } 560 561 if (ir->lhs->type->is_scalar() || 562 ir->lhs->type->is_vector()) { 563 for (int i = 0; i < ir->lhs->type->vector_elements; i++) { 564 if (ir->write_mask & (1 << i)) { 565 inst = emit(BRW_OPCODE_MOV, l, r); 566 if (ir->condition) 567 inst->predicated = true; 568 r.reg_offset++; 569 } 570 l.reg_offset++; 571 } 572 } else { 573 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL); 574 } 575} 576 577fs_inst * 578fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate, 579 int sampler) 580{ 581 int mlen; 582 int base_mrf = 1; 583 bool simd16 = false; 584 fs_reg orig_dst; 585 586 /* g0 header. */ 587 mlen = 1; 588 589 if (ir->shadow_comparitor && ir->op != ir_txd) { 590 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 591 fs_inst *inst = emit(BRW_OPCODE_MOV, 592 fs_reg(MRF, base_mrf + mlen + i), coordinate); 593 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 594 inst->saturate = true; 595 596 coordinate.reg_offset++; 597 } 598 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 599 mlen += 3; 600 601 if (ir->op == ir_tex) { 602 /* There's no plain shadow compare message, so we use shadow 603 * compare with a bias of 0.0. 604 */ 605 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)); 606 mlen++; 607 } else if (ir->op == ir_txb) { 608 ir->lod_info.bias->accept(this); 609 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 610 mlen++; 611 } else { 612 assert(ir->op == ir_txl); 613 ir->lod_info.lod->accept(this); 614 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 615 mlen++; 616 } 617 618 ir->shadow_comparitor->accept(this); 619 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 620 mlen++; 621 } else if (ir->op == ir_tex) { 622 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 623 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), 624 coordinate); 625 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 626 inst->saturate = true; 627 coordinate.reg_offset++; 628 } 629 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 630 mlen += 3; 631 } else if (ir->op == ir_txd) { 632 ir->lod_info.grad.dPdx->accept(this); 633 fs_reg dPdx = this->result; 634 635 ir->lod_info.grad.dPdy->accept(this); 636 fs_reg dPdy = this->result; 637 638 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 639 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); 640 coordinate.reg_offset++; 641 } 642 /* the slots for u and v are always present, but r is optional */ 643 mlen += MAX2(ir->coordinate->type->vector_elements, 2); 644 645 /* P = u, v, r 646 * dPdx = dudx, dvdx, drdx 647 * dPdy = dudy, dvdy, drdy 648 * 649 * 1-arg: Does not exist. 650 * 651 * 2-arg: dudx dvdx dudy dvdy 652 * dPdx.x dPdx.y dPdy.x dPdy.y 653 * m4 m5 m6 m7 654 * 655 * 3-arg: dudx dvdx drdx dudy dvdy drdy 656 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z 657 * m5 m6 m7 m8 m9 m10 658 */ 659 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 660 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 661 dPdx.reg_offset++; 662 } 663 mlen += MAX2(ir->lod_info.grad.dPdx->type->vector_elements, 2); 664 665 for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) { 666 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 667 dPdy.reg_offset++; 668 } 669 mlen += MAX2(ir->lod_info.grad.dPdy->type->vector_elements, 2); 670 } else if (ir->op == ir_txs) { 671 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */ 672 simd16 = true; 673 ir->lod_info.lod->accept(this); 674 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 675 mlen += 2; 676 } else { 677 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod 678 * instructions. We'll need to do SIMD16 here. 679 */ 680 simd16 = true; 681 assert(ir->op == ir_txb || ir->op == ir_txl); 682 683 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 684 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, 685 base_mrf + mlen + i * 2), 686 coordinate); 687 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 688 inst->saturate = true; 689 coordinate.reg_offset++; 690 } 691 692 /* lod/bias appears after u/v/r. */ 693 mlen += 6; 694 695 if (ir->op == ir_txb) { 696 ir->lod_info.bias->accept(this); 697 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 698 mlen++; 699 } else { 700 ir->lod_info.lod->accept(this); 701 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 702 mlen++; 703 } 704 705 /* The unused upper half. */ 706 mlen++; 707 } 708 709 if (simd16) { 710 /* Now, since we're doing simd16, the return is 2 interleaved 711 * vec4s where the odd-indexed ones are junk. We'll need to move 712 * this weirdness around to the expected layout. 713 */ 714 orig_dst = dst; 715 const glsl_type *vec_type = 716 glsl_type::get_instance(ir->type->base_type, 4, 1); 717 dst = fs_reg(this, glsl_type::get_array_instance(vec_type, 2)); 718 dst.type = intel->is_g4x ? brw_type_for_base_type(ir->type) 719 : BRW_REGISTER_TYPE_F; 720 } 721 722 fs_inst *inst = NULL; 723 switch (ir->op) { 724 case ir_tex: 725 inst = emit(FS_OPCODE_TEX, dst); 726 break; 727 case ir_txb: 728 inst = emit(FS_OPCODE_TXB, dst); 729 break; 730 case ir_txl: 731 inst = emit(FS_OPCODE_TXL, dst); 732 break; 733 case ir_txd: 734 inst = emit(FS_OPCODE_TXD, dst); 735 break; 736 case ir_txs: 737 inst = emit(FS_OPCODE_TXS, dst); 738 break; 739 case ir_txf: 740 assert(!"GLSL 1.30 features unsupported"); 741 break; 742 } 743 inst->base_mrf = base_mrf; 744 inst->mlen = mlen; 745 inst->header_present = true; 746 747 if (simd16) { 748 for (int i = 0; i < 4; i++) { 749 emit(BRW_OPCODE_MOV, orig_dst, dst); 750 orig_dst.reg_offset++; 751 dst.reg_offset += 2; 752 } 753 } 754 755 return inst; 756} 757 758/* gen5's sampler has slots for u, v, r, array index, then optional 759 * parameters like shadow comparitor or LOD bias. If optional 760 * parameters aren't present, those base slots are optional and don't 761 * need to be included in the message. 762 * 763 * We don't fill in the unnecessary slots regardless, which may look 764 * surprising in the disassembly. 765 */ 766fs_inst * 767fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate, 768 int sampler) 769{ 770 int mlen = 0; 771 int base_mrf = 2; 772 int reg_width = c->dispatch_width / 8; 773 bool header_present = false; 774 const int vector_elements = 775 ir->coordinate ? ir->coordinate->type->vector_elements : 0; 776 777 if (ir->offset) { 778 /* The offsets set up by the ir_texture visitor are in the 779 * m1 header, so we can't go headerless. 780 */ 781 header_present = true; 782 mlen++; 783 base_mrf--; 784 } 785 786 for (int i = 0; i < vector_elements; i++) { 787 fs_inst *inst = emit(BRW_OPCODE_MOV, 788 fs_reg(MRF, base_mrf + mlen + i * reg_width), 789 coordinate); 790 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 791 inst->saturate = true; 792 coordinate.reg_offset++; 793 } 794 mlen += vector_elements * reg_width; 795 796 if (ir->shadow_comparitor && ir->op != ir_txd) { 797 mlen = MAX2(mlen, header_present + 4 * reg_width); 798 799 ir->shadow_comparitor->accept(this); 800 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 801 mlen += reg_width; 802 } 803 804 fs_inst *inst = NULL; 805 switch (ir->op) { 806 case ir_tex: 807 inst = emit(FS_OPCODE_TEX, dst); 808 break; 809 case ir_txb: 810 ir->lod_info.bias->accept(this); 811 mlen = MAX2(mlen, header_present + 4 * reg_width); 812 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 813 mlen += reg_width; 814 815 inst = emit(FS_OPCODE_TXB, dst); 816 817 break; 818 case ir_txl: 819 ir->lod_info.lod->accept(this); 820 mlen = MAX2(mlen, header_present + 4 * reg_width); 821 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 822 mlen += reg_width; 823 824 inst = emit(FS_OPCODE_TXL, dst); 825 break; 826 case ir_txd: { 827 ir->lod_info.grad.dPdx->accept(this); 828 fs_reg dPdx = this->result; 829 830 ir->lod_info.grad.dPdy->accept(this); 831 fs_reg dPdy = this->result; 832 833 mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */ 834 835 /** 836 * P = u, v, r 837 * dPdx = dudx, dvdx, drdx 838 * dPdy = dudy, dvdy, drdy 839 * 840 * Load up these values: 841 * - dudx dudy dvdx dvdy drdx drdy 842 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z 843 */ 844 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 845 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 846 dPdx.reg_offset++; 847 mlen += reg_width; 848 849 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 850 dPdy.reg_offset++; 851 mlen += reg_width; 852 } 853 854 inst = emit(FS_OPCODE_TXD, dst); 855 break; 856 } 857 case ir_txs: 858 ir->lod_info.lod->accept(this); 859 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 860 mlen += reg_width; 861 inst = emit(FS_OPCODE_TXS, dst); 862 break; 863 case ir_txf: 864 assert(!"GLSL 1.30 features unsupported"); 865 break; 866 } 867 inst->base_mrf = base_mrf; 868 inst->mlen = mlen; 869 inst->header_present = header_present; 870 871 if (mlen > 11) { 872 fail("Message length >11 disallowed by hardware\n"); 873 } 874 875 return inst; 876} 877 878fs_inst * 879fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate, 880 int sampler) 881{ 882 int mlen = 0; 883 int base_mrf = 2; 884 int reg_width = c->dispatch_width / 8; 885 bool header_present = false; 886 887 if (ir->offset) { 888 /* The offsets set up by the ir_texture visitor are in the 889 * m1 header, so we can't go headerless. 890 */ 891 header_present = true; 892 mlen++; 893 base_mrf--; 894 } 895 896 if (ir->shadow_comparitor && ir->op != ir_txd) { 897 ir->shadow_comparitor->accept(this); 898 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 899 mlen += reg_width; 900 } 901 902 /* Set up the LOD info */ 903 switch (ir->op) { 904 case ir_tex: 905 break; 906 case ir_txb: 907 ir->lod_info.bias->accept(this); 908 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 909 mlen += reg_width; 910 break; 911 case ir_txl: 912 ir->lod_info.lod->accept(this); 913 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 914 mlen += reg_width; 915 break; 916 case ir_txd: { 917 if (c->dispatch_width == 16) 918 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode."); 919 920 ir->lod_info.grad.dPdx->accept(this); 921 fs_reg dPdx = this->result; 922 923 ir->lod_info.grad.dPdy->accept(this); 924 fs_reg dPdy = this->result; 925 926 /* Load dPdx and the coordinate together: 927 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z 928 */ 929 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 930 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 931 coordinate); 932 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 933 inst->saturate = true; 934 coordinate.reg_offset++; 935 mlen += reg_width; 936 937 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 938 dPdx.reg_offset++; 939 mlen += reg_width; 940 941 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 942 dPdy.reg_offset++; 943 mlen += reg_width; 944 } 945 break; 946 } 947 case ir_txs: 948 ir->lod_info.lod->accept(this); 949 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 950 mlen += reg_width; 951 break; 952 case ir_txf: 953 assert(!"GLSL 1.30 features unsupported"); 954 break; 955 } 956 957 /* Set up the coordinate (except for TXD where it was done earlier) */ 958 if (ir->op != ir_txd && ir->op != ir_txs) { 959 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 960 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 961 coordinate); 962 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 963 inst->saturate = true; 964 coordinate.reg_offset++; 965 mlen += reg_width; 966 } 967 } 968 969 /* Generate the SEND */ 970 fs_inst *inst = NULL; 971 switch (ir->op) { 972 case ir_tex: inst = emit(FS_OPCODE_TEX, dst); break; 973 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break; 974 case ir_txl: inst = emit(FS_OPCODE_TXL, dst); break; 975 case ir_txd: inst = emit(FS_OPCODE_TXD, dst); break; 976 case ir_txf: assert(!"TXF unsupported."); break; 977 case ir_txs: inst = emit(FS_OPCODE_TXS, dst); break; 978 } 979 inst->base_mrf = base_mrf; 980 inst->mlen = mlen; 981 inst->header_present = header_present; 982 983 if (mlen > 11) { 984 fail("Message length >11 disallowed by hardware\n"); 985 } 986 987 return inst; 988} 989 990void 991fs_visitor::visit(ir_texture *ir) 992{ 993 fs_inst *inst = NULL; 994 995 int sampler = _mesa_get_sampler_uniform_value(ir->sampler, prog, &fp->Base); 996 sampler = fp->Base.SamplerUnits[sampler]; 997 998 /* Our hardware doesn't have a sample_d_c message, so shadow compares 999 * for textureGrad/TXD need to be emulated with instructions. 1000 */ 1001 bool hw_compare_supported = ir->op != ir_txd; 1002 if (ir->shadow_comparitor && !hw_compare_supported) { 1003 assert(c->key.compare_funcs[sampler] != GL_NONE); 1004 /* No need to even sample for GL_ALWAYS or GL_NEVER...bail early */ 1005 if (c->key.compare_funcs[sampler] == GL_ALWAYS) 1006 return swizzle_result(ir, fs_reg(1.0f), sampler); 1007 else if (c->key.compare_funcs[sampler] == GL_NEVER) 1008 return swizzle_result(ir, fs_reg(0.0f), sampler); 1009 } 1010 1011 if (ir->coordinate) 1012 ir->coordinate->accept(this); 1013 fs_reg coordinate = this->result; 1014 1015 if (ir->offset != NULL) { 1016 ir_constant *offset = ir->offset->as_constant(); 1017 assert(offset != NULL); 1018 1019 signed char offsets[3]; 1020 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) 1021 offsets[i] = (signed char) offset->value.i[i]; 1022 1023 /* Combine all three offsets into a single unsigned dword: 1024 * 1025 * bits 11:8 - U Offset (X component) 1026 * bits 7:4 - V Offset (Y component) 1027 * bits 3:0 - R Offset (Z component) 1028 */ 1029 unsigned offset_bits = 0; 1030 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) { 1031 const unsigned shift = 4 * (2 - i); 1032 offset_bits |= (offsets[i] << shift) & (0xF << shift); 1033 } 1034 1035 /* Explicitly set up the message header by copying g0 to msg reg m1. */ 1036 emit(BRW_OPCODE_MOV, fs_reg(MRF, 1, BRW_REGISTER_TYPE_UD), 1037 fs_reg(GRF, 0, BRW_REGISTER_TYPE_UD)); 1038 1039 /* Then set the offset bits in DWord 2 of the message header. */ 1040 emit(BRW_OPCODE_MOV, 1041 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 1, 2), 1042 BRW_REGISTER_TYPE_UD)), 1043 fs_reg(brw_imm_uw(offset_bits))); 1044 } 1045 1046 /* Should be lowered by do_lower_texture_projection */ 1047 assert(!ir->projector); 1048 1049 /* The 965 requires the EU to do the normalization of GL rectangle 1050 * texture coordinates. We use the program parameter state 1051 * tracking to get the scaling factor. 1052 */ 1053 if (intel->gen < 6 && 1054 ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) { 1055 struct gl_program_parameter_list *params = c->fp->program.Base.Parameters; 1056 int tokens[STATE_LENGTH] = { 1057 STATE_INTERNAL, 1058 STATE_TEXRECT_SCALE, 1059 sampler, 1060 0, 1061 0 1062 }; 1063 1064 if (c->dispatch_width == 16) { 1065 fail("rectangle scale uniform setup not supported on 16-wide\n"); 1066 this->result = fs_reg(this, ir->type); 1067 return; 1068 } 1069 1070 c->prog_data.param_convert[c->prog_data.nr_params] = 1071 PARAM_NO_CONVERT; 1072 c->prog_data.param_convert[c->prog_data.nr_params + 1] = 1073 PARAM_NO_CONVERT; 1074 1075 fs_reg scale_x = fs_reg(UNIFORM, c->prog_data.nr_params); 1076 fs_reg scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1); 1077 GLuint index = _mesa_add_state_reference(params, 1078 (gl_state_index *)tokens); 1079 1080 this->param_index[c->prog_data.nr_params] = index; 1081 this->param_offset[c->prog_data.nr_params] = 0; 1082 c->prog_data.nr_params++; 1083 this->param_index[c->prog_data.nr_params] = index; 1084 this->param_offset[c->prog_data.nr_params] = 1; 1085 c->prog_data.nr_params++; 1086 1087 fs_reg dst = fs_reg(this, ir->coordinate->type); 1088 fs_reg src = coordinate; 1089 coordinate = dst; 1090 1091 emit(BRW_OPCODE_MUL, dst, src, scale_x); 1092 dst.reg_offset++; 1093 src.reg_offset++; 1094 emit(BRW_OPCODE_MUL, dst, src, scale_y); 1095 } 1096 1097 /* Writemasking doesn't eliminate channels on SIMD8 texture 1098 * samples, so don't worry about them. 1099 */ 1100 fs_reg dst = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 4, 1)); 1101 1102 if (intel->gen >= 7) { 1103 inst = emit_texture_gen7(ir, dst, coordinate, sampler); 1104 } else if (intel->gen >= 5) { 1105 inst = emit_texture_gen5(ir, dst, coordinate, sampler); 1106 } else { 1107 inst = emit_texture_gen4(ir, dst, coordinate, sampler); 1108 } 1109 1110 /* If there's an offset, we already set up m1. To avoid the implied move, 1111 * use the null register. Otherwise, we want an implied move from g0. 1112 */ 1113 if (ir->offset != NULL || !inst->header_present) 1114 inst->src[0] = reg_undef; 1115 else 1116 inst->src[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW)); 1117 1118 inst->sampler = sampler; 1119 1120 if (ir->shadow_comparitor) { 1121 if (hw_compare_supported) { 1122 inst->shadow_compare = true; 1123 } else { 1124 ir->shadow_comparitor->accept(this); 1125 fs_reg ref = this->result; 1126 1127 fs_reg value = dst; 1128 dst = fs_reg(this, glsl_type::vec4_type); 1129 1130 /* FINISHME: This needs to be done pre-filtering. */ 1131 1132 uint32_t conditional = 0; 1133 switch (c->key.compare_funcs[sampler]) { 1134 /* GL_ALWAYS and GL_NEVER were handled at the top of the function */ 1135 case GL_LESS: conditional = BRW_CONDITIONAL_L; break; 1136 case GL_GREATER: conditional = BRW_CONDITIONAL_G; break; 1137 case GL_LEQUAL: conditional = BRW_CONDITIONAL_LE; break; 1138 case GL_GEQUAL: conditional = BRW_CONDITIONAL_GE; break; 1139 case GL_EQUAL: conditional = BRW_CONDITIONAL_EQ; break; 1140 case GL_NOTEQUAL: conditional = BRW_CONDITIONAL_NEQ; break; 1141 default: assert(!"Should not get here: bad shadow compare function"); 1142 } 1143 1144 /* Use conditional moves to load 0 or 1 as the result */ 1145 this->current_annotation = "manual shadow comparison"; 1146 for (int i = 0; i < 4; i++) { 1147 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(0.0f)); 1148 1149 inst = emit(BRW_OPCODE_CMP, reg_null_f, ref, value); 1150 inst->conditional_mod = conditional; 1151 1152 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(1.0f)); 1153 inst->predicated = true; 1154 1155 dst.reg_offset++; 1156 value.reg_offset++; 1157 } 1158 dst.reg_offset = 0; 1159 } 1160 } 1161 1162 swizzle_result(ir, dst, sampler); 1163} 1164 1165/** 1166 * Swizzle the result of a texture result. This is necessary for 1167 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons. 1168 */ 1169void 1170fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler) 1171{ 1172 this->result = orig_val; 1173 1174 if (ir->type == glsl_type::float_type) { 1175 /* Ignore DEPTH_TEXTURE_MODE swizzling. */ 1176 assert(ir->sampler->type->sampler_shadow); 1177 } else if (c->key.tex_swizzles[sampler] != SWIZZLE_NOOP) { 1178 fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type); 1179 1180 for (int i = 0; i < 4; i++) { 1181 int swiz = GET_SWZ(c->key.tex_swizzles[sampler], i); 1182 fs_reg l = swizzled_result; 1183 l.reg_offset += i; 1184 1185 if (swiz == SWIZZLE_ZERO) { 1186 emit(BRW_OPCODE_MOV, l, fs_reg(0.0f)); 1187 } else if (swiz == SWIZZLE_ONE) { 1188 emit(BRW_OPCODE_MOV, l, fs_reg(1.0f)); 1189 } else { 1190 fs_reg r = orig_val; 1191 r.reg_offset += GET_SWZ(c->key.tex_swizzles[sampler], i); 1192 emit(BRW_OPCODE_MOV, l, r); 1193 } 1194 } 1195 this->result = swizzled_result; 1196 } 1197} 1198 1199void 1200fs_visitor::visit(ir_swizzle *ir) 1201{ 1202 ir->val->accept(this); 1203 fs_reg val = this->result; 1204 1205 if (ir->type->vector_elements == 1) { 1206 this->result.reg_offset += ir->mask.x; 1207 return; 1208 } 1209 1210 fs_reg result = fs_reg(this, ir->type); 1211 this->result = result; 1212 1213 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 1214 fs_reg channel = val; 1215 int swiz = 0; 1216 1217 switch (i) { 1218 case 0: 1219 swiz = ir->mask.x; 1220 break; 1221 case 1: 1222 swiz = ir->mask.y; 1223 break; 1224 case 2: 1225 swiz = ir->mask.z; 1226 break; 1227 case 3: 1228 swiz = ir->mask.w; 1229 break; 1230 } 1231 1232 channel.reg_offset += swiz; 1233 emit(BRW_OPCODE_MOV, result, channel); 1234 result.reg_offset++; 1235 } 1236} 1237 1238void 1239fs_visitor::visit(ir_discard *ir) 1240{ 1241 assert(ir->condition == NULL); /* FINISHME */ 1242 1243 emit(FS_OPCODE_DISCARD); 1244 kill_emitted = true; 1245} 1246 1247void 1248fs_visitor::visit(ir_constant *ir) 1249{ 1250 /* Set this->result to reg at the bottom of the function because some code 1251 * paths will cause this visitor to be applied to other fields. This will 1252 * cause the value stored in this->result to be modified. 1253 * 1254 * Make reg constant so that it doesn't get accidentally modified along the 1255 * way. Yes, I actually had this problem. :( 1256 */ 1257 const fs_reg reg(this, ir->type); 1258 fs_reg dst_reg = reg; 1259 1260 if (ir->type->is_array()) { 1261 const unsigned size = type_size(ir->type->fields.array); 1262 1263 for (unsigned i = 0; i < ir->type->length; i++) { 1264 ir->array_elements[i]->accept(this); 1265 fs_reg src_reg = this->result; 1266 1267 dst_reg.type = src_reg.type; 1268 for (unsigned j = 0; j < size; j++) { 1269 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1270 src_reg.reg_offset++; 1271 dst_reg.reg_offset++; 1272 } 1273 } 1274 } else if (ir->type->is_record()) { 1275 foreach_list(node, &ir->components) { 1276 ir_instruction *const field = (ir_instruction *) node; 1277 const unsigned size = type_size(field->type); 1278 1279 field->accept(this); 1280 fs_reg src_reg = this->result; 1281 1282 dst_reg.type = src_reg.type; 1283 for (unsigned j = 0; j < size; j++) { 1284 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1285 src_reg.reg_offset++; 1286 dst_reg.reg_offset++; 1287 } 1288 } 1289 } else { 1290 const unsigned size = type_size(ir->type); 1291 1292 for (unsigned i = 0; i < size; i++) { 1293 switch (ir->type->base_type) { 1294 case GLSL_TYPE_FLOAT: 1295 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i])); 1296 break; 1297 case GLSL_TYPE_UINT: 1298 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i])); 1299 break; 1300 case GLSL_TYPE_INT: 1301 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.i[i])); 1302 break; 1303 case GLSL_TYPE_BOOL: 1304 emit(BRW_OPCODE_MOV, dst_reg, fs_reg((int)ir->value.b[i])); 1305 break; 1306 default: 1307 assert(!"Non-float/uint/int/bool constant"); 1308 } 1309 dst_reg.reg_offset++; 1310 } 1311 } 1312 1313 this->result = reg; 1314} 1315 1316void 1317fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir) 1318{ 1319 ir_expression *expr = ir->as_expression(); 1320 1321 if (expr) { 1322 fs_reg op[2]; 1323 fs_inst *inst; 1324 1325 assert(expr->get_num_operands() <= 2); 1326 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1327 assert(expr->operands[i]->type->is_scalar()); 1328 1329 expr->operands[i]->accept(this); 1330 op[i] = this->result; 1331 } 1332 1333 switch (expr->operation) { 1334 case ir_unop_logic_not: 1335 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1)); 1336 inst->conditional_mod = BRW_CONDITIONAL_Z; 1337 break; 1338 1339 case ir_binop_logic_xor: 1340 inst = emit(BRW_OPCODE_XOR, reg_null_d, op[0], op[1]); 1341 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1342 break; 1343 1344 case ir_binop_logic_or: 1345 inst = emit(BRW_OPCODE_OR, reg_null_d, op[0], op[1]); 1346 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1347 break; 1348 1349 case ir_binop_logic_and: 1350 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], op[1]); 1351 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1352 break; 1353 1354 case ir_unop_f2b: 1355 if (intel->gen >= 6) { 1356 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0.0f)); 1357 } else { 1358 inst = emit(BRW_OPCODE_MOV, reg_null_f, op[0]); 1359 } 1360 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1361 break; 1362 1363 case ir_unop_i2b: 1364 if (intel->gen >= 6) { 1365 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0)); 1366 } else { 1367 inst = emit(BRW_OPCODE_MOV, reg_null_d, op[0]); 1368 } 1369 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1370 break; 1371 1372 case ir_binop_greater: 1373 case ir_binop_gequal: 1374 case ir_binop_less: 1375 case ir_binop_lequal: 1376 case ir_binop_equal: 1377 case ir_binop_all_equal: 1378 case ir_binop_nequal: 1379 case ir_binop_any_nequal: 1380 inst = emit(BRW_OPCODE_CMP, reg_null_cmp, op[0], op[1]); 1381 inst->conditional_mod = 1382 brw_conditional_for_comparison(expr->operation); 1383 break; 1384 1385 default: 1386 assert(!"not reached"); 1387 fail("bad cond code\n"); 1388 break; 1389 } 1390 return; 1391 } 1392 1393 ir->accept(this); 1394 1395 if (intel->gen >= 6) { 1396 fs_inst *inst = emit(BRW_OPCODE_AND, reg_null_d, this->result, fs_reg(1)); 1397 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1398 } else { 1399 fs_inst *inst = emit(BRW_OPCODE_MOV, reg_null_d, this->result); 1400 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1401 } 1402} 1403 1404/** 1405 * Emit a gen6 IF statement with the comparison folded into the IF 1406 * instruction. 1407 */ 1408void 1409fs_visitor::emit_if_gen6(ir_if *ir) 1410{ 1411 ir_expression *expr = ir->condition->as_expression(); 1412 1413 if (expr) { 1414 fs_reg op[2]; 1415 fs_inst *inst; 1416 fs_reg temp; 1417 1418 assert(expr->get_num_operands() <= 2); 1419 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1420 assert(expr->operands[i]->type->is_scalar()); 1421 1422 expr->operands[i]->accept(this); 1423 op[i] = this->result; 1424 } 1425 1426 switch (expr->operation) { 1427 case ir_unop_logic_not: 1428 inst = emit(BRW_OPCODE_IF, temp, op[0], fs_reg(0)); 1429 inst->conditional_mod = BRW_CONDITIONAL_Z; 1430 return; 1431 1432 case ir_binop_logic_xor: 1433 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1434 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1435 return; 1436 1437 case ir_binop_logic_or: 1438 temp = fs_reg(this, glsl_type::bool_type); 1439 emit(BRW_OPCODE_OR, temp, op[0], op[1]); 1440 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1441 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1442 return; 1443 1444 case ir_binop_logic_and: 1445 temp = fs_reg(this, glsl_type::bool_type); 1446 emit(BRW_OPCODE_AND, temp, op[0], op[1]); 1447 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1448 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1449 return; 1450 1451 case ir_unop_f2b: 1452 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0)); 1453 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1454 return; 1455 1456 case ir_unop_i2b: 1457 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1458 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1459 return; 1460 1461 case ir_binop_greater: 1462 case ir_binop_gequal: 1463 case ir_binop_less: 1464 case ir_binop_lequal: 1465 case ir_binop_equal: 1466 case ir_binop_all_equal: 1467 case ir_binop_nequal: 1468 case ir_binop_any_nequal: 1469 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1470 inst->conditional_mod = 1471 brw_conditional_for_comparison(expr->operation); 1472 return; 1473 default: 1474 assert(!"not reached"); 1475 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1476 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1477 fail("bad condition\n"); 1478 return; 1479 } 1480 return; 1481 } 1482 1483 ir->condition->accept(this); 1484 1485 fs_inst *inst = emit(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0)); 1486 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1487} 1488 1489void 1490fs_visitor::visit(ir_if *ir) 1491{ 1492 fs_inst *inst; 1493 1494 if (intel->gen != 6 && c->dispatch_width == 16) { 1495 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1496 } 1497 1498 /* Don't point the annotation at the if statement, because then it plus 1499 * the then and else blocks get printed. 1500 */ 1501 this->base_ir = ir->condition; 1502 1503 if (intel->gen == 6) { 1504 emit_if_gen6(ir); 1505 } else { 1506 emit_bool_to_cond_code(ir->condition); 1507 1508 inst = emit(BRW_OPCODE_IF); 1509 inst->predicated = true; 1510 } 1511 1512 foreach_list(node, &ir->then_instructions) { 1513 ir_instruction *ir = (ir_instruction *)node; 1514 this->base_ir = ir; 1515 1516 ir->accept(this); 1517 } 1518 1519 if (!ir->else_instructions.is_empty()) { 1520 emit(BRW_OPCODE_ELSE); 1521 1522 foreach_list(node, &ir->else_instructions) { 1523 ir_instruction *ir = (ir_instruction *)node; 1524 this->base_ir = ir; 1525 1526 ir->accept(this); 1527 } 1528 } 1529 1530 emit(BRW_OPCODE_ENDIF); 1531} 1532 1533void 1534fs_visitor::visit(ir_loop *ir) 1535{ 1536 fs_reg counter = reg_undef; 1537 1538 if (c->dispatch_width == 16) { 1539 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1540 } 1541 1542 if (ir->counter) { 1543 this->base_ir = ir->counter; 1544 ir->counter->accept(this); 1545 counter = *(variable_storage(ir->counter)); 1546 1547 if (ir->from) { 1548 this->base_ir = ir->from; 1549 ir->from->accept(this); 1550 1551 emit(BRW_OPCODE_MOV, counter, this->result); 1552 } 1553 } 1554 1555 emit(BRW_OPCODE_DO); 1556 1557 if (ir->to) { 1558 this->base_ir = ir->to; 1559 ir->to->accept(this); 1560 1561 fs_inst *inst = emit(BRW_OPCODE_CMP, reg_null_cmp, counter, this->result); 1562 inst->conditional_mod = brw_conditional_for_comparison(ir->cmp); 1563 1564 inst = emit(BRW_OPCODE_BREAK); 1565 inst->predicated = true; 1566 } 1567 1568 foreach_list(node, &ir->body_instructions) { 1569 ir_instruction *ir = (ir_instruction *)node; 1570 1571 this->base_ir = ir; 1572 ir->accept(this); 1573 } 1574 1575 if (ir->increment) { 1576 this->base_ir = ir->increment; 1577 ir->increment->accept(this); 1578 emit(BRW_OPCODE_ADD, counter, counter, this->result); 1579 } 1580 1581 emit(BRW_OPCODE_WHILE); 1582} 1583 1584void 1585fs_visitor::visit(ir_loop_jump *ir) 1586{ 1587 switch (ir->mode) { 1588 case ir_loop_jump::jump_break: 1589 emit(BRW_OPCODE_BREAK); 1590 break; 1591 case ir_loop_jump::jump_continue: 1592 emit(BRW_OPCODE_CONTINUE); 1593 break; 1594 } 1595} 1596 1597void 1598fs_visitor::visit(ir_call *ir) 1599{ 1600 assert(!"FINISHME"); 1601} 1602 1603void 1604fs_visitor::visit(ir_return *ir) 1605{ 1606 assert(!"FINISHME"); 1607} 1608 1609void 1610fs_visitor::visit(ir_function *ir) 1611{ 1612 /* Ignore function bodies other than main() -- we shouldn't see calls to 1613 * them since they should all be inlined before we get to ir_to_mesa. 1614 */ 1615 if (strcmp(ir->name, "main") == 0) { 1616 const ir_function_signature *sig; 1617 exec_list empty; 1618 1619 sig = ir->matching_signature(&empty); 1620 1621 assert(sig); 1622 1623 foreach_list(node, &sig->body) { 1624 ir_instruction *ir = (ir_instruction *)node; 1625 this->base_ir = ir; 1626 1627 ir->accept(this); 1628 } 1629 } 1630} 1631 1632void 1633fs_visitor::visit(ir_function_signature *ir) 1634{ 1635 assert(!"not reached"); 1636 (void)ir; 1637} 1638 1639fs_inst * 1640fs_visitor::emit(fs_inst inst) 1641{ 1642 fs_inst *list_inst = new(mem_ctx) fs_inst; 1643 *list_inst = inst; 1644 1645 if (force_uncompressed_stack > 0) 1646 list_inst->force_uncompressed = true; 1647 else if (force_sechalf_stack > 0) 1648 list_inst->force_sechalf = true; 1649 1650 list_inst->annotation = this->current_annotation; 1651 list_inst->ir = this->base_ir; 1652 1653 this->instructions.push_tail(list_inst); 1654 1655 return list_inst; 1656} 1657 1658/** Emits a dummy fragment shader consisting of magenta for bringup purposes. */ 1659void 1660fs_visitor::emit_dummy_fs() 1661{ 1662 /* Everyone's favorite color. */ 1663 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2), fs_reg(1.0f)); 1664 emit(BRW_OPCODE_MOV, fs_reg(MRF, 3), fs_reg(0.0f)); 1665 emit(BRW_OPCODE_MOV, fs_reg(MRF, 4), fs_reg(1.0f)); 1666 emit(BRW_OPCODE_MOV, fs_reg(MRF, 5), fs_reg(0.0f)); 1667 1668 fs_inst *write; 1669 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0)); 1670 write->base_mrf = 2; 1671} 1672 1673/* The register location here is relative to the start of the URB 1674 * data. It will get adjusted to be a real location before 1675 * generate_code() time. 1676 */ 1677struct brw_reg 1678fs_visitor::interp_reg(int location, int channel) 1679{ 1680 int regnr = urb_setup[location] * 2 + channel / 2; 1681 int stride = (channel & 1) * 4; 1682 1683 assert(urb_setup[location] != -1); 1684 1685 return brw_vec1_grf(regnr, stride); 1686} 1687 1688/** Emits the interpolation for the varying inputs. */ 1689void 1690fs_visitor::emit_interpolation_setup_gen4() 1691{ 1692 this->current_annotation = "compute pixel centers"; 1693 this->pixel_x = fs_reg(this, glsl_type::uint_type); 1694 this->pixel_y = fs_reg(this, glsl_type::uint_type); 1695 this->pixel_x.type = BRW_REGISTER_TYPE_UW; 1696 this->pixel_y.type = BRW_REGISTER_TYPE_UW; 1697 1698 emit(FS_OPCODE_PIXEL_X, this->pixel_x); 1699 emit(FS_OPCODE_PIXEL_Y, this->pixel_y); 1700 1701 this->current_annotation = "compute pixel deltas from v0"; 1702 if (brw->has_pln) { 1703 this->delta_x = fs_reg(this, glsl_type::vec2_type); 1704 this->delta_y = this->delta_x; 1705 this->delta_y.reg_offset++; 1706 } else { 1707 this->delta_x = fs_reg(this, glsl_type::float_type); 1708 this->delta_y = fs_reg(this, glsl_type::float_type); 1709 } 1710 emit(BRW_OPCODE_ADD, this->delta_x, 1711 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))); 1712 emit(BRW_OPCODE_ADD, this->delta_y, 1713 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))); 1714 1715 this->current_annotation = "compute pos.w and 1/pos.w"; 1716 /* Compute wpos.w. It's always in our setup, since it's needed to 1717 * interpolate the other attributes. 1718 */ 1719 this->wpos_w = fs_reg(this, glsl_type::float_type); 1720 emit(FS_OPCODE_LINTERP, wpos_w, this->delta_x, this->delta_y, 1721 interp_reg(FRAG_ATTRIB_WPOS, 3)); 1722 /* Compute the pixel 1/W value from wpos.w. */ 1723 this->pixel_w = fs_reg(this, glsl_type::float_type); 1724 emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w); 1725 this->current_annotation = NULL; 1726} 1727 1728/** Emits the interpolation for the varying inputs. */ 1729void 1730fs_visitor::emit_interpolation_setup_gen6() 1731{ 1732 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); 1733 1734 /* If the pixel centers end up used, the setup is the same as for gen4. */ 1735 this->current_annotation = "compute pixel centers"; 1736 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type); 1737 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type); 1738 int_pixel_x.type = BRW_REGISTER_TYPE_UW; 1739 int_pixel_y.type = BRW_REGISTER_TYPE_UW; 1740 emit(BRW_OPCODE_ADD, 1741 int_pixel_x, 1742 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), 1743 fs_reg(brw_imm_v(0x10101010))); 1744 emit(BRW_OPCODE_ADD, 1745 int_pixel_y, 1746 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), 1747 fs_reg(brw_imm_v(0x11001100))); 1748 1749 /* As of gen6, we can no longer mix float and int sources. We have 1750 * to turn the integer pixel centers into floats for their actual 1751 * use. 1752 */ 1753 this->pixel_x = fs_reg(this, glsl_type::float_type); 1754 this->pixel_y = fs_reg(this, glsl_type::float_type); 1755 emit(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x); 1756 emit(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y); 1757 1758 this->current_annotation = "compute pos.w"; 1759 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0)); 1760 this->wpos_w = fs_reg(this, glsl_type::float_type); 1761 emit_math(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w); 1762 1763 this->delta_x = fs_reg(brw_vec8_grf(2, 0)); 1764 this->delta_y = fs_reg(brw_vec8_grf(3, 0)); 1765 1766 this->current_annotation = NULL; 1767} 1768 1769void 1770fs_visitor::emit_color_write(int index, int first_color_mrf, fs_reg color) 1771{ 1772 int reg_width = c->dispatch_width / 8; 1773 fs_inst *inst; 1774 1775 if (c->dispatch_width == 8 || intel->gen == 6) { 1776 /* SIMD8 write looks like: 1777 * m + 0: r0 1778 * m + 1: r1 1779 * m + 2: g0 1780 * m + 3: g1 1781 * 1782 * gen6 SIMD16 DP write looks like: 1783 * m + 0: r0 1784 * m + 1: r1 1785 * m + 2: g0 1786 * m + 3: g1 1787 * m + 4: b0 1788 * m + 5: b1 1789 * m + 6: a0 1790 * m + 7: a1 1791 */ 1792 inst = emit(BRW_OPCODE_MOV, 1793 fs_reg(MRF, first_color_mrf + index * reg_width), 1794 color); 1795 inst->saturate = c->key.clamp_fragment_color; 1796 } else { 1797 /* pre-gen6 SIMD16 single source DP write looks like: 1798 * m + 0: r0 1799 * m + 1: g0 1800 * m + 2: b0 1801 * m + 3: a0 1802 * m + 4: r1 1803 * m + 5: g1 1804 * m + 6: b1 1805 * m + 7: a1 1806 */ 1807 if (brw->has_compr4) { 1808 /* By setting the high bit of the MRF register number, we 1809 * indicate that we want COMPR4 mode - instead of doing the 1810 * usual destination + 1 for the second half we get 1811 * destination + 4. 1812 */ 1813 inst = emit(BRW_OPCODE_MOV, 1814 fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index), 1815 color); 1816 inst->saturate = c->key.clamp_fragment_color; 1817 } else { 1818 push_force_uncompressed(); 1819 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index), 1820 color); 1821 inst->saturate = c->key.clamp_fragment_color; 1822 pop_force_uncompressed(); 1823 1824 push_force_sechalf(); 1825 color.sechalf = true; 1826 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index + 4), 1827 color); 1828 inst->saturate = c->key.clamp_fragment_color; 1829 pop_force_sechalf(); 1830 color.sechalf = false; 1831 } 1832 } 1833} 1834 1835void 1836fs_visitor::emit_fb_writes() 1837{ 1838 this->current_annotation = "FB write header"; 1839 GLboolean header_present = GL_TRUE; 1840 int base_mrf = 2; 1841 int nr = base_mrf; 1842 int reg_width = c->dispatch_width / 8; 1843 1844 if (intel->gen >= 6 && 1845 !this->kill_emitted && 1846 c->key.nr_color_regions == 1) { 1847 header_present = false; 1848 } 1849 1850 if (header_present) { 1851 /* m2, m3 header */ 1852 nr += 2; 1853 } 1854 1855 if (c->aa_dest_stencil_reg) { 1856 push_force_uncompressed(); 1857 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++), 1858 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))); 1859 pop_force_uncompressed(); 1860 } 1861 1862 /* Reserve space for color. It'll be filled in per MRT below. */ 1863 int color_mrf = nr; 1864 nr += 4 * reg_width; 1865 1866 if (c->source_depth_to_render_target) { 1867 if (intel->gen == 6 && c->dispatch_width == 16) { 1868 /* For outputting oDepth on gen6, SIMD8 writes have to be 1869 * used. This would require 8-wide moves of each half to 1870 * message regs, kind of like pre-gen5 SIMD16 FB writes. 1871 * Just bail on doing so for now. 1872 */ 1873 fail("Missing support for simd16 depth writes on gen6\n"); 1874 } 1875 1876 if (c->computes_depth) { 1877 /* Hand over gl_FragDepth. */ 1878 assert(this->frag_depth); 1879 fs_reg depth = *(variable_storage(this->frag_depth)); 1880 1881 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), depth); 1882 } else { 1883 /* Pass through the payload depth. */ 1884 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1885 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))); 1886 } 1887 nr += reg_width; 1888 } 1889 1890 if (c->dest_depth_reg) { 1891 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1892 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))); 1893 nr += reg_width; 1894 } 1895 1896 fs_reg color = reg_undef; 1897 if (this->frag_color) 1898 color = *(variable_storage(this->frag_color)); 1899 else if (this->frag_data) { 1900 color = *(variable_storage(this->frag_data)); 1901 color.type = BRW_REGISTER_TYPE_F; 1902 } 1903 1904 for (int target = 0; target < c->key.nr_color_regions; target++) { 1905 this->current_annotation = ralloc_asprintf(this->mem_ctx, 1906 "FB write target %d", 1907 target); 1908 if (this->frag_color || this->frag_data) { 1909 for (int i = 0; i < 4; i++) { 1910 emit_color_write(i, color_mrf, color); 1911 color.reg_offset++; 1912 } 1913 } 1914 1915 if (this->frag_color) 1916 color.reg_offset -= 4; 1917 1918 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1919 inst->target = target; 1920 inst->base_mrf = base_mrf; 1921 inst->mlen = nr - base_mrf; 1922 if (target == c->key.nr_color_regions - 1) 1923 inst->eot = true; 1924 inst->header_present = header_present; 1925 } 1926 1927 if (c->key.nr_color_regions == 0) { 1928 if (c->key.alpha_test && (this->frag_color || this->frag_data)) { 1929 /* If the alpha test is enabled but there's no color buffer, 1930 * we still need to send alpha out the pipeline to our null 1931 * renderbuffer. 1932 */ 1933 color.reg_offset += 3; 1934 emit_color_write(3, color_mrf, color); 1935 } 1936 1937 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1938 inst->base_mrf = base_mrf; 1939 inst->mlen = nr - base_mrf; 1940 inst->eot = true; 1941 inst->header_present = header_present; 1942 } 1943 1944 this->current_annotation = NULL; 1945} 1946