brw_fs_visitor.cpp revision 3fa910fff9f72d1adf33f0f4dea3d790a9ce04ab
1/* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24/** @file brw_fs_visitor.cpp 25 * 26 * This file supports generating the FS LIR from the GLSL IR. The LIR 27 * makes it easier to do backend-specific optimizations than doing so 28 * in the GLSL IR or in the native code. 29 */ 30extern "C" { 31 32#include <sys/types.h> 33 34#include "main/macros.h" 35#include "main/shaderobj.h" 36#include "main/uniforms.h" 37#include "program/prog_parameter.h" 38#include "program/prog_print.h" 39#include "program/prog_optimize.h" 40#include "program/register_allocate.h" 41#include "program/sampler.h" 42#include "program/hash_table.h" 43#include "brw_context.h" 44#include "brw_eu.h" 45#include "brw_wm.h" 46} 47#include "brw_shader.h" 48#include "brw_fs.h" 49#include "../glsl/glsl_types.h" 50#include "../glsl/ir_optimization.h" 51#include "../glsl/ir_print_visitor.h" 52 53void 54fs_visitor::visit(ir_variable *ir) 55{ 56 fs_reg *reg = NULL; 57 58 if (variable_storage(ir)) 59 return; 60 61 if (strcmp(ir->name, "gl_FragColor") == 0) { 62 this->frag_color = ir; 63 } else if (strcmp(ir->name, "gl_FragData") == 0) { 64 this->frag_data = ir; 65 } else if (strcmp(ir->name, "gl_FragDepth") == 0) { 66 this->frag_depth = ir; 67 } 68 69 if (ir->mode == ir_var_in) { 70 if (!strcmp(ir->name, "gl_FragCoord")) { 71 reg = emit_fragcoord_interpolation(ir); 72 } else if (!strcmp(ir->name, "gl_FrontFacing")) { 73 reg = emit_frontfacing_interpolation(ir); 74 } else { 75 reg = emit_general_interpolation(ir); 76 } 77 assert(reg); 78 hash_table_insert(this->variable_ht, reg, ir); 79 return; 80 } 81 82 if (ir->mode == ir_var_uniform) { 83 int param_index = c->prog_data.nr_params; 84 85 if (c->dispatch_width == 16) { 86 if (!variable_storage(ir)) { 87 fail("Failed to find uniform '%s' in 16-wide\n", ir->name); 88 } 89 return; 90 } 91 92 if (!strncmp(ir->name, "gl_", 3)) { 93 setup_builtin_uniform_values(ir); 94 } else { 95 setup_uniform_values(ir->location, ir->type); 96 } 97 98 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index); 99 reg->type = brw_type_for_base_type(ir->type); 100 } 101 102 if (!reg) 103 reg = new(this->mem_ctx) fs_reg(this, ir->type); 104 105 hash_table_insert(this->variable_ht, reg, ir); 106} 107 108void 109fs_visitor::visit(ir_dereference_variable *ir) 110{ 111 fs_reg *reg = variable_storage(ir->var); 112 this->result = *reg; 113} 114 115void 116fs_visitor::visit(ir_dereference_record *ir) 117{ 118 const glsl_type *struct_type = ir->record->type; 119 120 ir->record->accept(this); 121 122 unsigned int offset = 0; 123 for (unsigned int i = 0; i < struct_type->length; i++) { 124 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0) 125 break; 126 offset += type_size(struct_type->fields.structure[i].type); 127 } 128 this->result.reg_offset += offset; 129 this->result.type = brw_type_for_base_type(ir->type); 130} 131 132void 133fs_visitor::visit(ir_dereference_array *ir) 134{ 135 ir_constant *index; 136 int element_size; 137 138 ir->array->accept(this); 139 index = ir->array_index->as_constant(); 140 141 element_size = type_size(ir->type); 142 this->result.type = brw_type_for_base_type(ir->type); 143 144 if (index) { 145 assert(this->result.file == UNIFORM || 146 (this->result.file == GRF && 147 this->result.reg != 0)); 148 this->result.reg_offset += index->value.i[0] * element_size; 149 } else { 150 assert(!"FINISHME: non-constant array element"); 151 } 152} 153 154/* Instruction selection: Produce a MOV.sat instead of 155 * MIN(MAX(val, 0), 1) when possible. 156 */ 157bool 158fs_visitor::try_emit_saturate(ir_expression *ir) 159{ 160 ir_rvalue *sat_val = ir->as_rvalue_to_saturate(); 161 162 if (!sat_val) 163 return false; 164 165 this->result = reg_undef; 166 sat_val->accept(this); 167 fs_reg src = this->result; 168 169 this->result = fs_reg(this, ir->type); 170 fs_inst *inst = emit(BRW_OPCODE_MOV, this->result, src); 171 inst->saturate = true; 172 173 return true; 174} 175 176void 177fs_visitor::visit(ir_expression *ir) 178{ 179 unsigned int operand; 180 fs_reg op[2], temp; 181 fs_inst *inst; 182 183 assert(ir->get_num_operands() <= 2); 184 185 if (try_emit_saturate(ir)) 186 return; 187 188 /* This is where our caller would like us to put the result, if possible. */ 189 fs_reg saved_result_storage = this->result; 190 191 for (operand = 0; operand < ir->get_num_operands(); operand++) { 192 this->result = reg_undef; 193 ir->operands[operand]->accept(this); 194 if (this->result.file == BAD_FILE) { 195 ir_print_visitor v; 196 fail("Failed to get tree for expression operand:\n"); 197 ir->operands[operand]->accept(&v); 198 } 199 op[operand] = this->result; 200 201 /* Matrix expression operands should have been broken down to vector 202 * operations already. 203 */ 204 assert(!ir->operands[operand]->type->is_matrix()); 205 /* And then those vector operands should have been broken down to scalar. 206 */ 207 assert(!ir->operands[operand]->type->is_vector()); 208 } 209 210 /* Inherit storage from our parent if possible, and otherwise we 211 * alloc a temporary. 212 */ 213 if (saved_result_storage.file == BAD_FILE) { 214 this->result = fs_reg(this, ir->type); 215 } else { 216 this->result = saved_result_storage; 217 } 218 219 switch (ir->operation) { 220 case ir_unop_logic_not: 221 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is 222 * ones complement of the whole register, not just bit 0. 223 */ 224 emit(BRW_OPCODE_XOR, this->result, op[0], fs_reg(1)); 225 break; 226 case ir_unop_neg: 227 op[0].negate = !op[0].negate; 228 this->result = op[0]; 229 break; 230 case ir_unop_abs: 231 op[0].abs = true; 232 op[0].negate = false; 233 this->result = op[0]; 234 break; 235 case ir_unop_sign: 236 temp = fs_reg(this, ir->type); 237 238 /* Unalias the destination. (imagine a = sign(a)) */ 239 this->result = fs_reg(this, ir->type); 240 241 emit(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)); 242 243 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 244 inst->conditional_mod = BRW_CONDITIONAL_G; 245 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)); 246 inst->predicated = true; 247 248 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 249 inst->conditional_mod = BRW_CONDITIONAL_L; 250 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)); 251 inst->predicated = true; 252 253 break; 254 case ir_unop_rcp: 255 emit_math(FS_OPCODE_RCP, this->result, op[0]); 256 break; 257 258 case ir_unop_exp2: 259 emit_math(FS_OPCODE_EXP2, this->result, op[0]); 260 break; 261 case ir_unop_log2: 262 emit_math(FS_OPCODE_LOG2, this->result, op[0]); 263 break; 264 case ir_unop_exp: 265 case ir_unop_log: 266 assert(!"not reached: should be handled by ir_explog_to_explog2"); 267 break; 268 case ir_unop_sin: 269 case ir_unop_sin_reduced: 270 emit_math(FS_OPCODE_SIN, this->result, op[0]); 271 break; 272 case ir_unop_cos: 273 case ir_unop_cos_reduced: 274 emit_math(FS_OPCODE_COS, this->result, op[0]); 275 break; 276 277 case ir_unop_dFdx: 278 emit(FS_OPCODE_DDX, this->result, op[0]); 279 break; 280 case ir_unop_dFdy: 281 emit(FS_OPCODE_DDY, this->result, op[0]); 282 break; 283 284 case ir_binop_add: 285 emit(BRW_OPCODE_ADD, this->result, op[0], op[1]); 286 break; 287 case ir_binop_sub: 288 assert(!"not reached: should be handled by ir_sub_to_add_neg"); 289 break; 290 291 case ir_binop_mul: 292 emit(BRW_OPCODE_MUL, this->result, op[0], op[1]); 293 break; 294 case ir_binop_div: 295 assert(!"not reached: should be handled by ir_div_to_mul_rcp"); 296 break; 297 case ir_binop_mod: 298 assert(!"ir_binop_mod should have been converted to b * fract(a/b)"); 299 break; 300 301 case ir_binop_less: 302 case ir_binop_greater: 303 case ir_binop_lequal: 304 case ir_binop_gequal: 305 case ir_binop_equal: 306 case ir_binop_all_equal: 307 case ir_binop_nequal: 308 case ir_binop_any_nequal: 309 temp = this->result; 310 /* original gen4 does implicit conversion before comparison. */ 311 if (intel->gen < 5) 312 temp.type = op[0].type; 313 314 inst = emit(BRW_OPCODE_CMP, temp, op[0], op[1]); 315 inst->conditional_mod = brw_conditional_for_comparison(ir->operation); 316 emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)); 317 break; 318 319 case ir_binop_logic_xor: 320 emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 321 break; 322 323 case ir_binop_logic_or: 324 emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 325 break; 326 327 case ir_binop_logic_and: 328 emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 329 break; 330 331 case ir_binop_dot: 332 case ir_unop_any: 333 assert(!"not reached: should be handled by brw_fs_channel_expressions"); 334 break; 335 336 case ir_unop_noise: 337 assert(!"not reached: should be handled by lower_noise"); 338 break; 339 340 case ir_quadop_vector: 341 assert(!"not reached: should be handled by lower_quadop_vector"); 342 break; 343 344 case ir_unop_sqrt: 345 emit_math(FS_OPCODE_SQRT, this->result, op[0]); 346 break; 347 348 case ir_unop_rsq: 349 emit_math(FS_OPCODE_RSQ, this->result, op[0]); 350 break; 351 352 case ir_unop_i2f: 353 case ir_unop_b2f: 354 case ir_unop_b2i: 355 case ir_unop_f2i: 356 emit(BRW_OPCODE_MOV, this->result, op[0]); 357 break; 358 case ir_unop_f2b: 359 case ir_unop_i2b: 360 temp = this->result; 361 /* original gen4 does implicit conversion before comparison. */ 362 if (intel->gen < 5) 363 temp.type = op[0].type; 364 365 inst = emit(BRW_OPCODE_CMP, temp, op[0], fs_reg(0.0f)); 366 inst->conditional_mod = BRW_CONDITIONAL_NZ; 367 inst = emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(1)); 368 break; 369 370 case ir_unop_trunc: 371 emit(BRW_OPCODE_RNDZ, this->result, op[0]); 372 break; 373 case ir_unop_ceil: 374 op[0].negate = !op[0].negate; 375 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 376 this->result.negate = true; 377 break; 378 case ir_unop_floor: 379 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 380 break; 381 case ir_unop_fract: 382 inst = emit(BRW_OPCODE_FRC, this->result, op[0]); 383 break; 384 case ir_unop_round_even: 385 emit(BRW_OPCODE_RNDE, this->result, op[0]); 386 break; 387 388 case ir_binop_min: 389 if (intel->gen >= 6) { 390 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 391 inst->conditional_mod = BRW_CONDITIONAL_L; 392 } else { 393 /* Unalias the destination */ 394 this->result = fs_reg(this, ir->type); 395 396 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 397 inst->conditional_mod = BRW_CONDITIONAL_L; 398 399 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 400 inst->predicated = true; 401 } 402 break; 403 case ir_binop_max: 404 if (intel->gen >= 6) { 405 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 406 inst->conditional_mod = BRW_CONDITIONAL_GE; 407 } else { 408 /* Unalias the destination */ 409 this->result = fs_reg(this, ir->type); 410 411 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 412 inst->conditional_mod = BRW_CONDITIONAL_G; 413 414 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 415 inst->predicated = true; 416 } 417 break; 418 419 case ir_binop_pow: 420 emit_math(FS_OPCODE_POW, this->result, op[0], op[1]); 421 break; 422 423 case ir_unop_bit_not: 424 inst = emit(BRW_OPCODE_NOT, this->result, op[0]); 425 break; 426 case ir_binop_bit_and: 427 inst = emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 428 break; 429 case ir_binop_bit_xor: 430 inst = emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 431 break; 432 case ir_binop_bit_or: 433 inst = emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 434 break; 435 436 case ir_unop_u2f: 437 case ir_binop_lshift: 438 case ir_binop_rshift: 439 assert(!"GLSL 1.30 features unsupported"); 440 break; 441 } 442} 443 444void 445fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r, 446 const glsl_type *type, bool predicated) 447{ 448 switch (type->base_type) { 449 case GLSL_TYPE_FLOAT: 450 case GLSL_TYPE_UINT: 451 case GLSL_TYPE_INT: 452 case GLSL_TYPE_BOOL: 453 for (unsigned int i = 0; i < type->components(); i++) { 454 l.type = brw_type_for_base_type(type); 455 r.type = brw_type_for_base_type(type); 456 457 if (predicated || !l.equals(&r)) { 458 fs_inst *inst = emit(BRW_OPCODE_MOV, l, r); 459 inst->predicated = predicated; 460 } 461 462 l.reg_offset++; 463 r.reg_offset++; 464 } 465 break; 466 case GLSL_TYPE_ARRAY: 467 for (unsigned int i = 0; i < type->length; i++) { 468 emit_assignment_writes(l, r, type->fields.array, predicated); 469 } 470 break; 471 472 case GLSL_TYPE_STRUCT: 473 for (unsigned int i = 0; i < type->length; i++) { 474 emit_assignment_writes(l, r, type->fields.structure[i].type, 475 predicated); 476 } 477 break; 478 479 case GLSL_TYPE_SAMPLER: 480 break; 481 482 default: 483 assert(!"not reached"); 484 break; 485 } 486} 487 488void 489fs_visitor::visit(ir_assignment *ir) 490{ 491 struct fs_reg l, r; 492 fs_inst *inst; 493 494 /* FINISHME: arrays on the lhs */ 495 this->result = reg_undef; 496 ir->lhs->accept(this); 497 l = this->result; 498 499 /* If we're doing a direct assignment, an RHS expression could 500 * drop its result right into our destination. Otherwise, tell it 501 * not to. 502 */ 503 if (ir->condition || 504 !(ir->lhs->type->is_scalar() || 505 (ir->lhs->type->is_vector() && 506 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1))) { 507 this->result = reg_undef; 508 } 509 510 ir->rhs->accept(this); 511 r = this->result; 512 513 assert(l.file != BAD_FILE); 514 assert(r.file != BAD_FILE); 515 516 if (ir->condition) { 517 emit_bool_to_cond_code(ir->condition); 518 } 519 520 if (ir->lhs->type->is_scalar() || 521 ir->lhs->type->is_vector()) { 522 for (int i = 0; i < ir->lhs->type->vector_elements; i++) { 523 if (ir->write_mask & (1 << i)) { 524 if (ir->condition) { 525 inst = emit(BRW_OPCODE_MOV, l, r); 526 inst->predicated = true; 527 } else if (!l.equals(&r)) { 528 inst = emit(BRW_OPCODE_MOV, l, r); 529 } 530 531 r.reg_offset++; 532 } 533 l.reg_offset++; 534 } 535 } else { 536 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL); 537 } 538} 539 540fs_inst * 541fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate, 542 int sampler) 543{ 544 int mlen; 545 int base_mrf = 1; 546 bool simd16 = false; 547 fs_reg orig_dst; 548 549 /* g0 header. */ 550 mlen = 1; 551 552 if (ir->shadow_comparitor) { 553 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 554 fs_inst *inst = emit(BRW_OPCODE_MOV, 555 fs_reg(MRF, base_mrf + mlen + i), coordinate); 556 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 557 inst->saturate = true; 558 559 coordinate.reg_offset++; 560 } 561 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 562 mlen += 3; 563 564 if (ir->op == ir_tex) { 565 /* There's no plain shadow compare message, so we use shadow 566 * compare with a bias of 0.0. 567 */ 568 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)); 569 mlen++; 570 } else if (ir->op == ir_txb) { 571 this->result = reg_undef; 572 ir->lod_info.bias->accept(this); 573 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 574 mlen++; 575 } else { 576 assert(ir->op == ir_txl); 577 this->result = reg_undef; 578 ir->lod_info.lod->accept(this); 579 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 580 mlen++; 581 } 582 583 this->result = reg_undef; 584 ir->shadow_comparitor->accept(this); 585 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 586 mlen++; 587 } else if (ir->op == ir_tex) { 588 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 589 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), 590 coordinate); 591 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 592 inst->saturate = true; 593 coordinate.reg_offset++; 594 } 595 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 596 mlen += 3; 597 } else if (ir->op == ir_txd) { 598 assert(!"TXD isn't supported on gen4 yet."); 599 } else { 600 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod 601 * instructions. We'll need to do SIMD16 here. 602 */ 603 assert(ir->op == ir_txb || ir->op == ir_txl); 604 605 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 606 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, 607 base_mrf + mlen + i * 2), 608 coordinate); 609 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 610 inst->saturate = true; 611 coordinate.reg_offset++; 612 } 613 614 /* lod/bias appears after u/v/r. */ 615 mlen += 6; 616 617 if (ir->op == ir_txb) { 618 this->result = reg_undef; 619 ir->lod_info.bias->accept(this); 620 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 621 mlen++; 622 } else { 623 this->result = reg_undef; 624 ir->lod_info.lod->accept(this); 625 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 626 mlen++; 627 } 628 629 /* The unused upper half. */ 630 mlen++; 631 632 /* Now, since we're doing simd16, the return is 2 interleaved 633 * vec4s where the odd-indexed ones are junk. We'll need to move 634 * this weirdness around to the expected layout. 635 */ 636 simd16 = true; 637 orig_dst = dst; 638 dst = fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type, 639 2)); 640 dst.type = BRW_REGISTER_TYPE_F; 641 } 642 643 fs_inst *inst = NULL; 644 switch (ir->op) { 645 case ir_tex: 646 inst = emit(FS_OPCODE_TEX, dst); 647 break; 648 case ir_txb: 649 inst = emit(FS_OPCODE_TXB, dst); 650 break; 651 case ir_txl: 652 inst = emit(FS_OPCODE_TXL, dst); 653 break; 654 case ir_txd: 655 inst = emit(FS_OPCODE_TXD, dst); 656 break; 657 case ir_txf: 658 assert(!"GLSL 1.30 features unsupported"); 659 break; 660 } 661 inst->base_mrf = base_mrf; 662 inst->mlen = mlen; 663 inst->header_present = true; 664 665 if (simd16) { 666 for (int i = 0; i < 4; i++) { 667 emit(BRW_OPCODE_MOV, orig_dst, dst); 668 orig_dst.reg_offset++; 669 dst.reg_offset += 2; 670 } 671 } 672 673 return inst; 674} 675 676/* gen5's sampler has slots for u, v, r, array index, then optional 677 * parameters like shadow comparitor or LOD bias. If optional 678 * parameters aren't present, those base slots are optional and don't 679 * need to be included in the message. 680 * 681 * We don't fill in the unnecessary slots regardless, which may look 682 * surprising in the disassembly. 683 */ 684fs_inst * 685fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate, 686 int sampler) 687{ 688 int mlen = 0; 689 int base_mrf = 2; 690 int reg_width = c->dispatch_width / 8; 691 bool header_present = false; 692 693 if (ir->offset) { 694 /* The offsets set up by the ir_texture visitor are in the 695 * m1 header, so we can't go headerless. 696 */ 697 header_present = true; 698 mlen++; 699 base_mrf--; 700 } 701 702 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 703 fs_inst *inst = emit(BRW_OPCODE_MOV, 704 fs_reg(MRF, base_mrf + mlen + i * reg_width), 705 coordinate); 706 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 707 inst->saturate = true; 708 coordinate.reg_offset++; 709 } 710 mlen += ir->coordinate->type->vector_elements * reg_width; 711 712 if (ir->shadow_comparitor) { 713 mlen = MAX2(mlen, header_present + 4 * reg_width); 714 715 this->result = reg_undef; 716 ir->shadow_comparitor->accept(this); 717 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 718 mlen += reg_width; 719 } 720 721 fs_inst *inst = NULL; 722 switch (ir->op) { 723 case ir_tex: 724 inst = emit(FS_OPCODE_TEX, dst); 725 break; 726 case ir_txb: 727 this->result = reg_undef; 728 ir->lod_info.bias->accept(this); 729 mlen = MAX2(mlen, header_present + 4 * reg_width); 730 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 731 mlen += reg_width; 732 733 inst = emit(FS_OPCODE_TXB, dst); 734 735 break; 736 case ir_txl: 737 this->result = reg_undef; 738 ir->lod_info.lod->accept(this); 739 mlen = MAX2(mlen, header_present + 4 * reg_width); 740 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 741 mlen += reg_width; 742 743 inst = emit(FS_OPCODE_TXL, dst); 744 break; 745 case ir_txd: 746 case ir_txf: 747 assert(!"GLSL 1.30 features unsupported"); 748 break; 749 } 750 inst->base_mrf = base_mrf; 751 inst->mlen = mlen; 752 inst->header_present = header_present; 753 754 if (mlen > 11) { 755 fail("Message length >11 disallowed by hardware\n"); 756 } 757 758 return inst; 759} 760 761fs_inst * 762fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate, 763 int sampler) 764{ 765 int mlen = 0; 766 int base_mrf = 2; 767 int reg_width = c->dispatch_width / 8; 768 bool header_present = false; 769 770 if (ir->offset) { 771 /* The offsets set up by the ir_texture visitor are in the 772 * m1 header, so we can't go headerless. 773 */ 774 header_present = true; 775 mlen++; 776 base_mrf--; 777 } 778 779 if (ir->shadow_comparitor) { 780 ir->shadow_comparitor->accept(this); 781 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 782 mlen += reg_width; 783 } 784 785 /* Set up the LOD info */ 786 switch (ir->op) { 787 case ir_tex: 788 break; 789 case ir_txb: 790 ir->lod_info.bias->accept(this); 791 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 792 mlen += reg_width; 793 break; 794 case ir_txl: 795 ir->lod_info.lod->accept(this); 796 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 797 mlen += reg_width; 798 break; 799 case ir_txd: { 800 if (c->dispatch_width == 16) 801 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode."); 802 803 ir->lod_info.grad.dPdx->accept(this); 804 fs_reg dPdx = this->result; 805 806 ir->lod_info.grad.dPdy->accept(this); 807 fs_reg dPdy = this->result; 808 809 /* Load dPdx and the coordinate together: 810 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z 811 */ 812 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 813 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 814 coordinate); 815 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 816 inst->saturate = true; 817 coordinate.reg_offset++; 818 mlen += reg_width; 819 820 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 821 dPdx.reg_offset++; 822 mlen += reg_width; 823 824 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 825 dPdy.reg_offset++; 826 mlen += reg_width; 827 } 828 break; 829 } 830 case ir_txf: 831 assert(!"GLSL 1.30 features unsupported"); 832 break; 833 } 834 835 /* Set up the coordinate (except for TXD where it was done earlier) */ 836 if (ir->op != ir_txd) { 837 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 838 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 839 coordinate); 840 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 841 inst->saturate = true; 842 coordinate.reg_offset++; 843 mlen += reg_width; 844 } 845 } 846 847 /* Generate the SEND */ 848 fs_inst *inst = NULL; 849 switch (ir->op) { 850 case ir_tex: inst = emit(FS_OPCODE_TEX, dst); break; 851 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break; 852 case ir_txl: inst = emit(FS_OPCODE_TXL, dst); break; 853 case ir_txd: inst = emit(FS_OPCODE_TXD, dst); break; 854 case ir_txf: assert(!"TXF unsupported."); 855 } 856 inst->base_mrf = base_mrf; 857 inst->mlen = mlen; 858 inst->header_present = header_present; 859 860 if (mlen > 11) { 861 fail("Message length >11 disallowed by hardware\n"); 862 } 863 864 return inst; 865} 866 867void 868fs_visitor::visit(ir_texture *ir) 869{ 870 int sampler; 871 fs_inst *inst = NULL; 872 873 this->result = reg_undef; 874 ir->coordinate->accept(this); 875 fs_reg coordinate = this->result; 876 877 if (ir->offset != NULL) { 878 ir_constant *offset = ir->offset->as_constant(); 879 assert(offset != NULL); 880 881 signed char offsets[3]; 882 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) 883 offsets[i] = (signed char) offset->value.i[i]; 884 885 /* Combine all three offsets into a single unsigned dword: 886 * 887 * bits 11:8 - U Offset (X component) 888 * bits 7:4 - V Offset (Y component) 889 * bits 3:0 - R Offset (Z component) 890 */ 891 unsigned offset_bits = 0; 892 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) { 893 const unsigned shift = 4 * (2 - i); 894 offset_bits |= (offsets[i] << shift) & (0xF << shift); 895 } 896 897 /* Explicitly set up the message header by copying g0 to msg reg m1. */ 898 emit(BRW_OPCODE_MOV, fs_reg(MRF, 1, BRW_REGISTER_TYPE_UD), 899 fs_reg(GRF, 0, BRW_REGISTER_TYPE_UD)); 900 901 /* Then set the offset bits in DWord 2 of the message header. */ 902 emit(BRW_OPCODE_MOV, 903 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 1, 2), 904 BRW_REGISTER_TYPE_UD)), 905 fs_reg(brw_imm_uw(offset_bits))); 906 } 907 908 /* Should be lowered by do_lower_texture_projection */ 909 assert(!ir->projector); 910 911 sampler = _mesa_get_sampler_uniform_value(ir->sampler, 912 prog, 913 &fp->Base); 914 sampler = fp->Base.SamplerUnits[sampler]; 915 916 /* The 965 requires the EU to do the normalization of GL rectangle 917 * texture coordinates. We use the program parameter state 918 * tracking to get the scaling factor. 919 */ 920 if (ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) { 921 struct gl_program_parameter_list *params = c->fp->program.Base.Parameters; 922 int tokens[STATE_LENGTH] = { 923 STATE_INTERNAL, 924 STATE_TEXRECT_SCALE, 925 sampler, 926 0, 927 0 928 }; 929 930 if (c->dispatch_width == 16) { 931 fail("rectangle scale uniform setup not supported on 16-wide\n"); 932 this->result = fs_reg(this, ir->type); 933 return; 934 } 935 936 c->prog_data.param_convert[c->prog_data.nr_params] = 937 PARAM_NO_CONVERT; 938 c->prog_data.param_convert[c->prog_data.nr_params + 1] = 939 PARAM_NO_CONVERT; 940 941 fs_reg scale_x = fs_reg(UNIFORM, c->prog_data.nr_params); 942 fs_reg scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1); 943 GLuint index = _mesa_add_state_reference(params, 944 (gl_state_index *)tokens); 945 946 this->param_index[c->prog_data.nr_params] = index; 947 this->param_offset[c->prog_data.nr_params] = 0; 948 c->prog_data.nr_params++; 949 this->param_index[c->prog_data.nr_params] = index; 950 this->param_offset[c->prog_data.nr_params] = 1; 951 c->prog_data.nr_params++; 952 953 fs_reg dst = fs_reg(this, ir->coordinate->type); 954 fs_reg src = coordinate; 955 coordinate = dst; 956 957 emit(BRW_OPCODE_MUL, dst, src, scale_x); 958 dst.reg_offset++; 959 src.reg_offset++; 960 emit(BRW_OPCODE_MUL, dst, src, scale_y); 961 } 962 963 /* Writemasking doesn't eliminate channels on SIMD8 texture 964 * samples, so don't worry about them. 965 */ 966 fs_reg dst = fs_reg(this, glsl_type::vec4_type); 967 968 if (intel->gen >= 7) { 969 inst = emit_texture_gen7(ir, dst, coordinate, sampler); 970 } else if (intel->gen >= 5) { 971 inst = emit_texture_gen5(ir, dst, coordinate, sampler); 972 } else { 973 inst = emit_texture_gen4(ir, dst, coordinate, sampler); 974 } 975 976 /* If there's an offset, we already set up m1. To avoid the implied move, 977 * use the null register. Otherwise, we want an implied move from g0. 978 */ 979 if (ir->offset != NULL || !inst->header_present) 980 inst->src[0] = reg_undef; 981 else 982 inst->src[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW)); 983 984 inst->sampler = sampler; 985 986 this->result = dst; 987 988 if (ir->shadow_comparitor) 989 inst->shadow_compare = true; 990 991 if (ir->type == glsl_type::float_type) { 992 /* Ignore DEPTH_TEXTURE_MODE swizzling. */ 993 assert(ir->sampler->type->sampler_shadow); 994 } else if (c->key.tex_swizzles[inst->sampler] != SWIZZLE_NOOP) { 995 fs_reg swizzle_dst = fs_reg(this, glsl_type::vec4_type); 996 997 for (int i = 0; i < 4; i++) { 998 int swiz = GET_SWZ(c->key.tex_swizzles[inst->sampler], i); 999 fs_reg l = swizzle_dst; 1000 l.reg_offset += i; 1001 1002 if (swiz == SWIZZLE_ZERO) { 1003 emit(BRW_OPCODE_MOV, l, fs_reg(0.0f)); 1004 } else if (swiz == SWIZZLE_ONE) { 1005 emit(BRW_OPCODE_MOV, l, fs_reg(1.0f)); 1006 } else { 1007 fs_reg r = dst; 1008 r.reg_offset += GET_SWZ(c->key.tex_swizzles[inst->sampler], i); 1009 emit(BRW_OPCODE_MOV, l, r); 1010 } 1011 } 1012 this->result = swizzle_dst; 1013 } 1014} 1015 1016void 1017fs_visitor::visit(ir_swizzle *ir) 1018{ 1019 this->result = reg_undef; 1020 ir->val->accept(this); 1021 fs_reg val = this->result; 1022 1023 if (ir->type->vector_elements == 1) { 1024 this->result.reg_offset += ir->mask.x; 1025 return; 1026 } 1027 1028 fs_reg result = fs_reg(this, ir->type); 1029 this->result = result; 1030 1031 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 1032 fs_reg channel = val; 1033 int swiz = 0; 1034 1035 switch (i) { 1036 case 0: 1037 swiz = ir->mask.x; 1038 break; 1039 case 1: 1040 swiz = ir->mask.y; 1041 break; 1042 case 2: 1043 swiz = ir->mask.z; 1044 break; 1045 case 3: 1046 swiz = ir->mask.w; 1047 break; 1048 } 1049 1050 channel.reg_offset += swiz; 1051 emit(BRW_OPCODE_MOV, result, channel); 1052 result.reg_offset++; 1053 } 1054} 1055 1056void 1057fs_visitor::visit(ir_discard *ir) 1058{ 1059 assert(ir->condition == NULL); /* FINISHME */ 1060 1061 emit(FS_OPCODE_DISCARD); 1062 kill_emitted = true; 1063} 1064 1065void 1066fs_visitor::visit(ir_constant *ir) 1067{ 1068 /* Set this->result to reg at the bottom of the function because some code 1069 * paths will cause this visitor to be applied to other fields. This will 1070 * cause the value stored in this->result to be modified. 1071 * 1072 * Make reg constant so that it doesn't get accidentally modified along the 1073 * way. Yes, I actually had this problem. :( 1074 */ 1075 const fs_reg reg(this, ir->type); 1076 fs_reg dst_reg = reg; 1077 1078 if (ir->type->is_array()) { 1079 const unsigned size = type_size(ir->type->fields.array); 1080 1081 for (unsigned i = 0; i < ir->type->length; i++) { 1082 this->result = reg_undef; 1083 ir->array_elements[i]->accept(this); 1084 fs_reg src_reg = this->result; 1085 1086 dst_reg.type = src_reg.type; 1087 for (unsigned j = 0; j < size; j++) { 1088 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1089 src_reg.reg_offset++; 1090 dst_reg.reg_offset++; 1091 } 1092 } 1093 } else if (ir->type->is_record()) { 1094 foreach_list(node, &ir->components) { 1095 ir_instruction *const field = (ir_instruction *) node; 1096 const unsigned size = type_size(field->type); 1097 1098 this->result = reg_undef; 1099 field->accept(this); 1100 fs_reg src_reg = this->result; 1101 1102 dst_reg.type = src_reg.type; 1103 for (unsigned j = 0; j < size; j++) { 1104 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1105 src_reg.reg_offset++; 1106 dst_reg.reg_offset++; 1107 } 1108 } 1109 } else { 1110 const unsigned size = type_size(ir->type); 1111 1112 for (unsigned i = 0; i < size; i++) { 1113 switch (ir->type->base_type) { 1114 case GLSL_TYPE_FLOAT: 1115 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i])); 1116 break; 1117 case GLSL_TYPE_UINT: 1118 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i])); 1119 break; 1120 case GLSL_TYPE_INT: 1121 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.i[i])); 1122 break; 1123 case GLSL_TYPE_BOOL: 1124 emit(BRW_OPCODE_MOV, dst_reg, fs_reg((int)ir->value.b[i])); 1125 break; 1126 default: 1127 assert(!"Non-float/uint/int/bool constant"); 1128 } 1129 dst_reg.reg_offset++; 1130 } 1131 } 1132 1133 this->result = reg; 1134} 1135 1136void 1137fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir) 1138{ 1139 ir_expression *expr = ir->as_expression(); 1140 1141 if (expr) { 1142 fs_reg op[2]; 1143 fs_inst *inst; 1144 1145 assert(expr->get_num_operands() <= 2); 1146 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1147 assert(expr->operands[i]->type->is_scalar()); 1148 1149 this->result = reg_undef; 1150 expr->operands[i]->accept(this); 1151 op[i] = this->result; 1152 } 1153 1154 switch (expr->operation) { 1155 case ir_unop_logic_not: 1156 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1)); 1157 inst->conditional_mod = BRW_CONDITIONAL_Z; 1158 break; 1159 1160 case ir_binop_logic_xor: 1161 inst = emit(BRW_OPCODE_XOR, reg_null_d, op[0], op[1]); 1162 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1163 break; 1164 1165 case ir_binop_logic_or: 1166 inst = emit(BRW_OPCODE_OR, reg_null_d, op[0], op[1]); 1167 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1168 break; 1169 1170 case ir_binop_logic_and: 1171 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], op[1]); 1172 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1173 break; 1174 1175 case ir_unop_f2b: 1176 if (intel->gen >= 6) { 1177 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0.0f)); 1178 } else { 1179 inst = emit(BRW_OPCODE_MOV, reg_null_f, op[0]); 1180 } 1181 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1182 break; 1183 1184 case ir_unop_i2b: 1185 if (intel->gen >= 6) { 1186 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0)); 1187 } else { 1188 inst = emit(BRW_OPCODE_MOV, reg_null_d, op[0]); 1189 } 1190 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1191 break; 1192 1193 case ir_binop_greater: 1194 case ir_binop_gequal: 1195 case ir_binop_less: 1196 case ir_binop_lequal: 1197 case ir_binop_equal: 1198 case ir_binop_all_equal: 1199 case ir_binop_nequal: 1200 case ir_binop_any_nequal: 1201 inst = emit(BRW_OPCODE_CMP, reg_null_cmp, op[0], op[1]); 1202 inst->conditional_mod = 1203 brw_conditional_for_comparison(expr->operation); 1204 break; 1205 1206 default: 1207 assert(!"not reached"); 1208 fail("bad cond code\n"); 1209 break; 1210 } 1211 return; 1212 } 1213 1214 this->result = reg_undef; 1215 ir->accept(this); 1216 1217 if (intel->gen >= 6) { 1218 fs_inst *inst = emit(BRW_OPCODE_AND, reg_null_d, this->result, fs_reg(1)); 1219 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1220 } else { 1221 fs_inst *inst = emit(BRW_OPCODE_MOV, reg_null_d, this->result); 1222 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1223 } 1224} 1225 1226/** 1227 * Emit a gen6 IF statement with the comparison folded into the IF 1228 * instruction. 1229 */ 1230void 1231fs_visitor::emit_if_gen6(ir_if *ir) 1232{ 1233 ir_expression *expr = ir->condition->as_expression(); 1234 1235 if (expr) { 1236 fs_reg op[2]; 1237 fs_inst *inst; 1238 fs_reg temp; 1239 1240 assert(expr->get_num_operands() <= 2); 1241 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1242 assert(expr->operands[i]->type->is_scalar()); 1243 1244 this->result = reg_undef; 1245 expr->operands[i]->accept(this); 1246 op[i] = this->result; 1247 } 1248 1249 switch (expr->operation) { 1250 case ir_unop_logic_not: 1251 inst = emit(BRW_OPCODE_IF, temp, op[0], fs_reg(0)); 1252 inst->conditional_mod = BRW_CONDITIONAL_Z; 1253 return; 1254 1255 case ir_binop_logic_xor: 1256 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1257 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1258 return; 1259 1260 case ir_binop_logic_or: 1261 temp = fs_reg(this, glsl_type::bool_type); 1262 emit(BRW_OPCODE_OR, temp, op[0], op[1]); 1263 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1264 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1265 return; 1266 1267 case ir_binop_logic_and: 1268 temp = fs_reg(this, glsl_type::bool_type); 1269 emit(BRW_OPCODE_AND, temp, op[0], op[1]); 1270 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1271 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1272 return; 1273 1274 case ir_unop_f2b: 1275 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0)); 1276 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1277 return; 1278 1279 case ir_unop_i2b: 1280 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1281 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1282 return; 1283 1284 case ir_binop_greater: 1285 case ir_binop_gequal: 1286 case ir_binop_less: 1287 case ir_binop_lequal: 1288 case ir_binop_equal: 1289 case ir_binop_all_equal: 1290 case ir_binop_nequal: 1291 case ir_binop_any_nequal: 1292 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1293 inst->conditional_mod = 1294 brw_conditional_for_comparison(expr->operation); 1295 return; 1296 default: 1297 assert(!"not reached"); 1298 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1299 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1300 fail("bad condition\n"); 1301 return; 1302 } 1303 return; 1304 } 1305 1306 this->result = reg_undef; 1307 ir->condition->accept(this); 1308 1309 fs_inst *inst = emit(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0)); 1310 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1311} 1312 1313void 1314fs_visitor::visit(ir_if *ir) 1315{ 1316 fs_inst *inst; 1317 1318 if (intel->gen != 6 && c->dispatch_width == 16) { 1319 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1320 } 1321 1322 /* Don't point the annotation at the if statement, because then it plus 1323 * the then and else blocks get printed. 1324 */ 1325 this->base_ir = ir->condition; 1326 1327 if (intel->gen == 6) { 1328 emit_if_gen6(ir); 1329 } else { 1330 emit_bool_to_cond_code(ir->condition); 1331 1332 inst = emit(BRW_OPCODE_IF); 1333 inst->predicated = true; 1334 } 1335 1336 foreach_iter(exec_list_iterator, iter, ir->then_instructions) { 1337 ir_instruction *ir = (ir_instruction *)iter.get(); 1338 this->base_ir = ir; 1339 this->result = reg_undef; 1340 ir->accept(this); 1341 } 1342 1343 if (!ir->else_instructions.is_empty()) { 1344 emit(BRW_OPCODE_ELSE); 1345 1346 foreach_iter(exec_list_iterator, iter, ir->else_instructions) { 1347 ir_instruction *ir = (ir_instruction *)iter.get(); 1348 this->base_ir = ir; 1349 this->result = reg_undef; 1350 ir->accept(this); 1351 } 1352 } 1353 1354 emit(BRW_OPCODE_ENDIF); 1355} 1356 1357void 1358fs_visitor::visit(ir_loop *ir) 1359{ 1360 fs_reg counter = reg_undef; 1361 1362 if (c->dispatch_width == 16) { 1363 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1364 } 1365 1366 if (ir->counter) { 1367 this->base_ir = ir->counter; 1368 ir->counter->accept(this); 1369 counter = *(variable_storage(ir->counter)); 1370 1371 if (ir->from) { 1372 this->result = counter; 1373 1374 this->base_ir = ir->from; 1375 this->result = counter; 1376 ir->from->accept(this); 1377 1378 if (!this->result.equals(&counter)) 1379 emit(BRW_OPCODE_MOV, counter, this->result); 1380 } 1381 } 1382 1383 emit(BRW_OPCODE_DO); 1384 1385 if (ir->to) { 1386 this->base_ir = ir->to; 1387 this->result = reg_undef; 1388 ir->to->accept(this); 1389 1390 fs_inst *inst = emit(BRW_OPCODE_CMP, reg_null_cmp, counter, this->result); 1391 inst->conditional_mod = brw_conditional_for_comparison(ir->cmp); 1392 1393 inst = emit(BRW_OPCODE_BREAK); 1394 inst->predicated = true; 1395 } 1396 1397 foreach_iter(exec_list_iterator, iter, ir->body_instructions) { 1398 ir_instruction *ir = (ir_instruction *)iter.get(); 1399 1400 this->base_ir = ir; 1401 this->result = reg_undef; 1402 ir->accept(this); 1403 } 1404 1405 if (ir->increment) { 1406 this->base_ir = ir->increment; 1407 this->result = reg_undef; 1408 ir->increment->accept(this); 1409 emit(BRW_OPCODE_ADD, counter, counter, this->result); 1410 } 1411 1412 emit(BRW_OPCODE_WHILE); 1413} 1414 1415void 1416fs_visitor::visit(ir_loop_jump *ir) 1417{ 1418 switch (ir->mode) { 1419 case ir_loop_jump::jump_break: 1420 emit(BRW_OPCODE_BREAK); 1421 break; 1422 case ir_loop_jump::jump_continue: 1423 emit(BRW_OPCODE_CONTINUE); 1424 break; 1425 } 1426} 1427 1428void 1429fs_visitor::visit(ir_call *ir) 1430{ 1431 assert(!"FINISHME"); 1432} 1433 1434void 1435fs_visitor::visit(ir_return *ir) 1436{ 1437 assert(!"FINISHME"); 1438} 1439 1440void 1441fs_visitor::visit(ir_function *ir) 1442{ 1443 /* Ignore function bodies other than main() -- we shouldn't see calls to 1444 * them since they should all be inlined before we get to ir_to_mesa. 1445 */ 1446 if (strcmp(ir->name, "main") == 0) { 1447 const ir_function_signature *sig; 1448 exec_list empty; 1449 1450 sig = ir->matching_signature(&empty); 1451 1452 assert(sig); 1453 1454 foreach_iter(exec_list_iterator, iter, sig->body) { 1455 ir_instruction *ir = (ir_instruction *)iter.get(); 1456 this->base_ir = ir; 1457 this->result = reg_undef; 1458 ir->accept(this); 1459 } 1460 } 1461} 1462 1463void 1464fs_visitor::visit(ir_function_signature *ir) 1465{ 1466 assert(!"not reached"); 1467 (void)ir; 1468} 1469 1470fs_inst * 1471fs_visitor::emit(fs_inst inst) 1472{ 1473 fs_inst *list_inst = new(mem_ctx) fs_inst; 1474 *list_inst = inst; 1475 1476 if (force_uncompressed_stack > 0) 1477 list_inst->force_uncompressed = true; 1478 else if (force_sechalf_stack > 0) 1479 list_inst->force_sechalf = true; 1480 1481 list_inst->annotation = this->current_annotation; 1482 list_inst->ir = this->base_ir; 1483 1484 this->instructions.push_tail(list_inst); 1485 1486 return list_inst; 1487} 1488 1489/** Emits a dummy fragment shader consisting of magenta for bringup purposes. */ 1490void 1491fs_visitor::emit_dummy_fs() 1492{ 1493 /* Everyone's favorite color. */ 1494 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2), fs_reg(1.0f)); 1495 emit(BRW_OPCODE_MOV, fs_reg(MRF, 3), fs_reg(0.0f)); 1496 emit(BRW_OPCODE_MOV, fs_reg(MRF, 4), fs_reg(1.0f)); 1497 emit(BRW_OPCODE_MOV, fs_reg(MRF, 5), fs_reg(0.0f)); 1498 1499 fs_inst *write; 1500 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0)); 1501 write->base_mrf = 0; 1502} 1503 1504/* The register location here is relative to the start of the URB 1505 * data. It will get adjusted to be a real location before 1506 * generate_code() time. 1507 */ 1508struct brw_reg 1509fs_visitor::interp_reg(int location, int channel) 1510{ 1511 int regnr = urb_setup[location] * 2 + channel / 2; 1512 int stride = (channel & 1) * 4; 1513 1514 assert(urb_setup[location] != -1); 1515 1516 return brw_vec1_grf(regnr, stride); 1517} 1518 1519/** Emits the interpolation for the varying inputs. */ 1520void 1521fs_visitor::emit_interpolation_setup_gen4() 1522{ 1523 this->current_annotation = "compute pixel centers"; 1524 this->pixel_x = fs_reg(this, glsl_type::uint_type); 1525 this->pixel_y = fs_reg(this, glsl_type::uint_type); 1526 this->pixel_x.type = BRW_REGISTER_TYPE_UW; 1527 this->pixel_y.type = BRW_REGISTER_TYPE_UW; 1528 1529 emit(FS_OPCODE_PIXEL_X, this->pixel_x); 1530 emit(FS_OPCODE_PIXEL_Y, this->pixel_y); 1531 1532 this->current_annotation = "compute pixel deltas from v0"; 1533 if (brw->has_pln) { 1534 this->delta_x = fs_reg(this, glsl_type::vec2_type); 1535 this->delta_y = this->delta_x; 1536 this->delta_y.reg_offset++; 1537 } else { 1538 this->delta_x = fs_reg(this, glsl_type::float_type); 1539 this->delta_y = fs_reg(this, glsl_type::float_type); 1540 } 1541 emit(BRW_OPCODE_ADD, this->delta_x, 1542 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))); 1543 emit(BRW_OPCODE_ADD, this->delta_y, 1544 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))); 1545 1546 this->current_annotation = "compute pos.w and 1/pos.w"; 1547 /* Compute wpos.w. It's always in our setup, since it's needed to 1548 * interpolate the other attributes. 1549 */ 1550 this->wpos_w = fs_reg(this, glsl_type::float_type); 1551 emit(FS_OPCODE_LINTERP, wpos_w, this->delta_x, this->delta_y, 1552 interp_reg(FRAG_ATTRIB_WPOS, 3)); 1553 /* Compute the pixel 1/W value from wpos.w. */ 1554 this->pixel_w = fs_reg(this, glsl_type::float_type); 1555 emit_math(FS_OPCODE_RCP, this->pixel_w, wpos_w); 1556 this->current_annotation = NULL; 1557} 1558 1559/** Emits the interpolation for the varying inputs. */ 1560void 1561fs_visitor::emit_interpolation_setup_gen6() 1562{ 1563 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); 1564 1565 /* If the pixel centers end up used, the setup is the same as for gen4. */ 1566 this->current_annotation = "compute pixel centers"; 1567 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type); 1568 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type); 1569 int_pixel_x.type = BRW_REGISTER_TYPE_UW; 1570 int_pixel_y.type = BRW_REGISTER_TYPE_UW; 1571 emit(BRW_OPCODE_ADD, 1572 int_pixel_x, 1573 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), 1574 fs_reg(brw_imm_v(0x10101010))); 1575 emit(BRW_OPCODE_ADD, 1576 int_pixel_y, 1577 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), 1578 fs_reg(brw_imm_v(0x11001100))); 1579 1580 /* As of gen6, we can no longer mix float and int sources. We have 1581 * to turn the integer pixel centers into floats for their actual 1582 * use. 1583 */ 1584 this->pixel_x = fs_reg(this, glsl_type::float_type); 1585 this->pixel_y = fs_reg(this, glsl_type::float_type); 1586 emit(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x); 1587 emit(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y); 1588 1589 this->current_annotation = "compute pos.w"; 1590 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0)); 1591 this->wpos_w = fs_reg(this, glsl_type::float_type); 1592 emit_math(FS_OPCODE_RCP, this->wpos_w, this->pixel_w); 1593 1594 this->delta_x = fs_reg(brw_vec8_grf(2, 0)); 1595 this->delta_y = fs_reg(brw_vec8_grf(3, 0)); 1596 1597 this->current_annotation = NULL; 1598} 1599 1600void 1601fs_visitor::emit_color_write(int index, int first_color_mrf, fs_reg color) 1602{ 1603 int reg_width = c->dispatch_width / 8; 1604 1605 if (c->dispatch_width == 8 || intel->gen == 6) { 1606 /* SIMD8 write looks like: 1607 * m + 0: r0 1608 * m + 1: r1 1609 * m + 2: g0 1610 * m + 3: g1 1611 * 1612 * gen6 SIMD16 DP write looks like: 1613 * m + 0: r0 1614 * m + 1: r1 1615 * m + 2: g0 1616 * m + 3: g1 1617 * m + 4: b0 1618 * m + 5: b1 1619 * m + 6: a0 1620 * m + 7: a1 1621 */ 1622 emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index * reg_width), 1623 color); 1624 } else { 1625 /* pre-gen6 SIMD16 single source DP write looks like: 1626 * m + 0: r0 1627 * m + 1: g0 1628 * m + 2: b0 1629 * m + 3: a0 1630 * m + 4: r1 1631 * m + 5: g1 1632 * m + 6: b1 1633 * m + 7: a1 1634 */ 1635 if (brw->has_compr4) { 1636 /* By setting the high bit of the MRF register number, we 1637 * indicate that we want COMPR4 mode - instead of doing the 1638 * usual destination + 1 for the second half we get 1639 * destination + 4. 1640 */ 1641 emit(BRW_OPCODE_MOV, 1642 fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index), color); 1643 } else { 1644 push_force_uncompressed(); 1645 emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index), color); 1646 pop_force_uncompressed(); 1647 1648 push_force_sechalf(); 1649 color.sechalf = true; 1650 emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index + 4), color); 1651 pop_force_sechalf(); 1652 color.sechalf = false; 1653 } 1654 } 1655} 1656 1657void 1658fs_visitor::emit_fb_writes() 1659{ 1660 this->current_annotation = "FB write header"; 1661 GLboolean header_present = GL_TRUE; 1662 int nr = 0; 1663 int reg_width = c->dispatch_width / 8; 1664 1665 if (intel->gen >= 6 && 1666 !this->kill_emitted && 1667 c->key.nr_color_regions == 1) { 1668 header_present = false; 1669 } 1670 1671 if (header_present) { 1672 /* m0, m1 header */ 1673 nr += 2; 1674 } 1675 1676 if (c->aa_dest_stencil_reg) { 1677 push_force_uncompressed(); 1678 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++), 1679 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))); 1680 pop_force_uncompressed(); 1681 } 1682 1683 /* Reserve space for color. It'll be filled in per MRT below. */ 1684 int color_mrf = nr; 1685 nr += 4 * reg_width; 1686 1687 if (c->source_depth_to_render_target) { 1688 if (intel->gen == 6 && c->dispatch_width == 16) { 1689 /* For outputting oDepth on gen6, SIMD8 writes have to be 1690 * used. This would require 8-wide moves of each half to 1691 * message regs, kind of like pre-gen5 SIMD16 FB writes. 1692 * Just bail on doing so for now. 1693 */ 1694 fail("Missing support for simd16 depth writes on gen6\n"); 1695 } 1696 1697 if (c->computes_depth) { 1698 /* Hand over gl_FragDepth. */ 1699 assert(this->frag_depth); 1700 fs_reg depth = *(variable_storage(this->frag_depth)); 1701 1702 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), depth); 1703 } else { 1704 /* Pass through the payload depth. */ 1705 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1706 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))); 1707 } 1708 nr += reg_width; 1709 } 1710 1711 if (c->dest_depth_reg) { 1712 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1713 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))); 1714 nr += reg_width; 1715 } 1716 1717 fs_reg color = reg_undef; 1718 if (this->frag_color) 1719 color = *(variable_storage(this->frag_color)); 1720 else if (this->frag_data) { 1721 color = *(variable_storage(this->frag_data)); 1722 color.type = BRW_REGISTER_TYPE_F; 1723 } 1724 1725 for (int target = 0; target < c->key.nr_color_regions; target++) { 1726 this->current_annotation = ralloc_asprintf(this->mem_ctx, 1727 "FB write target %d", 1728 target); 1729 if (this->frag_color || this->frag_data) { 1730 for (int i = 0; i < 4; i++) { 1731 emit_color_write(i, color_mrf, color); 1732 color.reg_offset++; 1733 } 1734 } 1735 1736 if (this->frag_color) 1737 color.reg_offset -= 4; 1738 1739 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1740 inst->target = target; 1741 inst->base_mrf = 0; 1742 inst->mlen = nr; 1743 if (target == c->key.nr_color_regions - 1) 1744 inst->eot = true; 1745 inst->header_present = header_present; 1746 } 1747 1748 if (c->key.nr_color_regions == 0) { 1749 if (c->key.alpha_test && (this->frag_color || this->frag_data)) { 1750 /* If the alpha test is enabled but there's no color buffer, 1751 * we still need to send alpha out the pipeline to our null 1752 * renderbuffer. 1753 */ 1754 color.reg_offset += 3; 1755 emit_color_write(3, color_mrf, color); 1756 } 1757 1758 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1759 inst->base_mrf = 0; 1760 inst->mlen = nr; 1761 inst->eot = true; 1762 inst->header_present = header_present; 1763 } 1764 1765 this->current_annotation = NULL; 1766} 1767