brw_fs_visitor.cpp revision 4eeb4c150598605d1be3ce6674fa63076a720ae9
1/* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24/** @file brw_fs_visitor.cpp 25 * 26 * This file supports generating the FS LIR from the GLSL IR. The LIR 27 * makes it easier to do backend-specific optimizations than doing so 28 * in the GLSL IR or in the native code. 29 */ 30extern "C" { 31 32#include <sys/types.h> 33 34#include "main/macros.h" 35#include "main/shaderobj.h" 36#include "main/uniforms.h" 37#include "program/prog_parameter.h" 38#include "program/prog_print.h" 39#include "program/prog_optimize.h" 40#include "program/register_allocate.h" 41#include "program/sampler.h" 42#include "program/hash_table.h" 43#include "brw_context.h" 44#include "brw_eu.h" 45#include "brw_wm.h" 46} 47#include "brw_shader.h" 48#include "brw_fs.h" 49#include "../glsl/glsl_types.h" 50#include "../glsl/ir_optimization.h" 51#include "../glsl/ir_print_visitor.h" 52 53void 54fs_visitor::visit(ir_variable *ir) 55{ 56 fs_reg *reg = NULL; 57 58 if (variable_storage(ir)) 59 return; 60 61 if (strcmp(ir->name, "gl_FragColor") == 0) { 62 this->frag_color = ir; 63 } else if (strcmp(ir->name, "gl_FragData") == 0) { 64 this->frag_data = ir; 65 } else if (strcmp(ir->name, "gl_FragDepth") == 0) { 66 this->frag_depth = ir; 67 } 68 69 if (ir->mode == ir_var_in) { 70 if (!strcmp(ir->name, "gl_FragCoord")) { 71 reg = emit_fragcoord_interpolation(ir); 72 } else if (!strcmp(ir->name, "gl_FrontFacing")) { 73 reg = emit_frontfacing_interpolation(ir); 74 } else { 75 reg = emit_general_interpolation(ir); 76 } 77 assert(reg); 78 hash_table_insert(this->variable_ht, reg, ir); 79 return; 80 } 81 82 if (ir->mode == ir_var_uniform) { 83 int param_index = c->prog_data.nr_params; 84 85 if (c->dispatch_width == 16) { 86 if (!variable_storage(ir)) { 87 fail("Failed to find uniform '%s' in 16-wide\n", ir->name); 88 } 89 return; 90 } 91 92 if (!strncmp(ir->name, "gl_", 3)) { 93 setup_builtin_uniform_values(ir); 94 } else { 95 setup_uniform_values(ir->location, ir->type); 96 } 97 98 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index); 99 reg->type = brw_type_for_base_type(ir->type); 100 } 101 102 if (!reg) 103 reg = new(this->mem_ctx) fs_reg(this, ir->type); 104 105 hash_table_insert(this->variable_ht, reg, ir); 106} 107 108void 109fs_visitor::visit(ir_dereference_variable *ir) 110{ 111 fs_reg *reg = variable_storage(ir->var); 112 this->result = *reg; 113} 114 115void 116fs_visitor::visit(ir_dereference_record *ir) 117{ 118 const glsl_type *struct_type = ir->record->type; 119 120 ir->record->accept(this); 121 122 unsigned int offset = 0; 123 for (unsigned int i = 0; i < struct_type->length; i++) { 124 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0) 125 break; 126 offset += type_size(struct_type->fields.structure[i].type); 127 } 128 this->result.reg_offset += offset; 129 this->result.type = brw_type_for_base_type(ir->type); 130} 131 132void 133fs_visitor::visit(ir_dereference_array *ir) 134{ 135 ir_constant *index; 136 int element_size; 137 138 ir->array->accept(this); 139 index = ir->array_index->as_constant(); 140 141 element_size = type_size(ir->type); 142 this->result.type = brw_type_for_base_type(ir->type); 143 144 if (index) { 145 assert(this->result.file == UNIFORM || this->result.file == GRF); 146 this->result.reg_offset += index->value.i[0] * element_size; 147 } else { 148 assert(!"FINISHME: non-constant array element"); 149 } 150} 151 152/* Instruction selection: Produce a MOV.sat instead of 153 * MIN(MAX(val, 0), 1) when possible. 154 */ 155bool 156fs_visitor::try_emit_saturate(ir_expression *ir) 157{ 158 ir_rvalue *sat_val = ir->as_rvalue_to_saturate(); 159 160 if (!sat_val) 161 return false; 162 163 this->result = reg_undef; 164 sat_val->accept(this); 165 fs_reg src = this->result; 166 167 this->result = fs_reg(this, ir->type); 168 fs_inst *inst = emit(BRW_OPCODE_MOV, this->result, src); 169 inst->saturate = true; 170 171 return true; 172} 173 174void 175fs_visitor::visit(ir_expression *ir) 176{ 177 unsigned int operand; 178 fs_reg op[2], temp; 179 fs_inst *inst; 180 181 assert(ir->get_num_operands() <= 2); 182 183 if (try_emit_saturate(ir)) 184 return; 185 186 /* This is where our caller would like us to put the result, if possible. */ 187 fs_reg saved_result_storage = this->result; 188 189 for (operand = 0; operand < ir->get_num_operands(); operand++) { 190 this->result = reg_undef; 191 ir->operands[operand]->accept(this); 192 if (this->result.file == BAD_FILE) { 193 ir_print_visitor v; 194 fail("Failed to get tree for expression operand:\n"); 195 ir->operands[operand]->accept(&v); 196 } 197 op[operand] = this->result; 198 199 /* Matrix expression operands should have been broken down to vector 200 * operations already. 201 */ 202 assert(!ir->operands[operand]->type->is_matrix()); 203 /* And then those vector operands should have been broken down to scalar. 204 */ 205 assert(!ir->operands[operand]->type->is_vector()); 206 } 207 208 /* Inherit storage from our parent if possible, and otherwise we 209 * alloc a temporary. 210 */ 211 if (saved_result_storage.file == BAD_FILE) { 212 this->result = fs_reg(this, ir->type); 213 } else { 214 this->result = saved_result_storage; 215 } 216 217 switch (ir->operation) { 218 case ir_unop_logic_not: 219 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is 220 * ones complement of the whole register, not just bit 0. 221 */ 222 emit(BRW_OPCODE_XOR, this->result, op[0], fs_reg(1)); 223 break; 224 case ir_unop_neg: 225 op[0].negate = !op[0].negate; 226 this->result = op[0]; 227 break; 228 case ir_unop_abs: 229 op[0].abs = true; 230 op[0].negate = false; 231 this->result = op[0]; 232 break; 233 case ir_unop_sign: 234 temp = fs_reg(this, ir->type); 235 236 /* Unalias the destination. (imagine a = sign(a)) */ 237 this->result = fs_reg(this, ir->type); 238 239 emit(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)); 240 241 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 242 inst->conditional_mod = BRW_CONDITIONAL_G; 243 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)); 244 inst->predicated = true; 245 246 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 247 inst->conditional_mod = BRW_CONDITIONAL_L; 248 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)); 249 inst->predicated = true; 250 251 break; 252 case ir_unop_rcp: 253 emit_math(SHADER_OPCODE_RCP, this->result, op[0]); 254 break; 255 256 case ir_unop_exp2: 257 emit_math(SHADER_OPCODE_EXP2, this->result, op[0]); 258 break; 259 case ir_unop_log2: 260 emit_math(SHADER_OPCODE_LOG2, this->result, op[0]); 261 break; 262 case ir_unop_exp: 263 case ir_unop_log: 264 assert(!"not reached: should be handled by ir_explog_to_explog2"); 265 break; 266 case ir_unop_sin: 267 case ir_unop_sin_reduced: 268 emit_math(SHADER_OPCODE_SIN, this->result, op[0]); 269 break; 270 case ir_unop_cos: 271 case ir_unop_cos_reduced: 272 emit_math(SHADER_OPCODE_COS, this->result, op[0]); 273 break; 274 275 case ir_unop_dFdx: 276 emit(FS_OPCODE_DDX, this->result, op[0]); 277 break; 278 case ir_unop_dFdy: 279 emit(FS_OPCODE_DDY, this->result, op[0]); 280 break; 281 282 case ir_binop_add: 283 emit(BRW_OPCODE_ADD, this->result, op[0], op[1]); 284 break; 285 case ir_binop_sub: 286 assert(!"not reached: should be handled by ir_sub_to_add_neg"); 287 break; 288 289 case ir_binop_mul: 290 if (ir->type->is_integer()) { 291 /* For integer multiplication, the MUL uses the low 16 bits 292 * of one of the operands (src0 on gen6, src1 on gen7). The 293 * MACH accumulates in the contribution of the upper 16 bits 294 * of that operand. 295 * 296 * FINISHME: Emit just the MUL if we know an operand is small 297 * enough. 298 */ 299 struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_D); 300 301 emit(BRW_OPCODE_MUL, acc, op[0], op[1]); 302 emit(BRW_OPCODE_MACH, reg_null_d, op[0], op[1]); 303 emit(BRW_OPCODE_MOV, this->result, fs_reg(acc)); 304 } else { 305 emit(BRW_OPCODE_MUL, this->result, op[0], op[1]); 306 } 307 break; 308 case ir_binop_div: 309 assert(!"not reached: should be handled by ir_div_to_mul_rcp"); 310 break; 311 case ir_binop_mod: 312 assert(!"ir_binop_mod should have been converted to b * fract(a/b)"); 313 break; 314 315 case ir_binop_less: 316 case ir_binop_greater: 317 case ir_binop_lequal: 318 case ir_binop_gequal: 319 case ir_binop_equal: 320 case ir_binop_all_equal: 321 case ir_binop_nequal: 322 case ir_binop_any_nequal: 323 temp = this->result; 324 /* original gen4 does implicit conversion before comparison. */ 325 if (intel->gen < 5) 326 temp.type = op[0].type; 327 328 inst = emit(BRW_OPCODE_CMP, temp, op[0], op[1]); 329 inst->conditional_mod = brw_conditional_for_comparison(ir->operation); 330 emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)); 331 break; 332 333 case ir_binop_logic_xor: 334 emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 335 break; 336 337 case ir_binop_logic_or: 338 emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 339 break; 340 341 case ir_binop_logic_and: 342 emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 343 break; 344 345 case ir_binop_dot: 346 case ir_unop_any: 347 assert(!"not reached: should be handled by brw_fs_channel_expressions"); 348 break; 349 350 case ir_unop_noise: 351 assert(!"not reached: should be handled by lower_noise"); 352 break; 353 354 case ir_quadop_vector: 355 assert(!"not reached: should be handled by lower_quadop_vector"); 356 break; 357 358 case ir_unop_sqrt: 359 emit_math(SHADER_OPCODE_SQRT, this->result, op[0]); 360 break; 361 362 case ir_unop_rsq: 363 emit_math(SHADER_OPCODE_RSQ, this->result, op[0]); 364 break; 365 366 case ir_unop_i2u: 367 op[0].type = BRW_REGISTER_TYPE_UD; 368 this->result = op[0]; 369 break; 370 case ir_unop_u2i: 371 op[0].type = BRW_REGISTER_TYPE_D; 372 this->result = op[0]; 373 break; 374 case ir_unop_i2f: 375 case ir_unop_b2f: 376 case ir_unop_b2i: 377 case ir_unop_f2i: 378 emit(BRW_OPCODE_MOV, this->result, op[0]); 379 break; 380 case ir_unop_f2b: 381 case ir_unop_i2b: 382 temp = this->result; 383 /* original gen4 does implicit conversion before comparison. */ 384 if (intel->gen < 5) 385 temp.type = op[0].type; 386 387 inst = emit(BRW_OPCODE_CMP, temp, op[0], fs_reg(0.0f)); 388 inst->conditional_mod = BRW_CONDITIONAL_NZ; 389 inst = emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(1)); 390 break; 391 392 case ir_unop_trunc: 393 emit(BRW_OPCODE_RNDZ, this->result, op[0]); 394 break; 395 case ir_unop_ceil: 396 op[0].negate = !op[0].negate; 397 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 398 this->result.negate = true; 399 break; 400 case ir_unop_floor: 401 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 402 break; 403 case ir_unop_fract: 404 inst = emit(BRW_OPCODE_FRC, this->result, op[0]); 405 break; 406 case ir_unop_round_even: 407 emit(BRW_OPCODE_RNDE, this->result, op[0]); 408 break; 409 410 case ir_binop_min: 411 if (intel->gen >= 6) { 412 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 413 inst->conditional_mod = BRW_CONDITIONAL_L; 414 } else { 415 /* Unalias the destination */ 416 this->result = fs_reg(this, ir->type); 417 418 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 419 inst->conditional_mod = BRW_CONDITIONAL_L; 420 421 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 422 inst->predicated = true; 423 } 424 break; 425 case ir_binop_max: 426 if (intel->gen >= 6) { 427 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 428 inst->conditional_mod = BRW_CONDITIONAL_GE; 429 } else { 430 /* Unalias the destination */ 431 this->result = fs_reg(this, ir->type); 432 433 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 434 inst->conditional_mod = BRW_CONDITIONAL_G; 435 436 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 437 inst->predicated = true; 438 } 439 break; 440 441 case ir_binop_pow: 442 emit_math(SHADER_OPCODE_POW, this->result, op[0], op[1]); 443 break; 444 445 case ir_unop_bit_not: 446 inst = emit(BRW_OPCODE_NOT, this->result, op[0]); 447 break; 448 case ir_binop_bit_and: 449 inst = emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 450 break; 451 case ir_binop_bit_xor: 452 inst = emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 453 break; 454 case ir_binop_bit_or: 455 inst = emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 456 break; 457 458 case ir_unop_u2f: 459 case ir_binop_lshift: 460 case ir_binop_rshift: 461 assert(!"GLSL 1.30 features unsupported"); 462 break; 463 } 464} 465 466void 467fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r, 468 const glsl_type *type, bool predicated) 469{ 470 switch (type->base_type) { 471 case GLSL_TYPE_FLOAT: 472 case GLSL_TYPE_UINT: 473 case GLSL_TYPE_INT: 474 case GLSL_TYPE_BOOL: 475 for (unsigned int i = 0; i < type->components(); i++) { 476 l.type = brw_type_for_base_type(type); 477 r.type = brw_type_for_base_type(type); 478 479 if (predicated || !l.equals(&r)) { 480 fs_inst *inst = emit(BRW_OPCODE_MOV, l, r); 481 inst->predicated = predicated; 482 } 483 484 l.reg_offset++; 485 r.reg_offset++; 486 } 487 break; 488 case GLSL_TYPE_ARRAY: 489 for (unsigned int i = 0; i < type->length; i++) { 490 emit_assignment_writes(l, r, type->fields.array, predicated); 491 } 492 break; 493 494 case GLSL_TYPE_STRUCT: 495 for (unsigned int i = 0; i < type->length; i++) { 496 emit_assignment_writes(l, r, type->fields.structure[i].type, 497 predicated); 498 } 499 break; 500 501 case GLSL_TYPE_SAMPLER: 502 break; 503 504 default: 505 assert(!"not reached"); 506 break; 507 } 508} 509 510void 511fs_visitor::visit(ir_assignment *ir) 512{ 513 fs_reg l, r; 514 fs_inst *inst; 515 516 /* FINISHME: arrays on the lhs */ 517 this->result = reg_undef; 518 ir->lhs->accept(this); 519 l = this->result; 520 521 /* If we're doing a direct assignment, an RHS expression could 522 * drop its result right into our destination. Otherwise, tell it 523 * not to. 524 */ 525 if (ir->condition || 526 !(ir->lhs->type->is_scalar() || 527 (ir->lhs->type->is_vector() && 528 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1))) { 529 this->result = reg_undef; 530 } 531 532 ir->rhs->accept(this); 533 r = this->result; 534 535 assert(l.file != BAD_FILE); 536 assert(r.file != BAD_FILE); 537 538 if (ir->condition) { 539 emit_bool_to_cond_code(ir->condition); 540 } 541 542 if (ir->lhs->type->is_scalar() || 543 ir->lhs->type->is_vector()) { 544 for (int i = 0; i < ir->lhs->type->vector_elements; i++) { 545 if (ir->write_mask & (1 << i)) { 546 if (ir->condition) { 547 inst = emit(BRW_OPCODE_MOV, l, r); 548 inst->predicated = true; 549 } else if (!l.equals(&r)) { 550 inst = emit(BRW_OPCODE_MOV, l, r); 551 } 552 553 r.reg_offset++; 554 } 555 l.reg_offset++; 556 } 557 } else { 558 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL); 559 } 560} 561 562fs_inst * 563fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate, 564 int sampler) 565{ 566 int mlen; 567 int base_mrf = 1; 568 bool simd16 = false; 569 fs_reg orig_dst; 570 571 /* g0 header. */ 572 mlen = 1; 573 574 if (ir->shadow_comparitor && ir->op != ir_txd) { 575 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 576 fs_inst *inst = emit(BRW_OPCODE_MOV, 577 fs_reg(MRF, base_mrf + mlen + i), coordinate); 578 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 579 inst->saturate = true; 580 581 coordinate.reg_offset++; 582 } 583 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 584 mlen += 3; 585 586 if (ir->op == ir_tex) { 587 /* There's no plain shadow compare message, so we use shadow 588 * compare with a bias of 0.0. 589 */ 590 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)); 591 mlen++; 592 } else if (ir->op == ir_txb) { 593 this->result = reg_undef; 594 ir->lod_info.bias->accept(this); 595 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 596 mlen++; 597 } else { 598 assert(ir->op == ir_txl); 599 this->result = reg_undef; 600 ir->lod_info.lod->accept(this); 601 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 602 mlen++; 603 } 604 605 this->result = reg_undef; 606 ir->shadow_comparitor->accept(this); 607 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 608 mlen++; 609 } else if (ir->op == ir_tex) { 610 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 611 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), 612 coordinate); 613 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 614 inst->saturate = true; 615 coordinate.reg_offset++; 616 } 617 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 618 mlen += 3; 619 } else if (ir->op == ir_txd) { 620 this->result = reg_undef; 621 ir->lod_info.grad.dPdx->accept(this); 622 fs_reg dPdx = this->result; 623 624 this->result = reg_undef; 625 ir->lod_info.grad.dPdy->accept(this); 626 fs_reg dPdy = this->result; 627 628 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 629 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); 630 coordinate.reg_offset++; 631 } 632 /* the slots for u and v are always present, but r is optional */ 633 mlen += MAX2(ir->coordinate->type->vector_elements, 2); 634 635 /* P = u, v, r 636 * dPdx = dudx, dvdx, drdx 637 * dPdy = dudy, dvdy, drdy 638 * 639 * 1-arg: Does not exist. 640 * 641 * 2-arg: dudx dvdx dudy dvdy 642 * dPdx.x dPdx.y dPdy.x dPdy.y 643 * m4 m5 m6 m7 644 * 645 * 3-arg: dudx dvdx drdx dudy dvdy drdy 646 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z 647 * m5 m6 m7 m8 m9 m10 648 */ 649 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 650 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 651 dPdx.reg_offset++; 652 } 653 mlen += MAX2(ir->lod_info.grad.dPdx->type->vector_elements, 2); 654 655 for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) { 656 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 657 dPdy.reg_offset++; 658 } 659 mlen += MAX2(ir->lod_info.grad.dPdy->type->vector_elements, 2); 660 } else if (ir->op == ir_txs) { 661 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */ 662 simd16 = true; 663 this->result = reg_undef; 664 ir->lod_info.lod->accept(this); 665 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 666 mlen += 2; 667 } else { 668 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod 669 * instructions. We'll need to do SIMD16 here. 670 */ 671 simd16 = true; 672 assert(ir->op == ir_txb || ir->op == ir_txl); 673 674 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 675 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, 676 base_mrf + mlen + i * 2), 677 coordinate); 678 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 679 inst->saturate = true; 680 coordinate.reg_offset++; 681 } 682 683 /* lod/bias appears after u/v/r. */ 684 mlen += 6; 685 686 if (ir->op == ir_txb) { 687 this->result = reg_undef; 688 ir->lod_info.bias->accept(this); 689 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 690 mlen++; 691 } else { 692 this->result = reg_undef; 693 ir->lod_info.lod->accept(this); 694 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 695 mlen++; 696 } 697 698 /* The unused upper half. */ 699 mlen++; 700 } 701 702 if (simd16) { 703 /* Now, since we're doing simd16, the return is 2 interleaved 704 * vec4s where the odd-indexed ones are junk. We'll need to move 705 * this weirdness around to the expected layout. 706 */ 707 orig_dst = dst; 708 const glsl_type *vec_type = 709 glsl_type::get_instance(ir->type->base_type, 4, 1); 710 dst = fs_reg(this, glsl_type::get_array_instance(vec_type, 2)); 711 dst.type = intel->is_g4x ? brw_type_for_base_type(ir->type) 712 : BRW_REGISTER_TYPE_F; 713 } 714 715 fs_inst *inst = NULL; 716 switch (ir->op) { 717 case ir_tex: 718 inst = emit(FS_OPCODE_TEX, dst); 719 break; 720 case ir_txb: 721 inst = emit(FS_OPCODE_TXB, dst); 722 break; 723 case ir_txl: 724 inst = emit(FS_OPCODE_TXL, dst); 725 break; 726 case ir_txd: 727 inst = emit(FS_OPCODE_TXD, dst); 728 break; 729 case ir_txs: 730 inst = emit(FS_OPCODE_TXS, dst); 731 break; 732 case ir_txf: 733 assert(!"GLSL 1.30 features unsupported"); 734 break; 735 } 736 inst->base_mrf = base_mrf; 737 inst->mlen = mlen; 738 inst->header_present = true; 739 740 if (simd16) { 741 for (int i = 0; i < 4; i++) { 742 emit(BRW_OPCODE_MOV, orig_dst, dst); 743 orig_dst.reg_offset++; 744 dst.reg_offset += 2; 745 } 746 } 747 748 return inst; 749} 750 751/* gen5's sampler has slots for u, v, r, array index, then optional 752 * parameters like shadow comparitor or LOD bias. If optional 753 * parameters aren't present, those base slots are optional and don't 754 * need to be included in the message. 755 * 756 * We don't fill in the unnecessary slots regardless, which may look 757 * surprising in the disassembly. 758 */ 759fs_inst * 760fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate, 761 int sampler) 762{ 763 int mlen = 0; 764 int base_mrf = 2; 765 int reg_width = c->dispatch_width / 8; 766 bool header_present = false; 767 const int vector_elements = 768 ir->coordinate ? ir->coordinate->type->vector_elements : 0; 769 770 if (ir->offset) { 771 /* The offsets set up by the ir_texture visitor are in the 772 * m1 header, so we can't go headerless. 773 */ 774 header_present = true; 775 mlen++; 776 base_mrf--; 777 } 778 779 for (int i = 0; i < vector_elements; i++) { 780 fs_inst *inst = emit(BRW_OPCODE_MOV, 781 fs_reg(MRF, base_mrf + mlen + i * reg_width), 782 coordinate); 783 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 784 inst->saturate = true; 785 coordinate.reg_offset++; 786 } 787 mlen += vector_elements * reg_width; 788 789 if (ir->shadow_comparitor && ir->op != ir_txd) { 790 mlen = MAX2(mlen, header_present + 4 * reg_width); 791 792 this->result = reg_undef; 793 ir->shadow_comparitor->accept(this); 794 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 795 mlen += reg_width; 796 } 797 798 fs_inst *inst = NULL; 799 switch (ir->op) { 800 case ir_tex: 801 inst = emit(FS_OPCODE_TEX, dst); 802 break; 803 case ir_txb: 804 this->result = reg_undef; 805 ir->lod_info.bias->accept(this); 806 mlen = MAX2(mlen, header_present + 4 * reg_width); 807 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 808 mlen += reg_width; 809 810 inst = emit(FS_OPCODE_TXB, dst); 811 812 break; 813 case ir_txl: 814 this->result = reg_undef; 815 ir->lod_info.lod->accept(this); 816 mlen = MAX2(mlen, header_present + 4 * reg_width); 817 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 818 mlen += reg_width; 819 820 inst = emit(FS_OPCODE_TXL, dst); 821 break; 822 case ir_txd: { 823 this->result = reg_undef; 824 ir->lod_info.grad.dPdx->accept(this); 825 fs_reg dPdx = this->result; 826 827 this->result = reg_undef; 828 ir->lod_info.grad.dPdy->accept(this); 829 fs_reg dPdy = this->result; 830 831 mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */ 832 833 /** 834 * P = u, v, r 835 * dPdx = dudx, dvdx, drdx 836 * dPdy = dudy, dvdy, drdy 837 * 838 * Load up these values: 839 * - dudx dudy dvdx dvdy drdx drdy 840 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z 841 */ 842 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 843 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 844 dPdx.reg_offset++; 845 mlen += reg_width; 846 847 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 848 dPdy.reg_offset++; 849 mlen += reg_width; 850 } 851 852 inst = emit(FS_OPCODE_TXD, dst); 853 break; 854 } 855 case ir_txs: 856 this->result = reg_undef; 857 ir->lod_info.lod->accept(this); 858 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 859 mlen += reg_width; 860 inst = emit(FS_OPCODE_TXS, dst); 861 break; 862 case ir_txf: 863 assert(!"GLSL 1.30 features unsupported"); 864 break; 865 } 866 inst->base_mrf = base_mrf; 867 inst->mlen = mlen; 868 inst->header_present = header_present; 869 870 if (mlen > 11) { 871 fail("Message length >11 disallowed by hardware\n"); 872 } 873 874 return inst; 875} 876 877fs_inst * 878fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate, 879 int sampler) 880{ 881 int mlen = 0; 882 int base_mrf = 2; 883 int reg_width = c->dispatch_width / 8; 884 bool header_present = false; 885 886 if (ir->offset) { 887 /* The offsets set up by the ir_texture visitor are in the 888 * m1 header, so we can't go headerless. 889 */ 890 header_present = true; 891 mlen++; 892 base_mrf--; 893 } 894 895 if (ir->shadow_comparitor && ir->op != ir_txd) { 896 this->result = reg_undef; 897 ir->shadow_comparitor->accept(this); 898 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 899 mlen += reg_width; 900 } 901 902 /* Set up the LOD info */ 903 switch (ir->op) { 904 case ir_tex: 905 break; 906 case ir_txb: 907 this->result = reg_undef; 908 ir->lod_info.bias->accept(this); 909 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 910 mlen += reg_width; 911 break; 912 case ir_txl: 913 this->result = reg_undef; 914 ir->lod_info.lod->accept(this); 915 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 916 mlen += reg_width; 917 break; 918 case ir_txd: { 919 if (c->dispatch_width == 16) 920 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode."); 921 922 this->result = reg_undef; 923 ir->lod_info.grad.dPdx->accept(this); 924 fs_reg dPdx = this->result; 925 926 this->result = reg_undef; 927 ir->lod_info.grad.dPdy->accept(this); 928 fs_reg dPdy = this->result; 929 930 /* Load dPdx and the coordinate together: 931 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z 932 */ 933 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 934 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 935 coordinate); 936 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 937 inst->saturate = true; 938 coordinate.reg_offset++; 939 mlen += reg_width; 940 941 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 942 dPdx.reg_offset++; 943 mlen += reg_width; 944 945 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 946 dPdy.reg_offset++; 947 mlen += reg_width; 948 } 949 break; 950 } 951 case ir_txs: 952 this->result = reg_undef; 953 ir->lod_info.lod->accept(this); 954 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 955 mlen += reg_width; 956 break; 957 case ir_txf: 958 assert(!"GLSL 1.30 features unsupported"); 959 break; 960 } 961 962 /* Set up the coordinate (except for TXD where it was done earlier) */ 963 if (ir->op != ir_txd && ir->op != ir_txs) { 964 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 965 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 966 coordinate); 967 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 968 inst->saturate = true; 969 coordinate.reg_offset++; 970 mlen += reg_width; 971 } 972 } 973 974 /* Generate the SEND */ 975 fs_inst *inst = NULL; 976 switch (ir->op) { 977 case ir_tex: inst = emit(FS_OPCODE_TEX, dst); break; 978 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break; 979 case ir_txl: inst = emit(FS_OPCODE_TXL, dst); break; 980 case ir_txd: inst = emit(FS_OPCODE_TXD, dst); break; 981 case ir_txf: assert(!"TXF unsupported."); break; 982 case ir_txs: inst = emit(FS_OPCODE_TXS, dst); break; 983 } 984 inst->base_mrf = base_mrf; 985 inst->mlen = mlen; 986 inst->header_present = header_present; 987 988 if (mlen > 11) { 989 fail("Message length >11 disallowed by hardware\n"); 990 } 991 992 return inst; 993} 994 995void 996fs_visitor::visit(ir_texture *ir) 997{ 998 fs_inst *inst = NULL; 999 1000 int sampler = _mesa_get_sampler_uniform_value(ir->sampler, prog, &fp->Base); 1001 sampler = fp->Base.SamplerUnits[sampler]; 1002 1003 /* Our hardware doesn't have a sample_d_c message, so shadow compares 1004 * for textureGrad/TXD need to be emulated with instructions. 1005 */ 1006 bool hw_compare_supported = ir->op != ir_txd; 1007 if (ir->shadow_comparitor && !hw_compare_supported) { 1008 assert(c->key.compare_funcs[sampler] != GL_NONE); 1009 /* No need to even sample for GL_ALWAYS or GL_NEVER...bail early */ 1010 if (c->key.compare_funcs[sampler] == GL_ALWAYS) 1011 return swizzle_result(ir, fs_reg(1.0f), sampler); 1012 else if (c->key.compare_funcs[sampler] == GL_NEVER) 1013 return swizzle_result(ir, fs_reg(0.0f), sampler); 1014 } 1015 1016 this->result = reg_undef; 1017 if (ir->coordinate) 1018 ir->coordinate->accept(this); 1019 fs_reg coordinate = this->result; 1020 1021 if (ir->offset != NULL) { 1022 ir_constant *offset = ir->offset->as_constant(); 1023 assert(offset != NULL); 1024 1025 signed char offsets[3]; 1026 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) 1027 offsets[i] = (signed char) offset->value.i[i]; 1028 1029 /* Combine all three offsets into a single unsigned dword: 1030 * 1031 * bits 11:8 - U Offset (X component) 1032 * bits 7:4 - V Offset (Y component) 1033 * bits 3:0 - R Offset (Z component) 1034 */ 1035 unsigned offset_bits = 0; 1036 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) { 1037 const unsigned shift = 4 * (2 - i); 1038 offset_bits |= (offsets[i] << shift) & (0xF << shift); 1039 } 1040 1041 /* Explicitly set up the message header by copying g0 to msg reg m1. */ 1042 emit(BRW_OPCODE_MOV, fs_reg(MRF, 1, BRW_REGISTER_TYPE_UD), 1043 fs_reg(GRF, 0, BRW_REGISTER_TYPE_UD)); 1044 1045 /* Then set the offset bits in DWord 2 of the message header. */ 1046 emit(BRW_OPCODE_MOV, 1047 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 1, 2), 1048 BRW_REGISTER_TYPE_UD)), 1049 fs_reg(brw_imm_uw(offset_bits))); 1050 } 1051 1052 /* Should be lowered by do_lower_texture_projection */ 1053 assert(!ir->projector); 1054 1055 /* The 965 requires the EU to do the normalization of GL rectangle 1056 * texture coordinates. We use the program parameter state 1057 * tracking to get the scaling factor. 1058 */ 1059 if (ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) { 1060 struct gl_program_parameter_list *params = c->fp->program.Base.Parameters; 1061 int tokens[STATE_LENGTH] = { 1062 STATE_INTERNAL, 1063 STATE_TEXRECT_SCALE, 1064 sampler, 1065 0, 1066 0 1067 }; 1068 1069 if (c->dispatch_width == 16) { 1070 fail("rectangle scale uniform setup not supported on 16-wide\n"); 1071 this->result = fs_reg(this, ir->type); 1072 return; 1073 } 1074 1075 c->prog_data.param_convert[c->prog_data.nr_params] = 1076 PARAM_NO_CONVERT; 1077 c->prog_data.param_convert[c->prog_data.nr_params + 1] = 1078 PARAM_NO_CONVERT; 1079 1080 fs_reg scale_x = fs_reg(UNIFORM, c->prog_data.nr_params); 1081 fs_reg scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1); 1082 GLuint index = _mesa_add_state_reference(params, 1083 (gl_state_index *)tokens); 1084 1085 this->param_index[c->prog_data.nr_params] = index; 1086 this->param_offset[c->prog_data.nr_params] = 0; 1087 c->prog_data.nr_params++; 1088 this->param_index[c->prog_data.nr_params] = index; 1089 this->param_offset[c->prog_data.nr_params] = 1; 1090 c->prog_data.nr_params++; 1091 1092 fs_reg dst = fs_reg(this, ir->coordinate->type); 1093 fs_reg src = coordinate; 1094 coordinate = dst; 1095 1096 emit(BRW_OPCODE_MUL, dst, src, scale_x); 1097 dst.reg_offset++; 1098 src.reg_offset++; 1099 emit(BRW_OPCODE_MUL, dst, src, scale_y); 1100 } 1101 1102 /* Writemasking doesn't eliminate channels on SIMD8 texture 1103 * samples, so don't worry about them. 1104 */ 1105 fs_reg dst = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 4, 1)); 1106 1107 if (intel->gen >= 7) { 1108 inst = emit_texture_gen7(ir, dst, coordinate, sampler); 1109 } else if (intel->gen >= 5) { 1110 inst = emit_texture_gen5(ir, dst, coordinate, sampler); 1111 } else { 1112 inst = emit_texture_gen4(ir, dst, coordinate, sampler); 1113 } 1114 1115 /* If there's an offset, we already set up m1. To avoid the implied move, 1116 * use the null register. Otherwise, we want an implied move from g0. 1117 */ 1118 if (ir->offset != NULL || !inst->header_present) 1119 inst->src[0] = reg_undef; 1120 else 1121 inst->src[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW)); 1122 1123 inst->sampler = sampler; 1124 1125 if (ir->shadow_comparitor) { 1126 if (hw_compare_supported) { 1127 inst->shadow_compare = true; 1128 } else { 1129 this->result = reg_undef; 1130 ir->shadow_comparitor->accept(this); 1131 fs_reg ref = this->result; 1132 1133 fs_reg value = dst; 1134 dst = fs_reg(this, glsl_type::vec4_type); 1135 1136 /* FINISHME: This needs to be done pre-filtering. */ 1137 1138 uint32_t conditional = 0; 1139 switch (c->key.compare_funcs[sampler]) { 1140 /* GL_ALWAYS and GL_NEVER were handled at the top of the function */ 1141 case GL_LESS: conditional = BRW_CONDITIONAL_L; break; 1142 case GL_GREATER: conditional = BRW_CONDITIONAL_G; break; 1143 case GL_LEQUAL: conditional = BRW_CONDITIONAL_LE; break; 1144 case GL_GEQUAL: conditional = BRW_CONDITIONAL_GE; break; 1145 case GL_EQUAL: conditional = BRW_CONDITIONAL_EQ; break; 1146 case GL_NOTEQUAL: conditional = BRW_CONDITIONAL_NEQ; break; 1147 default: assert(!"Should not get here: bad shadow compare function"); 1148 } 1149 1150 /* Use conditional moves to load 0 or 1 as the result */ 1151 this->current_annotation = "manual shadow comparison"; 1152 for (int i = 0; i < 4; i++) { 1153 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(0.0f)); 1154 1155 inst = emit(BRW_OPCODE_CMP, reg_null_f, ref, value); 1156 inst->conditional_mod = conditional; 1157 1158 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(1.0f)); 1159 inst->predicated = true; 1160 1161 dst.reg_offset++; 1162 value.reg_offset++; 1163 } 1164 dst.reg_offset = 0; 1165 } 1166 } 1167 1168 swizzle_result(ir, dst, sampler); 1169} 1170 1171/** 1172 * Swizzle the result of a texture result. This is necessary for 1173 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons. 1174 */ 1175void 1176fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler) 1177{ 1178 this->result = orig_val; 1179 1180 if (ir->type == glsl_type::float_type) { 1181 /* Ignore DEPTH_TEXTURE_MODE swizzling. */ 1182 assert(ir->sampler->type->sampler_shadow); 1183 } else if (c->key.tex_swizzles[sampler] != SWIZZLE_NOOP) { 1184 fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type); 1185 1186 for (int i = 0; i < 4; i++) { 1187 int swiz = GET_SWZ(c->key.tex_swizzles[sampler], i); 1188 fs_reg l = swizzled_result; 1189 l.reg_offset += i; 1190 1191 if (swiz == SWIZZLE_ZERO) { 1192 emit(BRW_OPCODE_MOV, l, fs_reg(0.0f)); 1193 } else if (swiz == SWIZZLE_ONE) { 1194 emit(BRW_OPCODE_MOV, l, fs_reg(1.0f)); 1195 } else { 1196 fs_reg r = orig_val; 1197 r.reg_offset += GET_SWZ(c->key.tex_swizzles[sampler], i); 1198 emit(BRW_OPCODE_MOV, l, r); 1199 } 1200 } 1201 this->result = swizzled_result; 1202 } 1203} 1204 1205void 1206fs_visitor::visit(ir_swizzle *ir) 1207{ 1208 this->result = reg_undef; 1209 ir->val->accept(this); 1210 fs_reg val = this->result; 1211 1212 if (ir->type->vector_elements == 1) { 1213 this->result.reg_offset += ir->mask.x; 1214 return; 1215 } 1216 1217 fs_reg result = fs_reg(this, ir->type); 1218 this->result = result; 1219 1220 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 1221 fs_reg channel = val; 1222 int swiz = 0; 1223 1224 switch (i) { 1225 case 0: 1226 swiz = ir->mask.x; 1227 break; 1228 case 1: 1229 swiz = ir->mask.y; 1230 break; 1231 case 2: 1232 swiz = ir->mask.z; 1233 break; 1234 case 3: 1235 swiz = ir->mask.w; 1236 break; 1237 } 1238 1239 channel.reg_offset += swiz; 1240 emit(BRW_OPCODE_MOV, result, channel); 1241 result.reg_offset++; 1242 } 1243} 1244 1245void 1246fs_visitor::visit(ir_discard *ir) 1247{ 1248 assert(ir->condition == NULL); /* FINISHME */ 1249 1250 emit(FS_OPCODE_DISCARD); 1251 kill_emitted = true; 1252} 1253 1254void 1255fs_visitor::visit(ir_constant *ir) 1256{ 1257 /* Set this->result to reg at the bottom of the function because some code 1258 * paths will cause this visitor to be applied to other fields. This will 1259 * cause the value stored in this->result to be modified. 1260 * 1261 * Make reg constant so that it doesn't get accidentally modified along the 1262 * way. Yes, I actually had this problem. :( 1263 */ 1264 const fs_reg reg(this, ir->type); 1265 fs_reg dst_reg = reg; 1266 1267 if (ir->type->is_array()) { 1268 const unsigned size = type_size(ir->type->fields.array); 1269 1270 for (unsigned i = 0; i < ir->type->length; i++) { 1271 this->result = reg_undef; 1272 ir->array_elements[i]->accept(this); 1273 fs_reg src_reg = this->result; 1274 1275 dst_reg.type = src_reg.type; 1276 for (unsigned j = 0; j < size; j++) { 1277 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1278 src_reg.reg_offset++; 1279 dst_reg.reg_offset++; 1280 } 1281 } 1282 } else if (ir->type->is_record()) { 1283 foreach_list(node, &ir->components) { 1284 ir_instruction *const field = (ir_instruction *) node; 1285 const unsigned size = type_size(field->type); 1286 1287 this->result = reg_undef; 1288 field->accept(this); 1289 fs_reg src_reg = this->result; 1290 1291 dst_reg.type = src_reg.type; 1292 for (unsigned j = 0; j < size; j++) { 1293 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1294 src_reg.reg_offset++; 1295 dst_reg.reg_offset++; 1296 } 1297 } 1298 } else { 1299 const unsigned size = type_size(ir->type); 1300 1301 for (unsigned i = 0; i < size; i++) { 1302 switch (ir->type->base_type) { 1303 case GLSL_TYPE_FLOAT: 1304 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i])); 1305 break; 1306 case GLSL_TYPE_UINT: 1307 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i])); 1308 break; 1309 case GLSL_TYPE_INT: 1310 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.i[i])); 1311 break; 1312 case GLSL_TYPE_BOOL: 1313 emit(BRW_OPCODE_MOV, dst_reg, fs_reg((int)ir->value.b[i])); 1314 break; 1315 default: 1316 assert(!"Non-float/uint/int/bool constant"); 1317 } 1318 dst_reg.reg_offset++; 1319 } 1320 } 1321 1322 this->result = reg; 1323} 1324 1325void 1326fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir) 1327{ 1328 ir_expression *expr = ir->as_expression(); 1329 1330 if (expr) { 1331 fs_reg op[2]; 1332 fs_inst *inst; 1333 1334 assert(expr->get_num_operands() <= 2); 1335 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1336 assert(expr->operands[i]->type->is_scalar()); 1337 1338 this->result = reg_undef; 1339 expr->operands[i]->accept(this); 1340 op[i] = this->result; 1341 } 1342 1343 switch (expr->operation) { 1344 case ir_unop_logic_not: 1345 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1)); 1346 inst->conditional_mod = BRW_CONDITIONAL_Z; 1347 break; 1348 1349 case ir_binop_logic_xor: 1350 inst = emit(BRW_OPCODE_XOR, reg_null_d, op[0], op[1]); 1351 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1352 break; 1353 1354 case ir_binop_logic_or: 1355 inst = emit(BRW_OPCODE_OR, reg_null_d, op[0], op[1]); 1356 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1357 break; 1358 1359 case ir_binop_logic_and: 1360 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], op[1]); 1361 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1362 break; 1363 1364 case ir_unop_f2b: 1365 if (intel->gen >= 6) { 1366 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0.0f)); 1367 } else { 1368 inst = emit(BRW_OPCODE_MOV, reg_null_f, op[0]); 1369 } 1370 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1371 break; 1372 1373 case ir_unop_i2b: 1374 if (intel->gen >= 6) { 1375 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0)); 1376 } else { 1377 inst = emit(BRW_OPCODE_MOV, reg_null_d, op[0]); 1378 } 1379 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1380 break; 1381 1382 case ir_binop_greater: 1383 case ir_binop_gequal: 1384 case ir_binop_less: 1385 case ir_binop_lequal: 1386 case ir_binop_equal: 1387 case ir_binop_all_equal: 1388 case ir_binop_nequal: 1389 case ir_binop_any_nequal: 1390 inst = emit(BRW_OPCODE_CMP, reg_null_cmp, op[0], op[1]); 1391 inst->conditional_mod = 1392 brw_conditional_for_comparison(expr->operation); 1393 break; 1394 1395 default: 1396 assert(!"not reached"); 1397 fail("bad cond code\n"); 1398 break; 1399 } 1400 return; 1401 } 1402 1403 this->result = reg_undef; 1404 ir->accept(this); 1405 1406 if (intel->gen >= 6) { 1407 fs_inst *inst = emit(BRW_OPCODE_AND, reg_null_d, this->result, fs_reg(1)); 1408 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1409 } else { 1410 fs_inst *inst = emit(BRW_OPCODE_MOV, reg_null_d, this->result); 1411 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1412 } 1413} 1414 1415/** 1416 * Emit a gen6 IF statement with the comparison folded into the IF 1417 * instruction. 1418 */ 1419void 1420fs_visitor::emit_if_gen6(ir_if *ir) 1421{ 1422 ir_expression *expr = ir->condition->as_expression(); 1423 1424 if (expr) { 1425 fs_reg op[2]; 1426 fs_inst *inst; 1427 fs_reg temp; 1428 1429 assert(expr->get_num_operands() <= 2); 1430 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1431 assert(expr->operands[i]->type->is_scalar()); 1432 1433 this->result = reg_undef; 1434 expr->operands[i]->accept(this); 1435 op[i] = this->result; 1436 } 1437 1438 switch (expr->operation) { 1439 case ir_unop_logic_not: 1440 inst = emit(BRW_OPCODE_IF, temp, op[0], fs_reg(0)); 1441 inst->conditional_mod = BRW_CONDITIONAL_Z; 1442 return; 1443 1444 case ir_binop_logic_xor: 1445 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1446 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1447 return; 1448 1449 case ir_binop_logic_or: 1450 temp = fs_reg(this, glsl_type::bool_type); 1451 emit(BRW_OPCODE_OR, temp, op[0], op[1]); 1452 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1453 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1454 return; 1455 1456 case ir_binop_logic_and: 1457 temp = fs_reg(this, glsl_type::bool_type); 1458 emit(BRW_OPCODE_AND, temp, op[0], op[1]); 1459 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1460 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1461 return; 1462 1463 case ir_unop_f2b: 1464 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0)); 1465 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1466 return; 1467 1468 case ir_unop_i2b: 1469 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1470 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1471 return; 1472 1473 case ir_binop_greater: 1474 case ir_binop_gequal: 1475 case ir_binop_less: 1476 case ir_binop_lequal: 1477 case ir_binop_equal: 1478 case ir_binop_all_equal: 1479 case ir_binop_nequal: 1480 case ir_binop_any_nequal: 1481 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1482 inst->conditional_mod = 1483 brw_conditional_for_comparison(expr->operation); 1484 return; 1485 default: 1486 assert(!"not reached"); 1487 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1488 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1489 fail("bad condition\n"); 1490 return; 1491 } 1492 return; 1493 } 1494 1495 this->result = reg_undef; 1496 ir->condition->accept(this); 1497 1498 fs_inst *inst = emit(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0)); 1499 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1500} 1501 1502void 1503fs_visitor::visit(ir_if *ir) 1504{ 1505 fs_inst *inst; 1506 1507 if (intel->gen != 6 && c->dispatch_width == 16) { 1508 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1509 } 1510 1511 /* Don't point the annotation at the if statement, because then it plus 1512 * the then and else blocks get printed. 1513 */ 1514 this->base_ir = ir->condition; 1515 1516 if (intel->gen == 6) { 1517 emit_if_gen6(ir); 1518 } else { 1519 emit_bool_to_cond_code(ir->condition); 1520 1521 inst = emit(BRW_OPCODE_IF); 1522 inst->predicated = true; 1523 } 1524 1525 foreach_list(node, &ir->then_instructions) { 1526 ir_instruction *ir = (ir_instruction *)node; 1527 this->base_ir = ir; 1528 this->result = reg_undef; 1529 ir->accept(this); 1530 } 1531 1532 if (!ir->else_instructions.is_empty()) { 1533 emit(BRW_OPCODE_ELSE); 1534 1535 foreach_list(node, &ir->else_instructions) { 1536 ir_instruction *ir = (ir_instruction *)node; 1537 this->base_ir = ir; 1538 this->result = reg_undef; 1539 ir->accept(this); 1540 } 1541 } 1542 1543 emit(BRW_OPCODE_ENDIF); 1544} 1545 1546void 1547fs_visitor::visit(ir_loop *ir) 1548{ 1549 fs_reg counter = reg_undef; 1550 1551 if (c->dispatch_width == 16) { 1552 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1553 } 1554 1555 if (ir->counter) { 1556 this->base_ir = ir->counter; 1557 ir->counter->accept(this); 1558 counter = *(variable_storage(ir->counter)); 1559 1560 if (ir->from) { 1561 this->result = counter; 1562 1563 this->base_ir = ir->from; 1564 this->result = counter; 1565 ir->from->accept(this); 1566 1567 if (!this->result.equals(&counter)) 1568 emit(BRW_OPCODE_MOV, counter, this->result); 1569 } 1570 } 1571 1572 emit(BRW_OPCODE_DO); 1573 1574 if (ir->to) { 1575 this->base_ir = ir->to; 1576 this->result = reg_undef; 1577 ir->to->accept(this); 1578 1579 fs_inst *inst = emit(BRW_OPCODE_CMP, reg_null_cmp, counter, this->result); 1580 inst->conditional_mod = brw_conditional_for_comparison(ir->cmp); 1581 1582 inst = emit(BRW_OPCODE_BREAK); 1583 inst->predicated = true; 1584 } 1585 1586 foreach_list(node, &ir->body_instructions) { 1587 ir_instruction *ir = (ir_instruction *)node; 1588 1589 this->base_ir = ir; 1590 this->result = reg_undef; 1591 ir->accept(this); 1592 } 1593 1594 if (ir->increment) { 1595 this->base_ir = ir->increment; 1596 this->result = reg_undef; 1597 ir->increment->accept(this); 1598 emit(BRW_OPCODE_ADD, counter, counter, this->result); 1599 } 1600 1601 emit(BRW_OPCODE_WHILE); 1602} 1603 1604void 1605fs_visitor::visit(ir_loop_jump *ir) 1606{ 1607 switch (ir->mode) { 1608 case ir_loop_jump::jump_break: 1609 emit(BRW_OPCODE_BREAK); 1610 break; 1611 case ir_loop_jump::jump_continue: 1612 emit(BRW_OPCODE_CONTINUE); 1613 break; 1614 } 1615} 1616 1617void 1618fs_visitor::visit(ir_call *ir) 1619{ 1620 assert(!"FINISHME"); 1621} 1622 1623void 1624fs_visitor::visit(ir_return *ir) 1625{ 1626 assert(!"FINISHME"); 1627} 1628 1629void 1630fs_visitor::visit(ir_function *ir) 1631{ 1632 /* Ignore function bodies other than main() -- we shouldn't see calls to 1633 * them since they should all be inlined before we get to ir_to_mesa. 1634 */ 1635 if (strcmp(ir->name, "main") == 0) { 1636 const ir_function_signature *sig; 1637 exec_list empty; 1638 1639 sig = ir->matching_signature(&empty); 1640 1641 assert(sig); 1642 1643 foreach_list(node, &sig->body) { 1644 ir_instruction *ir = (ir_instruction *)node; 1645 this->base_ir = ir; 1646 this->result = reg_undef; 1647 ir->accept(this); 1648 } 1649 } 1650} 1651 1652void 1653fs_visitor::visit(ir_function_signature *ir) 1654{ 1655 assert(!"not reached"); 1656 (void)ir; 1657} 1658 1659fs_inst * 1660fs_visitor::emit(fs_inst inst) 1661{ 1662 fs_inst *list_inst = new(mem_ctx) fs_inst; 1663 *list_inst = inst; 1664 1665 if (force_uncompressed_stack > 0) 1666 list_inst->force_uncompressed = true; 1667 else if (force_sechalf_stack > 0) 1668 list_inst->force_sechalf = true; 1669 1670 list_inst->annotation = this->current_annotation; 1671 list_inst->ir = this->base_ir; 1672 1673 this->instructions.push_tail(list_inst); 1674 1675 return list_inst; 1676} 1677 1678/** Emits a dummy fragment shader consisting of magenta for bringup purposes. */ 1679void 1680fs_visitor::emit_dummy_fs() 1681{ 1682 /* Everyone's favorite color. */ 1683 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2), fs_reg(1.0f)); 1684 emit(BRW_OPCODE_MOV, fs_reg(MRF, 3), fs_reg(0.0f)); 1685 emit(BRW_OPCODE_MOV, fs_reg(MRF, 4), fs_reg(1.0f)); 1686 emit(BRW_OPCODE_MOV, fs_reg(MRF, 5), fs_reg(0.0f)); 1687 1688 fs_inst *write; 1689 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0)); 1690 write->base_mrf = 2; 1691} 1692 1693/* The register location here is relative to the start of the URB 1694 * data. It will get adjusted to be a real location before 1695 * generate_code() time. 1696 */ 1697struct brw_reg 1698fs_visitor::interp_reg(int location, int channel) 1699{ 1700 int regnr = urb_setup[location] * 2 + channel / 2; 1701 int stride = (channel & 1) * 4; 1702 1703 assert(urb_setup[location] != -1); 1704 1705 return brw_vec1_grf(regnr, stride); 1706} 1707 1708/** Emits the interpolation for the varying inputs. */ 1709void 1710fs_visitor::emit_interpolation_setup_gen4() 1711{ 1712 this->current_annotation = "compute pixel centers"; 1713 this->pixel_x = fs_reg(this, glsl_type::uint_type); 1714 this->pixel_y = fs_reg(this, glsl_type::uint_type); 1715 this->pixel_x.type = BRW_REGISTER_TYPE_UW; 1716 this->pixel_y.type = BRW_REGISTER_TYPE_UW; 1717 1718 emit(FS_OPCODE_PIXEL_X, this->pixel_x); 1719 emit(FS_OPCODE_PIXEL_Y, this->pixel_y); 1720 1721 this->current_annotation = "compute pixel deltas from v0"; 1722 if (brw->has_pln) { 1723 this->delta_x = fs_reg(this, glsl_type::vec2_type); 1724 this->delta_y = this->delta_x; 1725 this->delta_y.reg_offset++; 1726 } else { 1727 this->delta_x = fs_reg(this, glsl_type::float_type); 1728 this->delta_y = fs_reg(this, glsl_type::float_type); 1729 } 1730 emit(BRW_OPCODE_ADD, this->delta_x, 1731 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))); 1732 emit(BRW_OPCODE_ADD, this->delta_y, 1733 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))); 1734 1735 this->current_annotation = "compute pos.w and 1/pos.w"; 1736 /* Compute wpos.w. It's always in our setup, since it's needed to 1737 * interpolate the other attributes. 1738 */ 1739 this->wpos_w = fs_reg(this, glsl_type::float_type); 1740 emit(FS_OPCODE_LINTERP, wpos_w, this->delta_x, this->delta_y, 1741 interp_reg(FRAG_ATTRIB_WPOS, 3)); 1742 /* Compute the pixel 1/W value from wpos.w. */ 1743 this->pixel_w = fs_reg(this, glsl_type::float_type); 1744 emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w); 1745 this->current_annotation = NULL; 1746} 1747 1748/** Emits the interpolation for the varying inputs. */ 1749void 1750fs_visitor::emit_interpolation_setup_gen6() 1751{ 1752 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); 1753 1754 /* If the pixel centers end up used, the setup is the same as for gen4. */ 1755 this->current_annotation = "compute pixel centers"; 1756 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type); 1757 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type); 1758 int_pixel_x.type = BRW_REGISTER_TYPE_UW; 1759 int_pixel_y.type = BRW_REGISTER_TYPE_UW; 1760 emit(BRW_OPCODE_ADD, 1761 int_pixel_x, 1762 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), 1763 fs_reg(brw_imm_v(0x10101010))); 1764 emit(BRW_OPCODE_ADD, 1765 int_pixel_y, 1766 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), 1767 fs_reg(brw_imm_v(0x11001100))); 1768 1769 /* As of gen6, we can no longer mix float and int sources. We have 1770 * to turn the integer pixel centers into floats for their actual 1771 * use. 1772 */ 1773 this->pixel_x = fs_reg(this, glsl_type::float_type); 1774 this->pixel_y = fs_reg(this, glsl_type::float_type); 1775 emit(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x); 1776 emit(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y); 1777 1778 this->current_annotation = "compute pos.w"; 1779 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0)); 1780 this->wpos_w = fs_reg(this, glsl_type::float_type); 1781 emit_math(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w); 1782 1783 this->delta_x = fs_reg(brw_vec8_grf(2, 0)); 1784 this->delta_y = fs_reg(brw_vec8_grf(3, 0)); 1785 1786 this->current_annotation = NULL; 1787} 1788 1789void 1790fs_visitor::emit_color_write(int index, int first_color_mrf, fs_reg color) 1791{ 1792 int reg_width = c->dispatch_width / 8; 1793 fs_inst *inst; 1794 1795 if (c->dispatch_width == 8 || intel->gen == 6) { 1796 /* SIMD8 write looks like: 1797 * m + 0: r0 1798 * m + 1: r1 1799 * m + 2: g0 1800 * m + 3: g1 1801 * 1802 * gen6 SIMD16 DP write looks like: 1803 * m + 0: r0 1804 * m + 1: r1 1805 * m + 2: g0 1806 * m + 3: g1 1807 * m + 4: b0 1808 * m + 5: b1 1809 * m + 6: a0 1810 * m + 7: a1 1811 */ 1812 inst = emit(BRW_OPCODE_MOV, 1813 fs_reg(MRF, first_color_mrf + index * reg_width), 1814 color); 1815 inst->saturate = c->key.clamp_fragment_color; 1816 } else { 1817 /* pre-gen6 SIMD16 single source DP write looks like: 1818 * m + 0: r0 1819 * m + 1: g0 1820 * m + 2: b0 1821 * m + 3: a0 1822 * m + 4: r1 1823 * m + 5: g1 1824 * m + 6: b1 1825 * m + 7: a1 1826 */ 1827 if (brw->has_compr4) { 1828 /* By setting the high bit of the MRF register number, we 1829 * indicate that we want COMPR4 mode - instead of doing the 1830 * usual destination + 1 for the second half we get 1831 * destination + 4. 1832 */ 1833 inst = emit(BRW_OPCODE_MOV, 1834 fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index), 1835 color); 1836 inst->saturate = c->key.clamp_fragment_color; 1837 } else { 1838 push_force_uncompressed(); 1839 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index), 1840 color); 1841 inst->saturate = c->key.clamp_fragment_color; 1842 pop_force_uncompressed(); 1843 1844 push_force_sechalf(); 1845 color.sechalf = true; 1846 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index + 4), 1847 color); 1848 inst->saturate = c->key.clamp_fragment_color; 1849 pop_force_sechalf(); 1850 color.sechalf = false; 1851 } 1852 } 1853} 1854 1855void 1856fs_visitor::emit_fb_writes() 1857{ 1858 this->current_annotation = "FB write header"; 1859 GLboolean header_present = GL_TRUE; 1860 int base_mrf = 2; 1861 int nr = base_mrf; 1862 int reg_width = c->dispatch_width / 8; 1863 1864 if (intel->gen >= 6 && 1865 !this->kill_emitted && 1866 c->key.nr_color_regions == 1) { 1867 header_present = false; 1868 } 1869 1870 if (header_present) { 1871 /* m2, m3 header */ 1872 nr += 2; 1873 } 1874 1875 if (c->aa_dest_stencil_reg) { 1876 push_force_uncompressed(); 1877 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++), 1878 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))); 1879 pop_force_uncompressed(); 1880 } 1881 1882 /* Reserve space for color. It'll be filled in per MRT below. */ 1883 int color_mrf = nr; 1884 nr += 4 * reg_width; 1885 1886 if (c->source_depth_to_render_target) { 1887 if (intel->gen == 6 && c->dispatch_width == 16) { 1888 /* For outputting oDepth on gen6, SIMD8 writes have to be 1889 * used. This would require 8-wide moves of each half to 1890 * message regs, kind of like pre-gen5 SIMD16 FB writes. 1891 * Just bail on doing so for now. 1892 */ 1893 fail("Missing support for simd16 depth writes on gen6\n"); 1894 } 1895 1896 if (c->computes_depth) { 1897 /* Hand over gl_FragDepth. */ 1898 assert(this->frag_depth); 1899 fs_reg depth = *(variable_storage(this->frag_depth)); 1900 1901 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), depth); 1902 } else { 1903 /* Pass through the payload depth. */ 1904 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1905 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))); 1906 } 1907 nr += reg_width; 1908 } 1909 1910 if (c->dest_depth_reg) { 1911 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1912 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))); 1913 nr += reg_width; 1914 } 1915 1916 fs_reg color = reg_undef; 1917 if (this->frag_color) 1918 color = *(variable_storage(this->frag_color)); 1919 else if (this->frag_data) { 1920 color = *(variable_storage(this->frag_data)); 1921 color.type = BRW_REGISTER_TYPE_F; 1922 } 1923 1924 for (int target = 0; target < c->key.nr_color_regions; target++) { 1925 this->current_annotation = ralloc_asprintf(this->mem_ctx, 1926 "FB write target %d", 1927 target); 1928 if (this->frag_color || this->frag_data) { 1929 for (int i = 0; i < 4; i++) { 1930 emit_color_write(i, color_mrf, color); 1931 color.reg_offset++; 1932 } 1933 } 1934 1935 if (this->frag_color) 1936 color.reg_offset -= 4; 1937 1938 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1939 inst->target = target; 1940 inst->base_mrf = base_mrf; 1941 inst->mlen = nr - base_mrf; 1942 if (target == c->key.nr_color_regions - 1) 1943 inst->eot = true; 1944 inst->header_present = header_present; 1945 } 1946 1947 if (c->key.nr_color_regions == 0) { 1948 if (c->key.alpha_test && (this->frag_color || this->frag_data)) { 1949 /* If the alpha test is enabled but there's no color buffer, 1950 * we still need to send alpha out the pipeline to our null 1951 * renderbuffer. 1952 */ 1953 color.reg_offset += 3; 1954 emit_color_write(3, color_mrf, color); 1955 } 1956 1957 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1958 inst->base_mrf = base_mrf; 1959 inst->mlen = nr - base_mrf; 1960 inst->eot = true; 1961 inst->header_present = header_present; 1962 } 1963 1964 this->current_annotation = NULL; 1965} 1966