brw_fs_visitor.cpp revision 4fdd289805d14d4f7a234f88cd375be1b3b96764
1/* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24/** @file brw_fs_visitor.cpp 25 * 26 * This file supports generating the FS LIR from the GLSL IR. The LIR 27 * makes it easier to do backend-specific optimizations than doing so 28 * in the GLSL IR or in the native code. 29 */ 30extern "C" { 31 32#include <sys/types.h> 33 34#include "main/macros.h" 35#include "main/shaderobj.h" 36#include "main/uniforms.h" 37#include "program/prog_parameter.h" 38#include "program/prog_print.h" 39#include "program/prog_optimize.h" 40#include "program/register_allocate.h" 41#include "program/sampler.h" 42#include "program/hash_table.h" 43#include "brw_context.h" 44#include "brw_eu.h" 45#include "brw_wm.h" 46} 47#include "brw_shader.h" 48#include "brw_fs.h" 49#include "../glsl/glsl_types.h" 50#include "../glsl/ir_optimization.h" 51#include "../glsl/ir_print_visitor.h" 52 53void 54fs_visitor::visit(ir_variable *ir) 55{ 56 fs_reg *reg = NULL; 57 58 if (variable_storage(ir)) 59 return; 60 61 if (strcmp(ir->name, "gl_FragColor") == 0) { 62 this->frag_color = ir; 63 } else if (strcmp(ir->name, "gl_FragData") == 0) { 64 this->frag_data = ir; 65 } else if (strcmp(ir->name, "gl_FragDepth") == 0) { 66 this->frag_depth = ir; 67 } 68 69 if (ir->mode == ir_var_in) { 70 if (!strcmp(ir->name, "gl_FragCoord")) { 71 reg = emit_fragcoord_interpolation(ir); 72 } else if (!strcmp(ir->name, "gl_FrontFacing")) { 73 reg = emit_frontfacing_interpolation(ir); 74 } else { 75 reg = emit_general_interpolation(ir); 76 } 77 assert(reg); 78 hash_table_insert(this->variable_ht, reg, ir); 79 return; 80 } 81 82 if (ir->mode == ir_var_uniform) { 83 int param_index = c->prog_data.nr_params; 84 85 if (c->dispatch_width == 16) { 86 if (!variable_storage(ir)) { 87 fail("Failed to find uniform '%s' in 16-wide\n", ir->name); 88 } 89 return; 90 } 91 92 if (!strncmp(ir->name, "gl_", 3)) { 93 setup_builtin_uniform_values(ir); 94 } else { 95 setup_uniform_values(ir->location, ir->type); 96 } 97 98 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index); 99 reg->type = brw_type_for_base_type(ir->type); 100 } 101 102 if (!reg) 103 reg = new(this->mem_ctx) fs_reg(this, ir->type); 104 105 hash_table_insert(this->variable_ht, reg, ir); 106} 107 108void 109fs_visitor::visit(ir_dereference_variable *ir) 110{ 111 fs_reg *reg = variable_storage(ir->var); 112 this->result = *reg; 113} 114 115void 116fs_visitor::visit(ir_dereference_record *ir) 117{ 118 const glsl_type *struct_type = ir->record->type; 119 120 ir->record->accept(this); 121 122 unsigned int offset = 0; 123 for (unsigned int i = 0; i < struct_type->length; i++) { 124 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0) 125 break; 126 offset += type_size(struct_type->fields.structure[i].type); 127 } 128 this->result.reg_offset += offset; 129 this->result.type = brw_type_for_base_type(ir->type); 130} 131 132void 133fs_visitor::visit(ir_dereference_array *ir) 134{ 135 ir_constant *index; 136 int element_size; 137 138 ir->array->accept(this); 139 index = ir->array_index->as_constant(); 140 141 element_size = type_size(ir->type); 142 this->result.type = brw_type_for_base_type(ir->type); 143 144 if (index) { 145 assert(this->result.file == UNIFORM || 146 (this->result.file == GRF && 147 this->result.reg != 0)); 148 this->result.reg_offset += index->value.i[0] * element_size; 149 } else { 150 assert(!"FINISHME: non-constant array element"); 151 } 152} 153 154/* Instruction selection: Produce a MOV.sat instead of 155 * MIN(MAX(val, 0), 1) when possible. 156 */ 157bool 158fs_visitor::try_emit_saturate(ir_expression *ir) 159{ 160 ir_rvalue *sat_val = ir->as_rvalue_to_saturate(); 161 162 if (!sat_val) 163 return false; 164 165 this->result = reg_undef; 166 sat_val->accept(this); 167 fs_reg src = this->result; 168 169 this->result = fs_reg(this, ir->type); 170 fs_inst *inst = emit(BRW_OPCODE_MOV, this->result, src); 171 inst->saturate = true; 172 173 return true; 174} 175 176void 177fs_visitor::visit(ir_expression *ir) 178{ 179 unsigned int operand; 180 fs_reg op[2], temp; 181 fs_inst *inst; 182 183 assert(ir->get_num_operands() <= 2); 184 185 if (try_emit_saturate(ir)) 186 return; 187 188 /* This is where our caller would like us to put the result, if possible. */ 189 fs_reg saved_result_storage = this->result; 190 191 for (operand = 0; operand < ir->get_num_operands(); operand++) { 192 this->result = reg_undef; 193 ir->operands[operand]->accept(this); 194 if (this->result.file == BAD_FILE) { 195 ir_print_visitor v; 196 fail("Failed to get tree for expression operand:\n"); 197 ir->operands[operand]->accept(&v); 198 } 199 op[operand] = this->result; 200 201 /* Matrix expression operands should have been broken down to vector 202 * operations already. 203 */ 204 assert(!ir->operands[operand]->type->is_matrix()); 205 /* And then those vector operands should have been broken down to scalar. 206 */ 207 assert(!ir->operands[operand]->type->is_vector()); 208 } 209 210 /* Inherit storage from our parent if possible, and otherwise we 211 * alloc a temporary. 212 */ 213 if (saved_result_storage.file == BAD_FILE) { 214 this->result = fs_reg(this, ir->type); 215 } else { 216 this->result = saved_result_storage; 217 } 218 219 switch (ir->operation) { 220 case ir_unop_logic_not: 221 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is 222 * ones complement of the whole register, not just bit 0. 223 */ 224 emit(BRW_OPCODE_XOR, this->result, op[0], fs_reg(1)); 225 break; 226 case ir_unop_neg: 227 op[0].negate = !op[0].negate; 228 this->result = op[0]; 229 break; 230 case ir_unop_abs: 231 op[0].abs = true; 232 op[0].negate = false; 233 this->result = op[0]; 234 break; 235 case ir_unop_sign: 236 temp = fs_reg(this, ir->type); 237 238 /* Unalias the destination. (imagine a = sign(a)) */ 239 this->result = fs_reg(this, ir->type); 240 241 emit(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)); 242 243 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 244 inst->conditional_mod = BRW_CONDITIONAL_G; 245 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)); 246 inst->predicated = true; 247 248 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 249 inst->conditional_mod = BRW_CONDITIONAL_L; 250 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)); 251 inst->predicated = true; 252 253 break; 254 case ir_unop_rcp: 255 emit_math(FS_OPCODE_RCP, this->result, op[0]); 256 break; 257 258 case ir_unop_exp2: 259 emit_math(FS_OPCODE_EXP2, this->result, op[0]); 260 break; 261 case ir_unop_log2: 262 emit_math(FS_OPCODE_LOG2, this->result, op[0]); 263 break; 264 case ir_unop_exp: 265 case ir_unop_log: 266 assert(!"not reached: should be handled by ir_explog_to_explog2"); 267 break; 268 case ir_unop_sin: 269 case ir_unop_sin_reduced: 270 emit_math(FS_OPCODE_SIN, this->result, op[0]); 271 break; 272 case ir_unop_cos: 273 case ir_unop_cos_reduced: 274 emit_math(FS_OPCODE_COS, this->result, op[0]); 275 break; 276 277 case ir_unop_dFdx: 278 emit(FS_OPCODE_DDX, this->result, op[0]); 279 break; 280 case ir_unop_dFdy: 281 emit(FS_OPCODE_DDY, this->result, op[0]); 282 break; 283 284 case ir_binop_add: 285 emit(BRW_OPCODE_ADD, this->result, op[0], op[1]); 286 break; 287 case ir_binop_sub: 288 assert(!"not reached: should be handled by ir_sub_to_add_neg"); 289 break; 290 291 case ir_binop_mul: 292 emit(BRW_OPCODE_MUL, this->result, op[0], op[1]); 293 break; 294 case ir_binop_div: 295 assert(!"not reached: should be handled by ir_div_to_mul_rcp"); 296 break; 297 case ir_binop_mod: 298 assert(!"ir_binop_mod should have been converted to b * fract(a/b)"); 299 break; 300 301 case ir_binop_less: 302 case ir_binop_greater: 303 case ir_binop_lequal: 304 case ir_binop_gequal: 305 case ir_binop_equal: 306 case ir_binop_all_equal: 307 case ir_binop_nequal: 308 case ir_binop_any_nequal: 309 temp = this->result; 310 /* original gen4 does implicit conversion before comparison. */ 311 if (intel->gen < 5) 312 temp.type = op[0].type; 313 314 inst = emit(BRW_OPCODE_CMP, temp, op[0], op[1]); 315 inst->conditional_mod = brw_conditional_for_comparison(ir->operation); 316 emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)); 317 break; 318 319 case ir_binop_logic_xor: 320 emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 321 break; 322 323 case ir_binop_logic_or: 324 emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 325 break; 326 327 case ir_binop_logic_and: 328 emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 329 break; 330 331 case ir_binop_dot: 332 case ir_unop_any: 333 assert(!"not reached: should be handled by brw_fs_channel_expressions"); 334 break; 335 336 case ir_unop_noise: 337 assert(!"not reached: should be handled by lower_noise"); 338 break; 339 340 case ir_quadop_vector: 341 assert(!"not reached: should be handled by lower_quadop_vector"); 342 break; 343 344 case ir_unop_sqrt: 345 emit_math(FS_OPCODE_SQRT, this->result, op[0]); 346 break; 347 348 case ir_unop_rsq: 349 emit_math(FS_OPCODE_RSQ, this->result, op[0]); 350 break; 351 352 case ir_unop_i2u: 353 op[0].type = BRW_REGISTER_TYPE_UD; 354 this->result = op[0]; 355 break; 356 case ir_unop_u2i: 357 op[0].type = BRW_REGISTER_TYPE_D; 358 this->result = op[0]; 359 break; 360 case ir_unop_i2f: 361 case ir_unop_b2f: 362 case ir_unop_b2i: 363 case ir_unop_f2i: 364 emit(BRW_OPCODE_MOV, this->result, op[0]); 365 break; 366 case ir_unop_f2b: 367 case ir_unop_i2b: 368 temp = this->result; 369 /* original gen4 does implicit conversion before comparison. */ 370 if (intel->gen < 5) 371 temp.type = op[0].type; 372 373 inst = emit(BRW_OPCODE_CMP, temp, op[0], fs_reg(0.0f)); 374 inst->conditional_mod = BRW_CONDITIONAL_NZ; 375 inst = emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(1)); 376 break; 377 378 case ir_unop_trunc: 379 emit(BRW_OPCODE_RNDZ, this->result, op[0]); 380 break; 381 case ir_unop_ceil: 382 op[0].negate = !op[0].negate; 383 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 384 this->result.negate = true; 385 break; 386 case ir_unop_floor: 387 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 388 break; 389 case ir_unop_fract: 390 inst = emit(BRW_OPCODE_FRC, this->result, op[0]); 391 break; 392 case ir_unop_round_even: 393 emit(BRW_OPCODE_RNDE, this->result, op[0]); 394 break; 395 396 case ir_binop_min: 397 if (intel->gen >= 6) { 398 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 399 inst->conditional_mod = BRW_CONDITIONAL_L; 400 } else { 401 /* Unalias the destination */ 402 this->result = fs_reg(this, ir->type); 403 404 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 405 inst->conditional_mod = BRW_CONDITIONAL_L; 406 407 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 408 inst->predicated = true; 409 } 410 break; 411 case ir_binop_max: 412 if (intel->gen >= 6) { 413 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 414 inst->conditional_mod = BRW_CONDITIONAL_GE; 415 } else { 416 /* Unalias the destination */ 417 this->result = fs_reg(this, ir->type); 418 419 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 420 inst->conditional_mod = BRW_CONDITIONAL_G; 421 422 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 423 inst->predicated = true; 424 } 425 break; 426 427 case ir_binop_pow: 428 emit_math(FS_OPCODE_POW, this->result, op[0], op[1]); 429 break; 430 431 case ir_unop_bit_not: 432 inst = emit(BRW_OPCODE_NOT, this->result, op[0]); 433 break; 434 case ir_binop_bit_and: 435 inst = emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 436 break; 437 case ir_binop_bit_xor: 438 inst = emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 439 break; 440 case ir_binop_bit_or: 441 inst = emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 442 break; 443 444 case ir_unop_u2f: 445 case ir_binop_lshift: 446 case ir_binop_rshift: 447 assert(!"GLSL 1.30 features unsupported"); 448 break; 449 } 450} 451 452void 453fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r, 454 const glsl_type *type, bool predicated) 455{ 456 switch (type->base_type) { 457 case GLSL_TYPE_FLOAT: 458 case GLSL_TYPE_UINT: 459 case GLSL_TYPE_INT: 460 case GLSL_TYPE_BOOL: 461 for (unsigned int i = 0; i < type->components(); i++) { 462 l.type = brw_type_for_base_type(type); 463 r.type = brw_type_for_base_type(type); 464 465 if (predicated || !l.equals(&r)) { 466 fs_inst *inst = emit(BRW_OPCODE_MOV, l, r); 467 inst->predicated = predicated; 468 } 469 470 l.reg_offset++; 471 r.reg_offset++; 472 } 473 break; 474 case GLSL_TYPE_ARRAY: 475 for (unsigned int i = 0; i < type->length; i++) { 476 emit_assignment_writes(l, r, type->fields.array, predicated); 477 } 478 break; 479 480 case GLSL_TYPE_STRUCT: 481 for (unsigned int i = 0; i < type->length; i++) { 482 emit_assignment_writes(l, r, type->fields.structure[i].type, 483 predicated); 484 } 485 break; 486 487 case GLSL_TYPE_SAMPLER: 488 break; 489 490 default: 491 assert(!"not reached"); 492 break; 493 } 494} 495 496void 497fs_visitor::visit(ir_assignment *ir) 498{ 499 struct fs_reg l, r; 500 fs_inst *inst; 501 502 /* FINISHME: arrays on the lhs */ 503 this->result = reg_undef; 504 ir->lhs->accept(this); 505 l = this->result; 506 507 /* If we're doing a direct assignment, an RHS expression could 508 * drop its result right into our destination. Otherwise, tell it 509 * not to. 510 */ 511 if (ir->condition || 512 !(ir->lhs->type->is_scalar() || 513 (ir->lhs->type->is_vector() && 514 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1))) { 515 this->result = reg_undef; 516 } 517 518 ir->rhs->accept(this); 519 r = this->result; 520 521 assert(l.file != BAD_FILE); 522 assert(r.file != BAD_FILE); 523 524 if (ir->condition) { 525 emit_bool_to_cond_code(ir->condition); 526 } 527 528 if (ir->lhs->type->is_scalar() || 529 ir->lhs->type->is_vector()) { 530 for (int i = 0; i < ir->lhs->type->vector_elements; i++) { 531 if (ir->write_mask & (1 << i)) { 532 if (ir->condition) { 533 inst = emit(BRW_OPCODE_MOV, l, r); 534 inst->predicated = true; 535 } else if (!l.equals(&r)) { 536 inst = emit(BRW_OPCODE_MOV, l, r); 537 } 538 539 r.reg_offset++; 540 } 541 l.reg_offset++; 542 } 543 } else { 544 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL); 545 } 546} 547 548fs_inst * 549fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate, 550 int sampler) 551{ 552 int mlen; 553 int base_mrf = 1; 554 bool simd16 = false; 555 fs_reg orig_dst; 556 557 /* g0 header. */ 558 mlen = 1; 559 560 if (ir->shadow_comparitor && ir->op != ir_txd) { 561 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 562 fs_inst *inst = emit(BRW_OPCODE_MOV, 563 fs_reg(MRF, base_mrf + mlen + i), coordinate); 564 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 565 inst->saturate = true; 566 567 coordinate.reg_offset++; 568 } 569 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 570 mlen += 3; 571 572 if (ir->op == ir_tex) { 573 /* There's no plain shadow compare message, so we use shadow 574 * compare with a bias of 0.0. 575 */ 576 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)); 577 mlen++; 578 } else if (ir->op == ir_txb) { 579 this->result = reg_undef; 580 ir->lod_info.bias->accept(this); 581 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 582 mlen++; 583 } else { 584 assert(ir->op == ir_txl); 585 this->result = reg_undef; 586 ir->lod_info.lod->accept(this); 587 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 588 mlen++; 589 } 590 591 this->result = reg_undef; 592 ir->shadow_comparitor->accept(this); 593 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 594 mlen++; 595 } else if (ir->op == ir_tex) { 596 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 597 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), 598 coordinate); 599 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 600 inst->saturate = true; 601 coordinate.reg_offset++; 602 } 603 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 604 mlen += 3; 605 } else if (ir->op == ir_txd) { 606 this->result = reg_undef; 607 ir->lod_info.grad.dPdx->accept(this); 608 fs_reg dPdx = this->result; 609 610 this->result = reg_undef; 611 ir->lod_info.grad.dPdy->accept(this); 612 fs_reg dPdy = this->result; 613 614 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 615 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); 616 coordinate.reg_offset++; 617 } 618 /* the slots for u and v are always present, but r is optional */ 619 mlen += MAX2(ir->coordinate->type->vector_elements, 2); 620 621 /* P = u, v, r 622 * dPdx = dudx, dvdx, drdx 623 * dPdy = dudy, dvdy, drdy 624 * 625 * 1-arg: Does not exist. 626 * 627 * 2-arg: dudx dvdx dudy dvdy 628 * dPdx.x dPdx.y dPdy.x dPdy.y 629 * m4 m5 m6 m7 630 * 631 * 3-arg: dudx dvdx drdx dudy dvdy drdy 632 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z 633 * m5 m6 m7 m8 m9 m10 634 */ 635 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 636 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 637 dPdx.reg_offset++; 638 } 639 mlen += MAX2(ir->lod_info.grad.dPdx->type->vector_elements, 2); 640 641 for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) { 642 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 643 dPdy.reg_offset++; 644 } 645 mlen += MAX2(ir->lod_info.grad.dPdy->type->vector_elements, 2); 646 } else { 647 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod 648 * instructions. We'll need to do SIMD16 here. 649 */ 650 assert(ir->op == ir_txb || ir->op == ir_txl); 651 652 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 653 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, 654 base_mrf + mlen + i * 2), 655 coordinate); 656 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 657 inst->saturate = true; 658 coordinate.reg_offset++; 659 } 660 661 /* lod/bias appears after u/v/r. */ 662 mlen += 6; 663 664 if (ir->op == ir_txb) { 665 this->result = reg_undef; 666 ir->lod_info.bias->accept(this); 667 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 668 mlen++; 669 } else { 670 this->result = reg_undef; 671 ir->lod_info.lod->accept(this); 672 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 673 mlen++; 674 } 675 676 /* The unused upper half. */ 677 mlen++; 678 679 /* Now, since we're doing simd16, the return is 2 interleaved 680 * vec4s where the odd-indexed ones are junk. We'll need to move 681 * this weirdness around to the expected layout. 682 */ 683 simd16 = true; 684 orig_dst = dst; 685 dst = fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type, 686 2)); 687 dst.type = BRW_REGISTER_TYPE_F; 688 } 689 690 fs_inst *inst = NULL; 691 switch (ir->op) { 692 case ir_tex: 693 inst = emit(FS_OPCODE_TEX, dst); 694 break; 695 case ir_txb: 696 inst = emit(FS_OPCODE_TXB, dst); 697 break; 698 case ir_txl: 699 inst = emit(FS_OPCODE_TXL, dst); 700 break; 701 case ir_txd: 702 inst = emit(FS_OPCODE_TXD, dst); 703 break; 704 case ir_txf: 705 assert(!"GLSL 1.30 features unsupported"); 706 break; 707 } 708 inst->base_mrf = base_mrf; 709 inst->mlen = mlen; 710 inst->header_present = true; 711 712 if (simd16) { 713 for (int i = 0; i < 4; i++) { 714 emit(BRW_OPCODE_MOV, orig_dst, dst); 715 orig_dst.reg_offset++; 716 dst.reg_offset += 2; 717 } 718 } 719 720 return inst; 721} 722 723/* gen5's sampler has slots for u, v, r, array index, then optional 724 * parameters like shadow comparitor or LOD bias. If optional 725 * parameters aren't present, those base slots are optional and don't 726 * need to be included in the message. 727 * 728 * We don't fill in the unnecessary slots regardless, which may look 729 * surprising in the disassembly. 730 */ 731fs_inst * 732fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate, 733 int sampler) 734{ 735 int mlen = 0; 736 int base_mrf = 2; 737 int reg_width = c->dispatch_width / 8; 738 bool header_present = false; 739 740 if (ir->offset) { 741 /* The offsets set up by the ir_texture visitor are in the 742 * m1 header, so we can't go headerless. 743 */ 744 header_present = true; 745 mlen++; 746 base_mrf--; 747 } 748 749 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 750 fs_inst *inst = emit(BRW_OPCODE_MOV, 751 fs_reg(MRF, base_mrf + mlen + i * reg_width), 752 coordinate); 753 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 754 inst->saturate = true; 755 coordinate.reg_offset++; 756 } 757 mlen += ir->coordinate->type->vector_elements * reg_width; 758 759 if (ir->shadow_comparitor && ir->op != ir_txd) { 760 mlen = MAX2(mlen, header_present + 4 * reg_width); 761 762 this->result = reg_undef; 763 ir->shadow_comparitor->accept(this); 764 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 765 mlen += reg_width; 766 } 767 768 fs_inst *inst = NULL; 769 switch (ir->op) { 770 case ir_tex: 771 inst = emit(FS_OPCODE_TEX, dst); 772 break; 773 case ir_txb: 774 this->result = reg_undef; 775 ir->lod_info.bias->accept(this); 776 mlen = MAX2(mlen, header_present + 4 * reg_width); 777 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 778 mlen += reg_width; 779 780 inst = emit(FS_OPCODE_TXB, dst); 781 782 break; 783 case ir_txl: 784 this->result = reg_undef; 785 ir->lod_info.lod->accept(this); 786 mlen = MAX2(mlen, header_present + 4 * reg_width); 787 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 788 mlen += reg_width; 789 790 inst = emit(FS_OPCODE_TXL, dst); 791 break; 792 case ir_txd: { 793 this->result = reg_undef; 794 ir->lod_info.grad.dPdx->accept(this); 795 fs_reg dPdx = this->result; 796 797 this->result = reg_undef; 798 ir->lod_info.grad.dPdy->accept(this); 799 fs_reg dPdy = this->result; 800 801 mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */ 802 803 /** 804 * P = u, v, r 805 * dPdx = dudx, dvdx, drdx 806 * dPdy = dudy, dvdy, drdy 807 * 808 * Load up these values: 809 * - dudx dudy dvdx dvdy drdx drdy 810 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z 811 */ 812 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 813 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 814 dPdx.reg_offset++; 815 mlen += reg_width; 816 817 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 818 dPdy.reg_offset++; 819 mlen += reg_width; 820 } 821 822 inst = emit(FS_OPCODE_TXD, dst); 823 break; 824 } 825 case ir_txf: 826 assert(!"GLSL 1.30 features unsupported"); 827 break; 828 } 829 inst->base_mrf = base_mrf; 830 inst->mlen = mlen; 831 inst->header_present = header_present; 832 833 if (mlen > 11) { 834 fail("Message length >11 disallowed by hardware\n"); 835 } 836 837 return inst; 838} 839 840fs_inst * 841fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate, 842 int sampler) 843{ 844 int mlen = 0; 845 int base_mrf = 2; 846 int reg_width = c->dispatch_width / 8; 847 bool header_present = false; 848 849 if (ir->offset) { 850 /* The offsets set up by the ir_texture visitor are in the 851 * m1 header, so we can't go headerless. 852 */ 853 header_present = true; 854 mlen++; 855 base_mrf--; 856 } 857 858 if (ir->shadow_comparitor && ir->op != ir_txd) { 859 this->result = reg_undef; 860 ir->shadow_comparitor->accept(this); 861 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 862 mlen += reg_width; 863 } 864 865 /* Set up the LOD info */ 866 switch (ir->op) { 867 case ir_tex: 868 break; 869 case ir_txb: 870 this->result = reg_undef; 871 ir->lod_info.bias->accept(this); 872 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 873 mlen += reg_width; 874 break; 875 case ir_txl: 876 this->result = reg_undef; 877 ir->lod_info.lod->accept(this); 878 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 879 mlen += reg_width; 880 break; 881 case ir_txd: { 882 if (c->dispatch_width == 16) 883 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode."); 884 885 this->result = reg_undef; 886 ir->lod_info.grad.dPdx->accept(this); 887 fs_reg dPdx = this->result; 888 889 this->result = reg_undef; 890 ir->lod_info.grad.dPdy->accept(this); 891 fs_reg dPdy = this->result; 892 893 /* Load dPdx and the coordinate together: 894 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z 895 */ 896 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 897 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 898 coordinate); 899 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 900 inst->saturate = true; 901 coordinate.reg_offset++; 902 mlen += reg_width; 903 904 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 905 dPdx.reg_offset++; 906 mlen += reg_width; 907 908 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 909 dPdy.reg_offset++; 910 mlen += reg_width; 911 } 912 break; 913 } 914 case ir_txf: 915 assert(!"GLSL 1.30 features unsupported"); 916 break; 917 } 918 919 /* Set up the coordinate (except for TXD where it was done earlier) */ 920 if (ir->op != ir_txd) { 921 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 922 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 923 coordinate); 924 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 925 inst->saturate = true; 926 coordinate.reg_offset++; 927 mlen += reg_width; 928 } 929 } 930 931 /* Generate the SEND */ 932 fs_inst *inst = NULL; 933 switch (ir->op) { 934 case ir_tex: inst = emit(FS_OPCODE_TEX, dst); break; 935 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break; 936 case ir_txl: inst = emit(FS_OPCODE_TXL, dst); break; 937 case ir_txd: inst = emit(FS_OPCODE_TXD, dst); break; 938 case ir_txf: assert(!"TXF unsupported."); 939 } 940 inst->base_mrf = base_mrf; 941 inst->mlen = mlen; 942 inst->header_present = header_present; 943 944 if (mlen > 11) { 945 fail("Message length >11 disallowed by hardware\n"); 946 } 947 948 return inst; 949} 950 951void 952fs_visitor::visit(ir_texture *ir) 953{ 954 fs_inst *inst = NULL; 955 956 int sampler = _mesa_get_sampler_uniform_value(ir->sampler, prog, &fp->Base); 957 sampler = fp->Base.SamplerUnits[sampler]; 958 959 /* Our hardware doesn't have a sample_d_c message, so shadow compares 960 * for textureGrad/TXD need to be emulated with instructions. 961 */ 962 bool hw_compare_supported = ir->op != ir_txd; 963 if (ir->shadow_comparitor && !hw_compare_supported) { 964 assert(c->key.compare_funcs[sampler] != GL_NONE); 965 /* No need to even sample for GL_ALWAYS or GL_NEVER...bail early */ 966 if (c->key.compare_funcs[sampler] == GL_ALWAYS) 967 return swizzle_result(ir, fs_reg(1.0f), sampler); 968 else if (c->key.compare_funcs[sampler] == GL_NEVER) 969 return swizzle_result(ir, fs_reg(0.0f), sampler); 970 } 971 972 this->result = reg_undef; 973 ir->coordinate->accept(this); 974 fs_reg coordinate = this->result; 975 976 if (ir->offset != NULL) { 977 ir_constant *offset = ir->offset->as_constant(); 978 assert(offset != NULL); 979 980 signed char offsets[3]; 981 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) 982 offsets[i] = (signed char) offset->value.i[i]; 983 984 /* Combine all three offsets into a single unsigned dword: 985 * 986 * bits 11:8 - U Offset (X component) 987 * bits 7:4 - V Offset (Y component) 988 * bits 3:0 - R Offset (Z component) 989 */ 990 unsigned offset_bits = 0; 991 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) { 992 const unsigned shift = 4 * (2 - i); 993 offset_bits |= (offsets[i] << shift) & (0xF << shift); 994 } 995 996 /* Explicitly set up the message header by copying g0 to msg reg m1. */ 997 emit(BRW_OPCODE_MOV, fs_reg(MRF, 1, BRW_REGISTER_TYPE_UD), 998 fs_reg(GRF, 0, BRW_REGISTER_TYPE_UD)); 999 1000 /* Then set the offset bits in DWord 2 of the message header. */ 1001 emit(BRW_OPCODE_MOV, 1002 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 1, 2), 1003 BRW_REGISTER_TYPE_UD)), 1004 fs_reg(brw_imm_uw(offset_bits))); 1005 } 1006 1007 /* Should be lowered by do_lower_texture_projection */ 1008 assert(!ir->projector); 1009 1010 /* The 965 requires the EU to do the normalization of GL rectangle 1011 * texture coordinates. We use the program parameter state 1012 * tracking to get the scaling factor. 1013 */ 1014 if (ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) { 1015 struct gl_program_parameter_list *params = c->fp->program.Base.Parameters; 1016 int tokens[STATE_LENGTH] = { 1017 STATE_INTERNAL, 1018 STATE_TEXRECT_SCALE, 1019 sampler, 1020 0, 1021 0 1022 }; 1023 1024 if (c->dispatch_width == 16) { 1025 fail("rectangle scale uniform setup not supported on 16-wide\n"); 1026 this->result = fs_reg(this, ir->type); 1027 return; 1028 } 1029 1030 c->prog_data.param_convert[c->prog_data.nr_params] = 1031 PARAM_NO_CONVERT; 1032 c->prog_data.param_convert[c->prog_data.nr_params + 1] = 1033 PARAM_NO_CONVERT; 1034 1035 fs_reg scale_x = fs_reg(UNIFORM, c->prog_data.nr_params); 1036 fs_reg scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1); 1037 GLuint index = _mesa_add_state_reference(params, 1038 (gl_state_index *)tokens); 1039 1040 this->param_index[c->prog_data.nr_params] = index; 1041 this->param_offset[c->prog_data.nr_params] = 0; 1042 c->prog_data.nr_params++; 1043 this->param_index[c->prog_data.nr_params] = index; 1044 this->param_offset[c->prog_data.nr_params] = 1; 1045 c->prog_data.nr_params++; 1046 1047 fs_reg dst = fs_reg(this, ir->coordinate->type); 1048 fs_reg src = coordinate; 1049 coordinate = dst; 1050 1051 emit(BRW_OPCODE_MUL, dst, src, scale_x); 1052 dst.reg_offset++; 1053 src.reg_offset++; 1054 emit(BRW_OPCODE_MUL, dst, src, scale_y); 1055 } 1056 1057 /* Writemasking doesn't eliminate channels on SIMD8 texture 1058 * samples, so don't worry about them. 1059 */ 1060 fs_reg dst = fs_reg(this, glsl_type::vec4_type); 1061 1062 if (intel->gen >= 7) { 1063 inst = emit_texture_gen7(ir, dst, coordinate, sampler); 1064 } else if (intel->gen >= 5) { 1065 inst = emit_texture_gen5(ir, dst, coordinate, sampler); 1066 } else { 1067 inst = emit_texture_gen4(ir, dst, coordinate, sampler); 1068 } 1069 1070 /* If there's an offset, we already set up m1. To avoid the implied move, 1071 * use the null register. Otherwise, we want an implied move from g0. 1072 */ 1073 if (ir->offset != NULL || !inst->header_present) 1074 inst->src[0] = reg_undef; 1075 else 1076 inst->src[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW)); 1077 1078 inst->sampler = sampler; 1079 1080 if (ir->shadow_comparitor) { 1081 if (hw_compare_supported) { 1082 inst->shadow_compare = true; 1083 } else { 1084 this->result = reg_undef; 1085 ir->shadow_comparitor->accept(this); 1086 fs_reg ref = this->result; 1087 1088 fs_reg value = dst; 1089 dst = fs_reg(this, glsl_type::vec4_type); 1090 1091 /* FINISHME: This needs to be done pre-filtering. */ 1092 1093 uint32_t conditional = 0; 1094 switch (c->key.compare_funcs[sampler]) { 1095 /* GL_ALWAYS and GL_NEVER were handled at the top of the function */ 1096 case GL_LESS: conditional = BRW_CONDITIONAL_L; break; 1097 case GL_GREATER: conditional = BRW_CONDITIONAL_G; break; 1098 case GL_LEQUAL: conditional = BRW_CONDITIONAL_LE; break; 1099 case GL_GEQUAL: conditional = BRW_CONDITIONAL_GE; break; 1100 case GL_EQUAL: conditional = BRW_CONDITIONAL_EQ; break; 1101 case GL_NOTEQUAL: conditional = BRW_CONDITIONAL_NEQ; break; 1102 default: assert(!"Should not get here: bad shadow compare function"); 1103 } 1104 1105 /* Use conditional moves to load 0 or 1 as the result */ 1106 this->current_annotation = "manual shadow comparison"; 1107 for (int i = 0; i < 4; i++) { 1108 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(0.0f)); 1109 1110 inst = emit(BRW_OPCODE_CMP, reg_null_f, ref, value); 1111 inst->conditional_mod = conditional; 1112 1113 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(1.0f)); 1114 inst->predicated = true; 1115 1116 dst.reg_offset++; 1117 value.reg_offset++; 1118 } 1119 dst.reg_offset = 0; 1120 } 1121 } 1122 1123 swizzle_result(ir, dst, sampler); 1124} 1125 1126/** 1127 * Swizzle the result of a texture result. This is necessary for 1128 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons. 1129 */ 1130void 1131fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler) 1132{ 1133 this->result = orig_val; 1134 1135 if (ir->type == glsl_type::float_type) { 1136 /* Ignore DEPTH_TEXTURE_MODE swizzling. */ 1137 assert(ir->sampler->type->sampler_shadow); 1138 } else if (c->key.tex_swizzles[sampler] != SWIZZLE_NOOP) { 1139 fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type); 1140 1141 for (int i = 0; i < 4; i++) { 1142 int swiz = GET_SWZ(c->key.tex_swizzles[sampler], i); 1143 fs_reg l = swizzled_result; 1144 l.reg_offset += i; 1145 1146 if (swiz == SWIZZLE_ZERO) { 1147 emit(BRW_OPCODE_MOV, l, fs_reg(0.0f)); 1148 } else if (swiz == SWIZZLE_ONE) { 1149 emit(BRW_OPCODE_MOV, l, fs_reg(1.0f)); 1150 } else { 1151 fs_reg r = orig_val; 1152 r.reg_offset += GET_SWZ(c->key.tex_swizzles[sampler], i); 1153 emit(BRW_OPCODE_MOV, l, r); 1154 } 1155 } 1156 this->result = swizzled_result; 1157 } 1158} 1159 1160void 1161fs_visitor::visit(ir_swizzle *ir) 1162{ 1163 this->result = reg_undef; 1164 ir->val->accept(this); 1165 fs_reg val = this->result; 1166 1167 if (ir->type->vector_elements == 1) { 1168 this->result.reg_offset += ir->mask.x; 1169 return; 1170 } 1171 1172 fs_reg result = fs_reg(this, ir->type); 1173 this->result = result; 1174 1175 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 1176 fs_reg channel = val; 1177 int swiz = 0; 1178 1179 switch (i) { 1180 case 0: 1181 swiz = ir->mask.x; 1182 break; 1183 case 1: 1184 swiz = ir->mask.y; 1185 break; 1186 case 2: 1187 swiz = ir->mask.z; 1188 break; 1189 case 3: 1190 swiz = ir->mask.w; 1191 break; 1192 } 1193 1194 channel.reg_offset += swiz; 1195 emit(BRW_OPCODE_MOV, result, channel); 1196 result.reg_offset++; 1197 } 1198} 1199 1200void 1201fs_visitor::visit(ir_discard *ir) 1202{ 1203 assert(ir->condition == NULL); /* FINISHME */ 1204 1205 emit(FS_OPCODE_DISCARD); 1206 kill_emitted = true; 1207} 1208 1209void 1210fs_visitor::visit(ir_constant *ir) 1211{ 1212 /* Set this->result to reg at the bottom of the function because some code 1213 * paths will cause this visitor to be applied to other fields. This will 1214 * cause the value stored in this->result to be modified. 1215 * 1216 * Make reg constant so that it doesn't get accidentally modified along the 1217 * way. Yes, I actually had this problem. :( 1218 */ 1219 const fs_reg reg(this, ir->type); 1220 fs_reg dst_reg = reg; 1221 1222 if (ir->type->is_array()) { 1223 const unsigned size = type_size(ir->type->fields.array); 1224 1225 for (unsigned i = 0; i < ir->type->length; i++) { 1226 this->result = reg_undef; 1227 ir->array_elements[i]->accept(this); 1228 fs_reg src_reg = this->result; 1229 1230 dst_reg.type = src_reg.type; 1231 for (unsigned j = 0; j < size; j++) { 1232 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1233 src_reg.reg_offset++; 1234 dst_reg.reg_offset++; 1235 } 1236 } 1237 } else if (ir->type->is_record()) { 1238 foreach_list(node, &ir->components) { 1239 ir_instruction *const field = (ir_instruction *) node; 1240 const unsigned size = type_size(field->type); 1241 1242 this->result = reg_undef; 1243 field->accept(this); 1244 fs_reg src_reg = this->result; 1245 1246 dst_reg.type = src_reg.type; 1247 for (unsigned j = 0; j < size; j++) { 1248 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1249 src_reg.reg_offset++; 1250 dst_reg.reg_offset++; 1251 } 1252 } 1253 } else { 1254 const unsigned size = type_size(ir->type); 1255 1256 for (unsigned i = 0; i < size; i++) { 1257 switch (ir->type->base_type) { 1258 case GLSL_TYPE_FLOAT: 1259 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i])); 1260 break; 1261 case GLSL_TYPE_UINT: 1262 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i])); 1263 break; 1264 case GLSL_TYPE_INT: 1265 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.i[i])); 1266 break; 1267 case GLSL_TYPE_BOOL: 1268 emit(BRW_OPCODE_MOV, dst_reg, fs_reg((int)ir->value.b[i])); 1269 break; 1270 default: 1271 assert(!"Non-float/uint/int/bool constant"); 1272 } 1273 dst_reg.reg_offset++; 1274 } 1275 } 1276 1277 this->result = reg; 1278} 1279 1280void 1281fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir) 1282{ 1283 ir_expression *expr = ir->as_expression(); 1284 1285 if (expr) { 1286 fs_reg op[2]; 1287 fs_inst *inst; 1288 1289 assert(expr->get_num_operands() <= 2); 1290 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1291 assert(expr->operands[i]->type->is_scalar()); 1292 1293 this->result = reg_undef; 1294 expr->operands[i]->accept(this); 1295 op[i] = this->result; 1296 } 1297 1298 switch (expr->operation) { 1299 case ir_unop_logic_not: 1300 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1)); 1301 inst->conditional_mod = BRW_CONDITIONAL_Z; 1302 break; 1303 1304 case ir_binop_logic_xor: 1305 inst = emit(BRW_OPCODE_XOR, reg_null_d, op[0], op[1]); 1306 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1307 break; 1308 1309 case ir_binop_logic_or: 1310 inst = emit(BRW_OPCODE_OR, reg_null_d, op[0], op[1]); 1311 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1312 break; 1313 1314 case ir_binop_logic_and: 1315 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], op[1]); 1316 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1317 break; 1318 1319 case ir_unop_f2b: 1320 if (intel->gen >= 6) { 1321 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0.0f)); 1322 } else { 1323 inst = emit(BRW_OPCODE_MOV, reg_null_f, op[0]); 1324 } 1325 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1326 break; 1327 1328 case ir_unop_i2b: 1329 if (intel->gen >= 6) { 1330 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0)); 1331 } else { 1332 inst = emit(BRW_OPCODE_MOV, reg_null_d, op[0]); 1333 } 1334 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1335 break; 1336 1337 case ir_binop_greater: 1338 case ir_binop_gequal: 1339 case ir_binop_less: 1340 case ir_binop_lequal: 1341 case ir_binop_equal: 1342 case ir_binop_all_equal: 1343 case ir_binop_nequal: 1344 case ir_binop_any_nequal: 1345 inst = emit(BRW_OPCODE_CMP, reg_null_cmp, op[0], op[1]); 1346 inst->conditional_mod = 1347 brw_conditional_for_comparison(expr->operation); 1348 break; 1349 1350 default: 1351 assert(!"not reached"); 1352 fail("bad cond code\n"); 1353 break; 1354 } 1355 return; 1356 } 1357 1358 this->result = reg_undef; 1359 ir->accept(this); 1360 1361 if (intel->gen >= 6) { 1362 fs_inst *inst = emit(BRW_OPCODE_AND, reg_null_d, this->result, fs_reg(1)); 1363 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1364 } else { 1365 fs_inst *inst = emit(BRW_OPCODE_MOV, reg_null_d, this->result); 1366 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1367 } 1368} 1369 1370/** 1371 * Emit a gen6 IF statement with the comparison folded into the IF 1372 * instruction. 1373 */ 1374void 1375fs_visitor::emit_if_gen6(ir_if *ir) 1376{ 1377 ir_expression *expr = ir->condition->as_expression(); 1378 1379 if (expr) { 1380 fs_reg op[2]; 1381 fs_inst *inst; 1382 fs_reg temp; 1383 1384 assert(expr->get_num_operands() <= 2); 1385 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1386 assert(expr->operands[i]->type->is_scalar()); 1387 1388 this->result = reg_undef; 1389 expr->operands[i]->accept(this); 1390 op[i] = this->result; 1391 } 1392 1393 switch (expr->operation) { 1394 case ir_unop_logic_not: 1395 inst = emit(BRW_OPCODE_IF, temp, op[0], fs_reg(0)); 1396 inst->conditional_mod = BRW_CONDITIONAL_Z; 1397 return; 1398 1399 case ir_binop_logic_xor: 1400 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1401 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1402 return; 1403 1404 case ir_binop_logic_or: 1405 temp = fs_reg(this, glsl_type::bool_type); 1406 emit(BRW_OPCODE_OR, temp, op[0], op[1]); 1407 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1408 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1409 return; 1410 1411 case ir_binop_logic_and: 1412 temp = fs_reg(this, glsl_type::bool_type); 1413 emit(BRW_OPCODE_AND, temp, op[0], op[1]); 1414 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1415 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1416 return; 1417 1418 case ir_unop_f2b: 1419 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0)); 1420 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1421 return; 1422 1423 case ir_unop_i2b: 1424 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1425 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1426 return; 1427 1428 case ir_binop_greater: 1429 case ir_binop_gequal: 1430 case ir_binop_less: 1431 case ir_binop_lequal: 1432 case ir_binop_equal: 1433 case ir_binop_all_equal: 1434 case ir_binop_nequal: 1435 case ir_binop_any_nequal: 1436 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1437 inst->conditional_mod = 1438 brw_conditional_for_comparison(expr->operation); 1439 return; 1440 default: 1441 assert(!"not reached"); 1442 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1443 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1444 fail("bad condition\n"); 1445 return; 1446 } 1447 return; 1448 } 1449 1450 this->result = reg_undef; 1451 ir->condition->accept(this); 1452 1453 fs_inst *inst = emit(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0)); 1454 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1455} 1456 1457void 1458fs_visitor::visit(ir_if *ir) 1459{ 1460 fs_inst *inst; 1461 1462 if (intel->gen != 6 && c->dispatch_width == 16) { 1463 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1464 } 1465 1466 /* Don't point the annotation at the if statement, because then it plus 1467 * the then and else blocks get printed. 1468 */ 1469 this->base_ir = ir->condition; 1470 1471 if (intel->gen == 6) { 1472 emit_if_gen6(ir); 1473 } else { 1474 emit_bool_to_cond_code(ir->condition); 1475 1476 inst = emit(BRW_OPCODE_IF); 1477 inst->predicated = true; 1478 } 1479 1480 foreach_iter(exec_list_iterator, iter, ir->then_instructions) { 1481 ir_instruction *ir = (ir_instruction *)iter.get(); 1482 this->base_ir = ir; 1483 this->result = reg_undef; 1484 ir->accept(this); 1485 } 1486 1487 if (!ir->else_instructions.is_empty()) { 1488 emit(BRW_OPCODE_ELSE); 1489 1490 foreach_iter(exec_list_iterator, iter, ir->else_instructions) { 1491 ir_instruction *ir = (ir_instruction *)iter.get(); 1492 this->base_ir = ir; 1493 this->result = reg_undef; 1494 ir->accept(this); 1495 } 1496 } 1497 1498 emit(BRW_OPCODE_ENDIF); 1499} 1500 1501void 1502fs_visitor::visit(ir_loop *ir) 1503{ 1504 fs_reg counter = reg_undef; 1505 1506 if (c->dispatch_width == 16) { 1507 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1508 } 1509 1510 if (ir->counter) { 1511 this->base_ir = ir->counter; 1512 ir->counter->accept(this); 1513 counter = *(variable_storage(ir->counter)); 1514 1515 if (ir->from) { 1516 this->result = counter; 1517 1518 this->base_ir = ir->from; 1519 this->result = counter; 1520 ir->from->accept(this); 1521 1522 if (!this->result.equals(&counter)) 1523 emit(BRW_OPCODE_MOV, counter, this->result); 1524 } 1525 } 1526 1527 emit(BRW_OPCODE_DO); 1528 1529 if (ir->to) { 1530 this->base_ir = ir->to; 1531 this->result = reg_undef; 1532 ir->to->accept(this); 1533 1534 fs_inst *inst = emit(BRW_OPCODE_CMP, reg_null_cmp, counter, this->result); 1535 inst->conditional_mod = brw_conditional_for_comparison(ir->cmp); 1536 1537 inst = emit(BRW_OPCODE_BREAK); 1538 inst->predicated = true; 1539 } 1540 1541 foreach_iter(exec_list_iterator, iter, ir->body_instructions) { 1542 ir_instruction *ir = (ir_instruction *)iter.get(); 1543 1544 this->base_ir = ir; 1545 this->result = reg_undef; 1546 ir->accept(this); 1547 } 1548 1549 if (ir->increment) { 1550 this->base_ir = ir->increment; 1551 this->result = reg_undef; 1552 ir->increment->accept(this); 1553 emit(BRW_OPCODE_ADD, counter, counter, this->result); 1554 } 1555 1556 emit(BRW_OPCODE_WHILE); 1557} 1558 1559void 1560fs_visitor::visit(ir_loop_jump *ir) 1561{ 1562 switch (ir->mode) { 1563 case ir_loop_jump::jump_break: 1564 emit(BRW_OPCODE_BREAK); 1565 break; 1566 case ir_loop_jump::jump_continue: 1567 emit(BRW_OPCODE_CONTINUE); 1568 break; 1569 } 1570} 1571 1572void 1573fs_visitor::visit(ir_call *ir) 1574{ 1575 assert(!"FINISHME"); 1576} 1577 1578void 1579fs_visitor::visit(ir_return *ir) 1580{ 1581 assert(!"FINISHME"); 1582} 1583 1584void 1585fs_visitor::visit(ir_function *ir) 1586{ 1587 /* Ignore function bodies other than main() -- we shouldn't see calls to 1588 * them since they should all be inlined before we get to ir_to_mesa. 1589 */ 1590 if (strcmp(ir->name, "main") == 0) { 1591 const ir_function_signature *sig; 1592 exec_list empty; 1593 1594 sig = ir->matching_signature(&empty); 1595 1596 assert(sig); 1597 1598 foreach_iter(exec_list_iterator, iter, sig->body) { 1599 ir_instruction *ir = (ir_instruction *)iter.get(); 1600 this->base_ir = ir; 1601 this->result = reg_undef; 1602 ir->accept(this); 1603 } 1604 } 1605} 1606 1607void 1608fs_visitor::visit(ir_function_signature *ir) 1609{ 1610 assert(!"not reached"); 1611 (void)ir; 1612} 1613 1614fs_inst * 1615fs_visitor::emit(fs_inst inst) 1616{ 1617 fs_inst *list_inst = new(mem_ctx) fs_inst; 1618 *list_inst = inst; 1619 1620 if (force_uncompressed_stack > 0) 1621 list_inst->force_uncompressed = true; 1622 else if (force_sechalf_stack > 0) 1623 list_inst->force_sechalf = true; 1624 1625 list_inst->annotation = this->current_annotation; 1626 list_inst->ir = this->base_ir; 1627 1628 this->instructions.push_tail(list_inst); 1629 1630 return list_inst; 1631} 1632 1633/** Emits a dummy fragment shader consisting of magenta for bringup purposes. */ 1634void 1635fs_visitor::emit_dummy_fs() 1636{ 1637 /* Everyone's favorite color. */ 1638 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2), fs_reg(1.0f)); 1639 emit(BRW_OPCODE_MOV, fs_reg(MRF, 3), fs_reg(0.0f)); 1640 emit(BRW_OPCODE_MOV, fs_reg(MRF, 4), fs_reg(1.0f)); 1641 emit(BRW_OPCODE_MOV, fs_reg(MRF, 5), fs_reg(0.0f)); 1642 1643 fs_inst *write; 1644 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0)); 1645 write->base_mrf = 2; 1646} 1647 1648/* The register location here is relative to the start of the URB 1649 * data. It will get adjusted to be a real location before 1650 * generate_code() time. 1651 */ 1652struct brw_reg 1653fs_visitor::interp_reg(int location, int channel) 1654{ 1655 int regnr = urb_setup[location] * 2 + channel / 2; 1656 int stride = (channel & 1) * 4; 1657 1658 assert(urb_setup[location] != -1); 1659 1660 return brw_vec1_grf(regnr, stride); 1661} 1662 1663/** Emits the interpolation for the varying inputs. */ 1664void 1665fs_visitor::emit_interpolation_setup_gen4() 1666{ 1667 this->current_annotation = "compute pixel centers"; 1668 this->pixel_x = fs_reg(this, glsl_type::uint_type); 1669 this->pixel_y = fs_reg(this, glsl_type::uint_type); 1670 this->pixel_x.type = BRW_REGISTER_TYPE_UW; 1671 this->pixel_y.type = BRW_REGISTER_TYPE_UW; 1672 1673 emit(FS_OPCODE_PIXEL_X, this->pixel_x); 1674 emit(FS_OPCODE_PIXEL_Y, this->pixel_y); 1675 1676 this->current_annotation = "compute pixel deltas from v0"; 1677 if (brw->has_pln) { 1678 this->delta_x = fs_reg(this, glsl_type::vec2_type); 1679 this->delta_y = this->delta_x; 1680 this->delta_y.reg_offset++; 1681 } else { 1682 this->delta_x = fs_reg(this, glsl_type::float_type); 1683 this->delta_y = fs_reg(this, glsl_type::float_type); 1684 } 1685 emit(BRW_OPCODE_ADD, this->delta_x, 1686 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))); 1687 emit(BRW_OPCODE_ADD, this->delta_y, 1688 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))); 1689 1690 this->current_annotation = "compute pos.w and 1/pos.w"; 1691 /* Compute wpos.w. It's always in our setup, since it's needed to 1692 * interpolate the other attributes. 1693 */ 1694 this->wpos_w = fs_reg(this, glsl_type::float_type); 1695 emit(FS_OPCODE_LINTERP, wpos_w, this->delta_x, this->delta_y, 1696 interp_reg(FRAG_ATTRIB_WPOS, 3)); 1697 /* Compute the pixel 1/W value from wpos.w. */ 1698 this->pixel_w = fs_reg(this, glsl_type::float_type); 1699 emit_math(FS_OPCODE_RCP, this->pixel_w, wpos_w); 1700 this->current_annotation = NULL; 1701} 1702 1703/** Emits the interpolation for the varying inputs. */ 1704void 1705fs_visitor::emit_interpolation_setup_gen6() 1706{ 1707 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); 1708 1709 /* If the pixel centers end up used, the setup is the same as for gen4. */ 1710 this->current_annotation = "compute pixel centers"; 1711 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type); 1712 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type); 1713 int_pixel_x.type = BRW_REGISTER_TYPE_UW; 1714 int_pixel_y.type = BRW_REGISTER_TYPE_UW; 1715 emit(BRW_OPCODE_ADD, 1716 int_pixel_x, 1717 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), 1718 fs_reg(brw_imm_v(0x10101010))); 1719 emit(BRW_OPCODE_ADD, 1720 int_pixel_y, 1721 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), 1722 fs_reg(brw_imm_v(0x11001100))); 1723 1724 /* As of gen6, we can no longer mix float and int sources. We have 1725 * to turn the integer pixel centers into floats for their actual 1726 * use. 1727 */ 1728 this->pixel_x = fs_reg(this, glsl_type::float_type); 1729 this->pixel_y = fs_reg(this, glsl_type::float_type); 1730 emit(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x); 1731 emit(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y); 1732 1733 this->current_annotation = "compute pos.w"; 1734 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0)); 1735 this->wpos_w = fs_reg(this, glsl_type::float_type); 1736 emit_math(FS_OPCODE_RCP, this->wpos_w, this->pixel_w); 1737 1738 this->delta_x = fs_reg(brw_vec8_grf(2, 0)); 1739 this->delta_y = fs_reg(brw_vec8_grf(3, 0)); 1740 1741 this->current_annotation = NULL; 1742} 1743 1744void 1745fs_visitor::emit_color_write(int index, int first_color_mrf, fs_reg color) 1746{ 1747 int reg_width = c->dispatch_width / 8; 1748 fs_inst *inst; 1749 1750 if (c->dispatch_width == 8 || intel->gen == 6) { 1751 /* SIMD8 write looks like: 1752 * m + 0: r0 1753 * m + 1: r1 1754 * m + 2: g0 1755 * m + 3: g1 1756 * 1757 * gen6 SIMD16 DP write looks like: 1758 * m + 0: r0 1759 * m + 1: r1 1760 * m + 2: g0 1761 * m + 3: g1 1762 * m + 4: b0 1763 * m + 5: b1 1764 * m + 6: a0 1765 * m + 7: a1 1766 */ 1767 inst = emit(BRW_OPCODE_MOV, 1768 fs_reg(MRF, first_color_mrf + index * reg_width), 1769 color); 1770 inst->saturate = c->key.clamp_fragment_color; 1771 } else { 1772 /* pre-gen6 SIMD16 single source DP write looks like: 1773 * m + 0: r0 1774 * m + 1: g0 1775 * m + 2: b0 1776 * m + 3: a0 1777 * m + 4: r1 1778 * m + 5: g1 1779 * m + 6: b1 1780 * m + 7: a1 1781 */ 1782 if (brw->has_compr4) { 1783 /* By setting the high bit of the MRF register number, we 1784 * indicate that we want COMPR4 mode - instead of doing the 1785 * usual destination + 1 for the second half we get 1786 * destination + 4. 1787 */ 1788 inst = emit(BRW_OPCODE_MOV, 1789 fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index), 1790 color); 1791 inst->saturate = c->key.clamp_fragment_color; 1792 } else { 1793 push_force_uncompressed(); 1794 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index), 1795 color); 1796 inst->saturate = c->key.clamp_fragment_color; 1797 pop_force_uncompressed(); 1798 1799 push_force_sechalf(); 1800 color.sechalf = true; 1801 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index + 4), 1802 color); 1803 inst->saturate = c->key.clamp_fragment_color; 1804 pop_force_sechalf(); 1805 color.sechalf = false; 1806 } 1807 } 1808} 1809 1810void 1811fs_visitor::emit_fb_writes() 1812{ 1813 this->current_annotation = "FB write header"; 1814 GLboolean header_present = GL_TRUE; 1815 int base_mrf = 2; 1816 int nr = base_mrf; 1817 int reg_width = c->dispatch_width / 8; 1818 1819 if (intel->gen >= 6 && 1820 !this->kill_emitted && 1821 c->key.nr_color_regions == 1) { 1822 header_present = false; 1823 } 1824 1825 if (header_present) { 1826 /* m2, m3 header */ 1827 nr += 2; 1828 } 1829 1830 if (c->aa_dest_stencil_reg) { 1831 push_force_uncompressed(); 1832 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++), 1833 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))); 1834 pop_force_uncompressed(); 1835 } 1836 1837 /* Reserve space for color. It'll be filled in per MRT below. */ 1838 int color_mrf = nr; 1839 nr += 4 * reg_width; 1840 1841 if (c->source_depth_to_render_target) { 1842 if (intel->gen == 6 && c->dispatch_width == 16) { 1843 /* For outputting oDepth on gen6, SIMD8 writes have to be 1844 * used. This would require 8-wide moves of each half to 1845 * message regs, kind of like pre-gen5 SIMD16 FB writes. 1846 * Just bail on doing so for now. 1847 */ 1848 fail("Missing support for simd16 depth writes on gen6\n"); 1849 } 1850 1851 if (c->computes_depth) { 1852 /* Hand over gl_FragDepth. */ 1853 assert(this->frag_depth); 1854 fs_reg depth = *(variable_storage(this->frag_depth)); 1855 1856 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), depth); 1857 } else { 1858 /* Pass through the payload depth. */ 1859 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1860 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))); 1861 } 1862 nr += reg_width; 1863 } 1864 1865 if (c->dest_depth_reg) { 1866 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1867 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))); 1868 nr += reg_width; 1869 } 1870 1871 fs_reg color = reg_undef; 1872 if (this->frag_color) 1873 color = *(variable_storage(this->frag_color)); 1874 else if (this->frag_data) { 1875 color = *(variable_storage(this->frag_data)); 1876 color.type = BRW_REGISTER_TYPE_F; 1877 } 1878 1879 for (int target = 0; target < c->key.nr_color_regions; target++) { 1880 this->current_annotation = ralloc_asprintf(this->mem_ctx, 1881 "FB write target %d", 1882 target); 1883 if (this->frag_color || this->frag_data) { 1884 for (int i = 0; i < 4; i++) { 1885 emit_color_write(i, color_mrf, color); 1886 color.reg_offset++; 1887 } 1888 } 1889 1890 if (this->frag_color) 1891 color.reg_offset -= 4; 1892 1893 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1894 inst->target = target; 1895 inst->base_mrf = base_mrf; 1896 inst->mlen = nr - base_mrf; 1897 if (target == c->key.nr_color_regions - 1) 1898 inst->eot = true; 1899 inst->header_present = header_present; 1900 } 1901 1902 if (c->key.nr_color_regions == 0) { 1903 if (c->key.alpha_test && (this->frag_color || this->frag_data)) { 1904 /* If the alpha test is enabled but there's no color buffer, 1905 * we still need to send alpha out the pipeline to our null 1906 * renderbuffer. 1907 */ 1908 color.reg_offset += 3; 1909 emit_color_write(3, color_mrf, color); 1910 } 1911 1912 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1913 inst->base_mrf = base_mrf; 1914 inst->mlen = nr - base_mrf; 1915 inst->eot = true; 1916 inst->header_present = header_present; 1917 } 1918 1919 this->current_annotation = NULL; 1920} 1921