brw_fs_visitor.cpp revision 73b0a28ba8b3e2ab917d4c729f34ddbde52c9e88
1/* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24/** @file brw_fs_visitor.cpp 25 * 26 * This file supports generating the FS LIR from the GLSL IR. The LIR 27 * makes it easier to do backend-specific optimizations than doing so 28 * in the GLSL IR or in the native code. 29 */ 30extern "C" { 31 32#include <sys/types.h> 33 34#include "main/macros.h" 35#include "main/shaderobj.h" 36#include "main/uniforms.h" 37#include "program/prog_parameter.h" 38#include "program/prog_print.h" 39#include "program/prog_optimize.h" 40#include "program/register_allocate.h" 41#include "program/sampler.h" 42#include "program/hash_table.h" 43#include "brw_context.h" 44#include "brw_eu.h" 45#include "brw_wm.h" 46} 47#include "brw_shader.h" 48#include "brw_fs.h" 49#include "glsl/glsl_types.h" 50#include "glsl/ir_optimization.h" 51#include "glsl/ir_print_visitor.h" 52 53void 54fs_visitor::visit(ir_variable *ir) 55{ 56 fs_reg *reg = NULL; 57 58 if (variable_storage(ir)) 59 return; 60 61 if (strcmp(ir->name, "gl_FragColor") == 0) { 62 this->frag_color = ir; 63 } else if (strcmp(ir->name, "gl_FragData") == 0) { 64 this->frag_data = ir; 65 } else if (strcmp(ir->name, "gl_FragDepth") == 0) { 66 this->frag_depth = ir; 67 } 68 69 if (ir->mode == ir_var_in) { 70 if (!strcmp(ir->name, "gl_FragCoord")) { 71 reg = emit_fragcoord_interpolation(ir); 72 } else if (!strcmp(ir->name, "gl_FrontFacing")) { 73 reg = emit_frontfacing_interpolation(ir); 74 } else { 75 reg = emit_general_interpolation(ir); 76 } 77 assert(reg); 78 hash_table_insert(this->variable_ht, reg, ir); 79 return; 80 } 81 82 if (ir->mode == ir_var_uniform) { 83 int param_index = c->prog_data.nr_params; 84 85 if (c->dispatch_width == 16) { 86 if (!variable_storage(ir)) { 87 fail("Failed to find uniform '%s' in 16-wide\n", ir->name); 88 } 89 return; 90 } 91 92 if (!strncmp(ir->name, "gl_", 3)) { 93 setup_builtin_uniform_values(ir); 94 } else { 95 setup_uniform_values(ir->location, ir->type); 96 } 97 98 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index); 99 reg->type = brw_type_for_base_type(ir->type); 100 } 101 102 if (!reg) 103 reg = new(this->mem_ctx) fs_reg(this, ir->type); 104 105 hash_table_insert(this->variable_ht, reg, ir); 106} 107 108void 109fs_visitor::visit(ir_dereference_variable *ir) 110{ 111 fs_reg *reg = variable_storage(ir->var); 112 this->result = *reg; 113} 114 115void 116fs_visitor::visit(ir_dereference_record *ir) 117{ 118 const glsl_type *struct_type = ir->record->type; 119 120 ir->record->accept(this); 121 122 unsigned int offset = 0; 123 for (unsigned int i = 0; i < struct_type->length; i++) { 124 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0) 125 break; 126 offset += type_size(struct_type->fields.structure[i].type); 127 } 128 this->result.reg_offset += offset; 129 this->result.type = brw_type_for_base_type(ir->type); 130} 131 132void 133fs_visitor::visit(ir_dereference_array *ir) 134{ 135 ir_constant *index; 136 int element_size; 137 138 ir->array->accept(this); 139 index = ir->array_index->as_constant(); 140 141 element_size = type_size(ir->type); 142 this->result.type = brw_type_for_base_type(ir->type); 143 144 if (index) { 145 assert(this->result.file == UNIFORM || this->result.file == GRF); 146 this->result.reg_offset += index->value.i[0] * element_size; 147 } else { 148 assert(!"FINISHME: non-constant array element"); 149 } 150} 151 152/* Instruction selection: Produce a MOV.sat instead of 153 * MIN(MAX(val, 0), 1) when possible. 154 */ 155bool 156fs_visitor::try_emit_saturate(ir_expression *ir) 157{ 158 ir_rvalue *sat_val = ir->as_rvalue_to_saturate(); 159 160 if (!sat_val) 161 return false; 162 163 sat_val->accept(this); 164 fs_reg src = this->result; 165 166 this->result = fs_reg(this, ir->type); 167 fs_inst *inst = emit(BRW_OPCODE_MOV, this->result, src); 168 inst->saturate = true; 169 170 return true; 171} 172 173void 174fs_visitor::visit(ir_expression *ir) 175{ 176 unsigned int operand; 177 fs_reg op[2], temp; 178 fs_inst *inst; 179 180 assert(ir->get_num_operands() <= 2); 181 182 if (try_emit_saturate(ir)) 183 return; 184 185 for (operand = 0; operand < ir->get_num_operands(); operand++) { 186 ir->operands[operand]->accept(this); 187 if (this->result.file == BAD_FILE) { 188 ir_print_visitor v; 189 fail("Failed to get tree for expression operand:\n"); 190 ir->operands[operand]->accept(&v); 191 } 192 op[operand] = this->result; 193 194 /* Matrix expression operands should have been broken down to vector 195 * operations already. 196 */ 197 assert(!ir->operands[operand]->type->is_matrix()); 198 /* And then those vector operands should have been broken down to scalar. 199 */ 200 assert(!ir->operands[operand]->type->is_vector()); 201 } 202 203 /* Storage for our result. If our result goes into an assignment, it will 204 * just get copy-propagated out, so no worries. 205 */ 206 this->result = fs_reg(this, ir->type); 207 208 switch (ir->operation) { 209 case ir_unop_logic_not: 210 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is 211 * ones complement of the whole register, not just bit 0. 212 */ 213 emit(BRW_OPCODE_XOR, this->result, op[0], fs_reg(1)); 214 break; 215 case ir_unop_neg: 216 op[0].negate = !op[0].negate; 217 this->result = op[0]; 218 break; 219 case ir_unop_abs: 220 op[0].abs = true; 221 op[0].negate = false; 222 this->result = op[0]; 223 break; 224 case ir_unop_sign: 225 temp = fs_reg(this, ir->type); 226 227 emit(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)); 228 229 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 230 inst->conditional_mod = BRW_CONDITIONAL_G; 231 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)); 232 inst->predicated = true; 233 234 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 235 inst->conditional_mod = BRW_CONDITIONAL_L; 236 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)); 237 inst->predicated = true; 238 239 break; 240 case ir_unop_rcp: 241 emit_math(SHADER_OPCODE_RCP, this->result, op[0]); 242 break; 243 244 case ir_unop_exp2: 245 emit_math(SHADER_OPCODE_EXP2, this->result, op[0]); 246 break; 247 case ir_unop_log2: 248 emit_math(SHADER_OPCODE_LOG2, this->result, op[0]); 249 break; 250 case ir_unop_exp: 251 case ir_unop_log: 252 assert(!"not reached: should be handled by ir_explog_to_explog2"); 253 break; 254 case ir_unop_sin: 255 case ir_unop_sin_reduced: 256 emit_math(SHADER_OPCODE_SIN, this->result, op[0]); 257 break; 258 case ir_unop_cos: 259 case ir_unop_cos_reduced: 260 emit_math(SHADER_OPCODE_COS, this->result, op[0]); 261 break; 262 263 case ir_unop_dFdx: 264 emit(FS_OPCODE_DDX, this->result, op[0]); 265 break; 266 case ir_unop_dFdy: 267 emit(FS_OPCODE_DDY, this->result, op[0]); 268 break; 269 270 case ir_binop_add: 271 emit(BRW_OPCODE_ADD, this->result, op[0], op[1]); 272 break; 273 case ir_binop_sub: 274 assert(!"not reached: should be handled by ir_sub_to_add_neg"); 275 break; 276 277 case ir_binop_mul: 278 if (ir->type->is_integer()) { 279 /* For integer multiplication, the MUL uses the low 16 bits 280 * of one of the operands (src0 on gen6, src1 on gen7). The 281 * MACH accumulates in the contribution of the upper 16 bits 282 * of that operand. 283 * 284 * FINISHME: Emit just the MUL if we know an operand is small 285 * enough. 286 */ 287 struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_D); 288 289 emit(BRW_OPCODE_MUL, acc, op[0], op[1]); 290 emit(BRW_OPCODE_MACH, reg_null_d, op[0], op[1]); 291 emit(BRW_OPCODE_MOV, this->result, fs_reg(acc)); 292 } else { 293 emit(BRW_OPCODE_MUL, this->result, op[0], op[1]); 294 } 295 break; 296 case ir_binop_div: 297 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */ 298 assert(ir->type->is_integer()); 299 emit_math(SHADER_OPCODE_INT_QUOTIENT, this->result, op[0], op[1]); 300 break; 301 case ir_binop_mod: 302 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */ 303 assert(ir->type->is_integer()); 304 emit_math(SHADER_OPCODE_INT_REMAINDER, this->result, op[0], op[1]); 305 break; 306 307 case ir_binop_less: 308 case ir_binop_greater: 309 case ir_binop_lequal: 310 case ir_binop_gequal: 311 case ir_binop_equal: 312 case ir_binop_all_equal: 313 case ir_binop_nequal: 314 case ir_binop_any_nequal: 315 temp = this->result; 316 /* original gen4 does implicit conversion before comparison. */ 317 if (intel->gen < 5) 318 temp.type = op[0].type; 319 320 resolve_ud_negate(&op[0]); 321 resolve_ud_negate(&op[1]); 322 323 inst = emit(BRW_OPCODE_CMP, temp, op[0], op[1]); 324 inst->conditional_mod = brw_conditional_for_comparison(ir->operation); 325 emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)); 326 break; 327 328 case ir_binop_logic_xor: 329 emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 330 break; 331 332 case ir_binop_logic_or: 333 emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 334 break; 335 336 case ir_binop_logic_and: 337 emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 338 break; 339 340 case ir_binop_dot: 341 case ir_unop_any: 342 assert(!"not reached: should be handled by brw_fs_channel_expressions"); 343 break; 344 345 case ir_unop_noise: 346 assert(!"not reached: should be handled by lower_noise"); 347 break; 348 349 case ir_quadop_vector: 350 assert(!"not reached: should be handled by lower_quadop_vector"); 351 break; 352 353 case ir_unop_sqrt: 354 emit_math(SHADER_OPCODE_SQRT, this->result, op[0]); 355 break; 356 357 case ir_unop_rsq: 358 emit_math(SHADER_OPCODE_RSQ, this->result, op[0]); 359 break; 360 361 case ir_unop_i2u: 362 op[0].type = BRW_REGISTER_TYPE_UD; 363 this->result = op[0]; 364 break; 365 case ir_unop_u2i: 366 op[0].type = BRW_REGISTER_TYPE_D; 367 this->result = op[0]; 368 break; 369 case ir_unop_i2f: 370 case ir_unop_u2f: 371 case ir_unop_b2f: 372 case ir_unop_b2i: 373 case ir_unop_f2i: 374 emit(BRW_OPCODE_MOV, this->result, op[0]); 375 break; 376 case ir_unop_f2b: 377 case ir_unop_i2b: 378 temp = this->result; 379 /* original gen4 does implicit conversion before comparison. */ 380 if (intel->gen < 5) 381 temp.type = op[0].type; 382 383 resolve_ud_negate(&op[0]); 384 385 inst = emit(BRW_OPCODE_CMP, temp, op[0], fs_reg(0.0f)); 386 inst->conditional_mod = BRW_CONDITIONAL_NZ; 387 inst = emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(1)); 388 break; 389 390 case ir_unop_trunc: 391 emit(BRW_OPCODE_RNDZ, this->result, op[0]); 392 break; 393 case ir_unop_ceil: 394 op[0].negate = !op[0].negate; 395 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 396 this->result.negate = true; 397 break; 398 case ir_unop_floor: 399 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 400 break; 401 case ir_unop_fract: 402 inst = emit(BRW_OPCODE_FRC, this->result, op[0]); 403 break; 404 case ir_unop_round_even: 405 emit(BRW_OPCODE_RNDE, this->result, op[0]); 406 break; 407 408 case ir_binop_min: 409 resolve_ud_negate(&op[0]); 410 resolve_ud_negate(&op[1]); 411 412 if (intel->gen >= 6) { 413 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 414 inst->conditional_mod = BRW_CONDITIONAL_L; 415 } else { 416 /* Unalias the destination */ 417 this->result = fs_reg(this, ir->type); 418 419 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 420 inst->conditional_mod = BRW_CONDITIONAL_L; 421 422 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 423 inst->predicated = true; 424 } 425 break; 426 case ir_binop_max: 427 resolve_ud_negate(&op[0]); 428 resolve_ud_negate(&op[1]); 429 430 if (intel->gen >= 6) { 431 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 432 inst->conditional_mod = BRW_CONDITIONAL_GE; 433 } else { 434 /* Unalias the destination */ 435 this->result = fs_reg(this, ir->type); 436 437 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 438 inst->conditional_mod = BRW_CONDITIONAL_G; 439 440 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 441 inst->predicated = true; 442 } 443 break; 444 445 case ir_binop_pow: 446 emit_math(SHADER_OPCODE_POW, this->result, op[0], op[1]); 447 break; 448 449 case ir_unop_bit_not: 450 inst = emit(BRW_OPCODE_NOT, this->result, op[0]); 451 break; 452 case ir_binop_bit_and: 453 inst = emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 454 break; 455 case ir_binop_bit_xor: 456 inst = emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 457 break; 458 case ir_binop_bit_or: 459 inst = emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 460 break; 461 462 case ir_binop_lshift: 463 inst = emit(BRW_OPCODE_SHL, this->result, op[0], op[1]); 464 break; 465 466 case ir_binop_rshift: 467 if (ir->type->base_type == GLSL_TYPE_INT) 468 inst = emit(BRW_OPCODE_ASR, this->result, op[0], op[1]); 469 else 470 inst = emit(BRW_OPCODE_SHR, this->result, op[0], op[1]); 471 break; 472 } 473} 474 475void 476fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r, 477 const glsl_type *type, bool predicated) 478{ 479 switch (type->base_type) { 480 case GLSL_TYPE_FLOAT: 481 case GLSL_TYPE_UINT: 482 case GLSL_TYPE_INT: 483 case GLSL_TYPE_BOOL: 484 for (unsigned int i = 0; i < type->components(); i++) { 485 l.type = brw_type_for_base_type(type); 486 r.type = brw_type_for_base_type(type); 487 488 if (predicated || !l.equals(&r)) { 489 fs_inst *inst = emit(BRW_OPCODE_MOV, l, r); 490 inst->predicated = predicated; 491 } 492 493 l.reg_offset++; 494 r.reg_offset++; 495 } 496 break; 497 case GLSL_TYPE_ARRAY: 498 for (unsigned int i = 0; i < type->length; i++) { 499 emit_assignment_writes(l, r, type->fields.array, predicated); 500 } 501 break; 502 503 case GLSL_TYPE_STRUCT: 504 for (unsigned int i = 0; i < type->length; i++) { 505 emit_assignment_writes(l, r, type->fields.structure[i].type, 506 predicated); 507 } 508 break; 509 510 case GLSL_TYPE_SAMPLER: 511 break; 512 513 default: 514 assert(!"not reached"); 515 break; 516 } 517} 518 519/* If the RHS processing resulted in an instruction generating a 520 * temporary value, and it would be easy to rewrite the instruction to 521 * generate its result right into the LHS instead, do so. This ends 522 * up reliably removing instructions where it can be tricky to do so 523 * later without real UD chain information. 524 */ 525bool 526fs_visitor::try_rewrite_rhs_to_dst(ir_assignment *ir, 527 fs_reg dst, 528 fs_reg src, 529 fs_inst *pre_rhs_inst, 530 fs_inst *last_rhs_inst) 531{ 532 if (pre_rhs_inst == last_rhs_inst) 533 return false; /* No instructions generated to work with. */ 534 535 /* Only attempt if we're doing a direct assignment. */ 536 if (ir->condition || 537 !(ir->lhs->type->is_scalar() || 538 (ir->lhs->type->is_vector() && 539 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1))) 540 return false; 541 542 /* Make sure the last instruction generated our source reg. */ 543 if (last_rhs_inst->predicated || 544 last_rhs_inst->force_uncompressed || 545 last_rhs_inst->force_sechalf || 546 !src.equals(&last_rhs_inst->dst)) 547 return false; 548 549 /* Success! Rewrite the instruction. */ 550 last_rhs_inst->dst = dst; 551 552 return true; 553} 554 555void 556fs_visitor::visit(ir_assignment *ir) 557{ 558 fs_reg l, r; 559 fs_inst *inst; 560 561 /* FINISHME: arrays on the lhs */ 562 ir->lhs->accept(this); 563 l = this->result; 564 565 fs_inst *pre_rhs_inst = (fs_inst *) this->instructions.get_tail(); 566 567 ir->rhs->accept(this); 568 r = this->result; 569 570 fs_inst *last_rhs_inst = (fs_inst *) this->instructions.get_tail(); 571 572 assert(l.file != BAD_FILE); 573 assert(r.file != BAD_FILE); 574 575 if (try_rewrite_rhs_to_dst(ir, l, r, pre_rhs_inst, last_rhs_inst)) 576 return; 577 578 if (ir->condition) { 579 emit_bool_to_cond_code(ir->condition); 580 } 581 582 if (ir->lhs->type->is_scalar() || 583 ir->lhs->type->is_vector()) { 584 for (int i = 0; i < ir->lhs->type->vector_elements; i++) { 585 if (ir->write_mask & (1 << i)) { 586 inst = emit(BRW_OPCODE_MOV, l, r); 587 if (ir->condition) 588 inst->predicated = true; 589 r.reg_offset++; 590 } 591 l.reg_offset++; 592 } 593 } else { 594 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL); 595 } 596} 597 598fs_inst * 599fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate, 600 int sampler) 601{ 602 int mlen; 603 int base_mrf = 1; 604 bool simd16 = false; 605 fs_reg orig_dst; 606 607 /* g0 header. */ 608 mlen = 1; 609 610 if (ir->shadow_comparitor && ir->op != ir_txd) { 611 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 612 fs_inst *inst = emit(BRW_OPCODE_MOV, 613 fs_reg(MRF, base_mrf + mlen + i), coordinate); 614 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 615 inst->saturate = true; 616 617 coordinate.reg_offset++; 618 } 619 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 620 mlen += 3; 621 622 if (ir->op == ir_tex) { 623 /* There's no plain shadow compare message, so we use shadow 624 * compare with a bias of 0.0. 625 */ 626 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)); 627 mlen++; 628 } else if (ir->op == ir_txb) { 629 ir->lod_info.bias->accept(this); 630 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 631 mlen++; 632 } else { 633 assert(ir->op == ir_txl); 634 ir->lod_info.lod->accept(this); 635 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 636 mlen++; 637 } 638 639 ir->shadow_comparitor->accept(this); 640 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 641 mlen++; 642 } else if (ir->op == ir_tex) { 643 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 644 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), 645 coordinate); 646 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 647 inst->saturate = true; 648 coordinate.reg_offset++; 649 } 650 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 651 mlen += 3; 652 } else if (ir->op == ir_txd) { 653 ir->lod_info.grad.dPdx->accept(this); 654 fs_reg dPdx = this->result; 655 656 ir->lod_info.grad.dPdy->accept(this); 657 fs_reg dPdy = this->result; 658 659 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 660 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); 661 coordinate.reg_offset++; 662 } 663 /* the slots for u and v are always present, but r is optional */ 664 mlen += MAX2(ir->coordinate->type->vector_elements, 2); 665 666 /* P = u, v, r 667 * dPdx = dudx, dvdx, drdx 668 * dPdy = dudy, dvdy, drdy 669 * 670 * 1-arg: Does not exist. 671 * 672 * 2-arg: dudx dvdx dudy dvdy 673 * dPdx.x dPdx.y dPdy.x dPdy.y 674 * m4 m5 m6 m7 675 * 676 * 3-arg: dudx dvdx drdx dudy dvdy drdy 677 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z 678 * m5 m6 m7 m8 m9 m10 679 */ 680 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 681 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 682 dPdx.reg_offset++; 683 } 684 mlen += MAX2(ir->lod_info.grad.dPdx->type->vector_elements, 2); 685 686 for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) { 687 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 688 dPdy.reg_offset++; 689 } 690 mlen += MAX2(ir->lod_info.grad.dPdy->type->vector_elements, 2); 691 } else if (ir->op == ir_txs) { 692 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */ 693 simd16 = true; 694 ir->lod_info.lod->accept(this); 695 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 696 mlen += 2; 697 } else { 698 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod 699 * instructions. We'll need to do SIMD16 here. 700 */ 701 simd16 = true; 702 assert(ir->op == ir_txb || ir->op == ir_txl || ir->op == ir_txf); 703 704 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 705 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, 706 base_mrf + mlen + i * 2, 707 coordinate.type), 708 coordinate); 709 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 710 inst->saturate = true; 711 coordinate.reg_offset++; 712 } 713 714 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to 715 * be necessary for TXF (ld), but seems wise to do for all messages. 716 */ 717 for (int i = ir->coordinate->type->vector_elements; i < 3; i++) { 718 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i * 2), fs_reg(0.0f)); 719 } 720 721 /* lod/bias appears after u/v/r. */ 722 mlen += 6; 723 724 if (ir->op == ir_txb) { 725 ir->lod_info.bias->accept(this); 726 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 727 mlen++; 728 } else { 729 ir->lod_info.lod->accept(this); 730 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, this->result.type), 731 this->result); 732 mlen++; 733 } 734 735 /* The unused upper half. */ 736 mlen++; 737 } 738 739 if (simd16) { 740 /* Now, since we're doing simd16, the return is 2 interleaved 741 * vec4s where the odd-indexed ones are junk. We'll need to move 742 * this weirdness around to the expected layout. 743 */ 744 orig_dst = dst; 745 const glsl_type *vec_type = 746 glsl_type::get_instance(ir->type->base_type, 4, 1); 747 dst = fs_reg(this, glsl_type::get_array_instance(vec_type, 2)); 748 dst.type = intel->is_g4x ? brw_type_for_base_type(ir->type) 749 : BRW_REGISTER_TYPE_F; 750 } 751 752 fs_inst *inst = NULL; 753 switch (ir->op) { 754 case ir_tex: 755 inst = emit(FS_OPCODE_TEX, dst); 756 break; 757 case ir_txb: 758 inst = emit(FS_OPCODE_TXB, dst); 759 break; 760 case ir_txl: 761 inst = emit(FS_OPCODE_TXL, dst); 762 break; 763 case ir_txd: 764 inst = emit(FS_OPCODE_TXD, dst); 765 break; 766 case ir_txs: 767 inst = emit(FS_OPCODE_TXS, dst); 768 break; 769 case ir_txf: 770 inst = emit(FS_OPCODE_TXF, dst); 771 break; 772 } 773 inst->base_mrf = base_mrf; 774 inst->mlen = mlen; 775 inst->header_present = true; 776 777 if (simd16) { 778 for (int i = 0; i < 4; i++) { 779 emit(BRW_OPCODE_MOV, orig_dst, dst); 780 orig_dst.reg_offset++; 781 dst.reg_offset += 2; 782 } 783 } 784 785 return inst; 786} 787 788/* gen5's sampler has slots for u, v, r, array index, then optional 789 * parameters like shadow comparitor or LOD bias. If optional 790 * parameters aren't present, those base slots are optional and don't 791 * need to be included in the message. 792 * 793 * We don't fill in the unnecessary slots regardless, which may look 794 * surprising in the disassembly. 795 */ 796fs_inst * 797fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate, 798 int sampler) 799{ 800 int mlen = 0; 801 int base_mrf = 2; 802 int reg_width = c->dispatch_width / 8; 803 bool header_present = false; 804 const int vector_elements = 805 ir->coordinate ? ir->coordinate->type->vector_elements : 0; 806 807 if (ir->offset) { 808 /* The offsets set up by the ir_texture visitor are in the 809 * m1 header, so we can't go headerless. 810 */ 811 header_present = true; 812 mlen++; 813 base_mrf--; 814 } 815 816 for (int i = 0; i < vector_elements; i++) { 817 fs_inst *inst = emit(BRW_OPCODE_MOV, 818 fs_reg(MRF, base_mrf + mlen + i * reg_width, 819 coordinate.type), 820 coordinate); 821 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 822 inst->saturate = true; 823 coordinate.reg_offset++; 824 } 825 mlen += vector_elements * reg_width; 826 827 if (ir->shadow_comparitor && ir->op != ir_txd) { 828 mlen = MAX2(mlen, header_present + 4 * reg_width); 829 830 ir->shadow_comparitor->accept(this); 831 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 832 mlen += reg_width; 833 } 834 835 fs_inst *inst = NULL; 836 switch (ir->op) { 837 case ir_tex: 838 inst = emit(FS_OPCODE_TEX, dst); 839 break; 840 case ir_txb: 841 ir->lod_info.bias->accept(this); 842 mlen = MAX2(mlen, header_present + 4 * reg_width); 843 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 844 mlen += reg_width; 845 846 inst = emit(FS_OPCODE_TXB, dst); 847 848 break; 849 case ir_txl: 850 ir->lod_info.lod->accept(this); 851 mlen = MAX2(mlen, header_present + 4 * reg_width); 852 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 853 mlen += reg_width; 854 855 inst = emit(FS_OPCODE_TXL, dst); 856 break; 857 case ir_txd: { 858 ir->lod_info.grad.dPdx->accept(this); 859 fs_reg dPdx = this->result; 860 861 ir->lod_info.grad.dPdy->accept(this); 862 fs_reg dPdy = this->result; 863 864 mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */ 865 866 /** 867 * P = u, v, r 868 * dPdx = dudx, dvdx, drdx 869 * dPdy = dudy, dvdy, drdy 870 * 871 * Load up these values: 872 * - dudx dudy dvdx dvdy drdx drdy 873 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z 874 */ 875 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 876 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 877 dPdx.reg_offset++; 878 mlen += reg_width; 879 880 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 881 dPdy.reg_offset++; 882 mlen += reg_width; 883 } 884 885 inst = emit(FS_OPCODE_TXD, dst); 886 break; 887 } 888 case ir_txs: 889 ir->lod_info.lod->accept(this); 890 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 891 mlen += reg_width; 892 inst = emit(FS_OPCODE_TXS, dst); 893 break; 894 case ir_txf: 895 mlen = header_present + 4 * reg_width; 896 897 ir->lod_info.lod->accept(this); 898 emit(BRW_OPCODE_MOV, 899 fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), 900 this->result); 901 inst = emit(FS_OPCODE_TXF, dst); 902 break; 903 } 904 inst->base_mrf = base_mrf; 905 inst->mlen = mlen; 906 inst->header_present = header_present; 907 908 if (mlen > 11) { 909 fail("Message length >11 disallowed by hardware\n"); 910 } 911 912 return inst; 913} 914 915fs_inst * 916fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate, 917 int sampler) 918{ 919 int mlen = 0; 920 int base_mrf = 2; 921 int reg_width = c->dispatch_width / 8; 922 bool header_present = false; 923 924 if (ir->offset) { 925 /* The offsets set up by the ir_texture visitor are in the 926 * m1 header, so we can't go headerless. 927 */ 928 header_present = true; 929 mlen++; 930 base_mrf--; 931 } 932 933 if (ir->shadow_comparitor && ir->op != ir_txd) { 934 ir->shadow_comparitor->accept(this); 935 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 936 mlen += reg_width; 937 } 938 939 /* Set up the LOD info */ 940 switch (ir->op) { 941 case ir_tex: 942 break; 943 case ir_txb: 944 ir->lod_info.bias->accept(this); 945 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 946 mlen += reg_width; 947 break; 948 case ir_txl: 949 ir->lod_info.lod->accept(this); 950 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 951 mlen += reg_width; 952 break; 953 case ir_txd: { 954 if (c->dispatch_width == 16) 955 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode."); 956 957 ir->lod_info.grad.dPdx->accept(this); 958 fs_reg dPdx = this->result; 959 960 ir->lod_info.grad.dPdy->accept(this); 961 fs_reg dPdy = this->result; 962 963 /* Load dPdx and the coordinate together: 964 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z 965 */ 966 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 967 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 968 coordinate); 969 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 970 inst->saturate = true; 971 coordinate.reg_offset++; 972 mlen += reg_width; 973 974 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 975 dPdx.reg_offset++; 976 mlen += reg_width; 977 978 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 979 dPdy.reg_offset++; 980 mlen += reg_width; 981 } 982 break; 983 } 984 case ir_txs: 985 ir->lod_info.lod->accept(this); 986 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 987 mlen += reg_width; 988 break; 989 case ir_txf: 990 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */ 991 emit(BRW_OPCODE_MOV, 992 fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), coordinate); 993 coordinate.reg_offset++; 994 mlen += reg_width; 995 996 ir->lod_info.lod->accept(this); 997 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), this->result); 998 mlen += reg_width; 999 1000 for (int i = 1; i < ir->coordinate->type->vector_elements; i++) { 1001 emit(BRW_OPCODE_MOV, 1002 fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), coordinate); 1003 coordinate.reg_offset++; 1004 mlen += reg_width; 1005 } 1006 break; 1007 } 1008 1009 /* Set up the coordinate (except for cases where it was done above) */ 1010 if (ir->op != ir_txd && ir->op != ir_txs && ir->op != ir_txf) { 1011 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 1012 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 1013 coordinate); 1014 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 1015 inst->saturate = true; 1016 coordinate.reg_offset++; 1017 mlen += reg_width; 1018 } 1019 } 1020 1021 /* Generate the SEND */ 1022 fs_inst *inst = NULL; 1023 switch (ir->op) { 1024 case ir_tex: inst = emit(FS_OPCODE_TEX, dst); break; 1025 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break; 1026 case ir_txl: inst = emit(FS_OPCODE_TXL, dst); break; 1027 case ir_txd: inst = emit(FS_OPCODE_TXD, dst); break; 1028 case ir_txf: inst = emit(FS_OPCODE_TXF, dst); break; 1029 case ir_txs: inst = emit(FS_OPCODE_TXS, dst); break; 1030 } 1031 inst->base_mrf = base_mrf; 1032 inst->mlen = mlen; 1033 inst->header_present = header_present; 1034 1035 if (mlen > 11) { 1036 fail("Message length >11 disallowed by hardware\n"); 1037 } 1038 1039 return inst; 1040} 1041 1042void 1043fs_visitor::visit(ir_texture *ir) 1044{ 1045 fs_inst *inst = NULL; 1046 1047 int sampler = _mesa_get_sampler_uniform_value(ir->sampler, prog, &fp->Base); 1048 sampler = fp->Base.SamplerUnits[sampler]; 1049 1050 /* Our hardware doesn't have a sample_d_c message, so shadow compares 1051 * for textureGrad/TXD need to be emulated with instructions. 1052 */ 1053 bool hw_compare_supported = ir->op != ir_txd; 1054 if (ir->shadow_comparitor && !hw_compare_supported) { 1055 assert(c->key.compare_funcs[sampler] != GL_NONE); 1056 /* No need to even sample for GL_ALWAYS or GL_NEVER...bail early */ 1057 if (c->key.compare_funcs[sampler] == GL_ALWAYS) 1058 return swizzle_result(ir, fs_reg(1.0f), sampler); 1059 else if (c->key.compare_funcs[sampler] == GL_NEVER) 1060 return swizzle_result(ir, fs_reg(0.0f), sampler); 1061 } 1062 1063 if (ir->coordinate) 1064 ir->coordinate->accept(this); 1065 fs_reg coordinate = this->result; 1066 1067 if (ir->offset != NULL) { 1068 ir_constant *offset = ir->offset->as_constant(); 1069 assert(offset != NULL); 1070 1071 signed char offsets[3]; 1072 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) 1073 offsets[i] = (signed char) offset->value.i[i]; 1074 1075 /* Combine all three offsets into a single unsigned dword: 1076 * 1077 * bits 11:8 - U Offset (X component) 1078 * bits 7:4 - V Offset (Y component) 1079 * bits 3:0 - R Offset (Z component) 1080 */ 1081 unsigned offset_bits = 0; 1082 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) { 1083 const unsigned shift = 4 * (2 - i); 1084 offset_bits |= (offsets[i] << shift) & (0xF << shift); 1085 } 1086 1087 /* Explicitly set up the message header by copying g0 to msg reg m1. */ 1088 emit(BRW_OPCODE_MOV, fs_reg(MRF, 1, BRW_REGISTER_TYPE_UD), 1089 fs_reg(GRF, 0, BRW_REGISTER_TYPE_UD)); 1090 1091 /* Then set the offset bits in DWord 2 of the message header. */ 1092 emit(BRW_OPCODE_MOV, 1093 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 1, 2), 1094 BRW_REGISTER_TYPE_UD)), 1095 fs_reg(brw_imm_uw(offset_bits))); 1096 } 1097 1098 /* Should be lowered by do_lower_texture_projection */ 1099 assert(!ir->projector); 1100 1101 /* The 965 requires the EU to do the normalization of GL rectangle 1102 * texture coordinates. We use the program parameter state 1103 * tracking to get the scaling factor. 1104 */ 1105 if (intel->gen < 6 && 1106 ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) { 1107 struct gl_program_parameter_list *params = c->fp->program.Base.Parameters; 1108 int tokens[STATE_LENGTH] = { 1109 STATE_INTERNAL, 1110 STATE_TEXRECT_SCALE, 1111 sampler, 1112 0, 1113 0 1114 }; 1115 1116 if (c->dispatch_width == 16) { 1117 fail("rectangle scale uniform setup not supported on 16-wide\n"); 1118 this->result = fs_reg(this, ir->type); 1119 return; 1120 } 1121 1122 c->prog_data.param_convert[c->prog_data.nr_params] = 1123 PARAM_NO_CONVERT; 1124 c->prog_data.param_convert[c->prog_data.nr_params + 1] = 1125 PARAM_NO_CONVERT; 1126 1127 fs_reg scale_x = fs_reg(UNIFORM, c->prog_data.nr_params); 1128 fs_reg scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1); 1129 GLuint index = _mesa_add_state_reference(params, 1130 (gl_state_index *)tokens); 1131 1132 this->param_index[c->prog_data.nr_params] = index; 1133 this->param_offset[c->prog_data.nr_params] = 0; 1134 c->prog_data.nr_params++; 1135 this->param_index[c->prog_data.nr_params] = index; 1136 this->param_offset[c->prog_data.nr_params] = 1; 1137 c->prog_data.nr_params++; 1138 1139 fs_reg dst = fs_reg(this, ir->coordinate->type); 1140 fs_reg src = coordinate; 1141 coordinate = dst; 1142 1143 emit(BRW_OPCODE_MUL, dst, src, scale_x); 1144 dst.reg_offset++; 1145 src.reg_offset++; 1146 emit(BRW_OPCODE_MUL, dst, src, scale_y); 1147 } 1148 1149 /* Writemasking doesn't eliminate channels on SIMD8 texture 1150 * samples, so don't worry about them. 1151 */ 1152 fs_reg dst = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 4, 1)); 1153 1154 if (intel->gen >= 7) { 1155 inst = emit_texture_gen7(ir, dst, coordinate, sampler); 1156 } else if (intel->gen >= 5) { 1157 inst = emit_texture_gen5(ir, dst, coordinate, sampler); 1158 } else { 1159 inst = emit_texture_gen4(ir, dst, coordinate, sampler); 1160 } 1161 1162 /* If there's an offset, we already set up m1. To avoid the implied move, 1163 * use the null register. Otherwise, we want an implied move from g0. 1164 */ 1165 if (ir->offset != NULL || !inst->header_present) 1166 inst->src[0] = reg_undef; 1167 else 1168 inst->src[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW)); 1169 1170 inst->sampler = sampler; 1171 1172 if (ir->shadow_comparitor) { 1173 if (hw_compare_supported) { 1174 inst->shadow_compare = true; 1175 } else { 1176 ir->shadow_comparitor->accept(this); 1177 fs_reg ref = this->result; 1178 1179 fs_reg value = dst; 1180 dst = fs_reg(this, glsl_type::vec4_type); 1181 1182 /* FINISHME: This needs to be done pre-filtering. */ 1183 1184 uint32_t conditional = 0; 1185 switch (c->key.compare_funcs[sampler]) { 1186 /* GL_ALWAYS and GL_NEVER were handled at the top of the function */ 1187 case GL_LESS: conditional = BRW_CONDITIONAL_L; break; 1188 case GL_GREATER: conditional = BRW_CONDITIONAL_G; break; 1189 case GL_LEQUAL: conditional = BRW_CONDITIONAL_LE; break; 1190 case GL_GEQUAL: conditional = BRW_CONDITIONAL_GE; break; 1191 case GL_EQUAL: conditional = BRW_CONDITIONAL_EQ; break; 1192 case GL_NOTEQUAL: conditional = BRW_CONDITIONAL_NEQ; break; 1193 default: assert(!"Should not get here: bad shadow compare function"); 1194 } 1195 1196 /* Use conditional moves to load 0 or 1 as the result */ 1197 this->current_annotation = "manual shadow comparison"; 1198 for (int i = 0; i < 4; i++) { 1199 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(0.0f)); 1200 1201 inst = emit(BRW_OPCODE_CMP, reg_null_f, ref, value); 1202 inst->conditional_mod = conditional; 1203 1204 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(1.0f)); 1205 inst->predicated = true; 1206 1207 dst.reg_offset++; 1208 value.reg_offset++; 1209 } 1210 dst.reg_offset = 0; 1211 } 1212 } 1213 1214 swizzle_result(ir, dst, sampler); 1215} 1216 1217/** 1218 * Swizzle the result of a texture result. This is necessary for 1219 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons. 1220 */ 1221void 1222fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler) 1223{ 1224 this->result = orig_val; 1225 1226 if (ir->type == glsl_type::float_type) { 1227 /* Ignore DEPTH_TEXTURE_MODE swizzling. */ 1228 assert(ir->sampler->type->sampler_shadow); 1229 } else if (c->key.tex_swizzles[sampler] != SWIZZLE_NOOP) { 1230 fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type); 1231 1232 for (int i = 0; i < 4; i++) { 1233 int swiz = GET_SWZ(c->key.tex_swizzles[sampler], i); 1234 fs_reg l = swizzled_result; 1235 l.reg_offset += i; 1236 1237 if (swiz == SWIZZLE_ZERO) { 1238 emit(BRW_OPCODE_MOV, l, fs_reg(0.0f)); 1239 } else if (swiz == SWIZZLE_ONE) { 1240 emit(BRW_OPCODE_MOV, l, fs_reg(1.0f)); 1241 } else { 1242 fs_reg r = orig_val; 1243 r.reg_offset += GET_SWZ(c->key.tex_swizzles[sampler], i); 1244 emit(BRW_OPCODE_MOV, l, r); 1245 } 1246 } 1247 this->result = swizzled_result; 1248 } 1249} 1250 1251void 1252fs_visitor::visit(ir_swizzle *ir) 1253{ 1254 ir->val->accept(this); 1255 fs_reg val = this->result; 1256 1257 if (ir->type->vector_elements == 1) { 1258 this->result.reg_offset += ir->mask.x; 1259 return; 1260 } 1261 1262 fs_reg result = fs_reg(this, ir->type); 1263 this->result = result; 1264 1265 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 1266 fs_reg channel = val; 1267 int swiz = 0; 1268 1269 switch (i) { 1270 case 0: 1271 swiz = ir->mask.x; 1272 break; 1273 case 1: 1274 swiz = ir->mask.y; 1275 break; 1276 case 2: 1277 swiz = ir->mask.z; 1278 break; 1279 case 3: 1280 swiz = ir->mask.w; 1281 break; 1282 } 1283 1284 channel.reg_offset += swiz; 1285 emit(BRW_OPCODE_MOV, result, channel); 1286 result.reg_offset++; 1287 } 1288} 1289 1290void 1291fs_visitor::visit(ir_discard *ir) 1292{ 1293 assert(ir->condition == NULL); /* FINISHME */ 1294 1295 emit(FS_OPCODE_DISCARD); 1296 kill_emitted = true; 1297} 1298 1299void 1300fs_visitor::visit(ir_constant *ir) 1301{ 1302 /* Set this->result to reg at the bottom of the function because some code 1303 * paths will cause this visitor to be applied to other fields. This will 1304 * cause the value stored in this->result to be modified. 1305 * 1306 * Make reg constant so that it doesn't get accidentally modified along the 1307 * way. Yes, I actually had this problem. :( 1308 */ 1309 const fs_reg reg(this, ir->type); 1310 fs_reg dst_reg = reg; 1311 1312 if (ir->type->is_array()) { 1313 const unsigned size = type_size(ir->type->fields.array); 1314 1315 for (unsigned i = 0; i < ir->type->length; i++) { 1316 ir->array_elements[i]->accept(this); 1317 fs_reg src_reg = this->result; 1318 1319 dst_reg.type = src_reg.type; 1320 for (unsigned j = 0; j < size; j++) { 1321 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1322 src_reg.reg_offset++; 1323 dst_reg.reg_offset++; 1324 } 1325 } 1326 } else if (ir->type->is_record()) { 1327 foreach_list(node, &ir->components) { 1328 ir_instruction *const field = (ir_instruction *) node; 1329 const unsigned size = type_size(field->type); 1330 1331 field->accept(this); 1332 fs_reg src_reg = this->result; 1333 1334 dst_reg.type = src_reg.type; 1335 for (unsigned j = 0; j < size; j++) { 1336 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1337 src_reg.reg_offset++; 1338 dst_reg.reg_offset++; 1339 } 1340 } 1341 } else { 1342 const unsigned size = type_size(ir->type); 1343 1344 for (unsigned i = 0; i < size; i++) { 1345 switch (ir->type->base_type) { 1346 case GLSL_TYPE_FLOAT: 1347 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i])); 1348 break; 1349 case GLSL_TYPE_UINT: 1350 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i])); 1351 break; 1352 case GLSL_TYPE_INT: 1353 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.i[i])); 1354 break; 1355 case GLSL_TYPE_BOOL: 1356 emit(BRW_OPCODE_MOV, dst_reg, fs_reg((int)ir->value.b[i])); 1357 break; 1358 default: 1359 assert(!"Non-float/uint/int/bool constant"); 1360 } 1361 dst_reg.reg_offset++; 1362 } 1363 } 1364 1365 this->result = reg; 1366} 1367 1368void 1369fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir) 1370{ 1371 ir_expression *expr = ir->as_expression(); 1372 1373 if (expr) { 1374 fs_reg op[2]; 1375 fs_inst *inst; 1376 1377 assert(expr->get_num_operands() <= 2); 1378 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1379 assert(expr->operands[i]->type->is_scalar()); 1380 1381 expr->operands[i]->accept(this); 1382 op[i] = this->result; 1383 1384 resolve_ud_negate(&op[i]); 1385 } 1386 1387 switch (expr->operation) { 1388 case ir_unop_logic_not: 1389 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1)); 1390 inst->conditional_mod = BRW_CONDITIONAL_Z; 1391 break; 1392 1393 case ir_binop_logic_xor: 1394 inst = emit(BRW_OPCODE_XOR, reg_null_d, op[0], op[1]); 1395 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1396 break; 1397 1398 case ir_binop_logic_or: 1399 inst = emit(BRW_OPCODE_OR, reg_null_d, op[0], op[1]); 1400 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1401 break; 1402 1403 case ir_binop_logic_and: 1404 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], op[1]); 1405 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1406 break; 1407 1408 case ir_unop_f2b: 1409 if (intel->gen >= 6) { 1410 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0.0f)); 1411 } else { 1412 inst = emit(BRW_OPCODE_MOV, reg_null_f, op[0]); 1413 } 1414 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1415 break; 1416 1417 case ir_unop_i2b: 1418 if (intel->gen >= 6) { 1419 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0)); 1420 } else { 1421 inst = emit(BRW_OPCODE_MOV, reg_null_d, op[0]); 1422 } 1423 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1424 break; 1425 1426 case ir_binop_greater: 1427 case ir_binop_gequal: 1428 case ir_binop_less: 1429 case ir_binop_lequal: 1430 case ir_binop_equal: 1431 case ir_binop_all_equal: 1432 case ir_binop_nequal: 1433 case ir_binop_any_nequal: 1434 inst = emit(BRW_OPCODE_CMP, reg_null_cmp, op[0], op[1]); 1435 inst->conditional_mod = 1436 brw_conditional_for_comparison(expr->operation); 1437 break; 1438 1439 default: 1440 assert(!"not reached"); 1441 fail("bad cond code\n"); 1442 break; 1443 } 1444 return; 1445 } 1446 1447 ir->accept(this); 1448 1449 if (intel->gen >= 6) { 1450 fs_inst *inst = emit(BRW_OPCODE_AND, reg_null_d, this->result, fs_reg(1)); 1451 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1452 } else { 1453 fs_inst *inst = emit(BRW_OPCODE_MOV, reg_null_d, this->result); 1454 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1455 } 1456} 1457 1458/** 1459 * Emit a gen6 IF statement with the comparison folded into the IF 1460 * instruction. 1461 */ 1462void 1463fs_visitor::emit_if_gen6(ir_if *ir) 1464{ 1465 ir_expression *expr = ir->condition->as_expression(); 1466 1467 if (expr) { 1468 fs_reg op[2]; 1469 fs_inst *inst; 1470 fs_reg temp; 1471 1472 assert(expr->get_num_operands() <= 2); 1473 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1474 assert(expr->operands[i]->type->is_scalar()); 1475 1476 expr->operands[i]->accept(this); 1477 op[i] = this->result; 1478 } 1479 1480 switch (expr->operation) { 1481 case ir_unop_logic_not: 1482 inst = emit(BRW_OPCODE_IF, temp, op[0], fs_reg(0)); 1483 inst->conditional_mod = BRW_CONDITIONAL_Z; 1484 return; 1485 1486 case ir_binop_logic_xor: 1487 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1488 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1489 return; 1490 1491 case ir_binop_logic_or: 1492 temp = fs_reg(this, glsl_type::bool_type); 1493 emit(BRW_OPCODE_OR, temp, op[0], op[1]); 1494 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1495 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1496 return; 1497 1498 case ir_binop_logic_and: 1499 temp = fs_reg(this, glsl_type::bool_type); 1500 emit(BRW_OPCODE_AND, temp, op[0], op[1]); 1501 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1502 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1503 return; 1504 1505 case ir_unop_f2b: 1506 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0)); 1507 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1508 return; 1509 1510 case ir_unop_i2b: 1511 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1512 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1513 return; 1514 1515 case ir_binop_greater: 1516 case ir_binop_gequal: 1517 case ir_binop_less: 1518 case ir_binop_lequal: 1519 case ir_binop_equal: 1520 case ir_binop_all_equal: 1521 case ir_binop_nequal: 1522 case ir_binop_any_nequal: 1523 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1524 inst->conditional_mod = 1525 brw_conditional_for_comparison(expr->operation); 1526 return; 1527 default: 1528 assert(!"not reached"); 1529 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1530 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1531 fail("bad condition\n"); 1532 return; 1533 } 1534 return; 1535 } 1536 1537 ir->condition->accept(this); 1538 1539 fs_inst *inst = emit(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0)); 1540 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1541} 1542 1543void 1544fs_visitor::visit(ir_if *ir) 1545{ 1546 fs_inst *inst; 1547 1548 if (intel->gen < 6 && c->dispatch_width == 16) { 1549 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1550 } 1551 1552 /* Don't point the annotation at the if statement, because then it plus 1553 * the then and else blocks get printed. 1554 */ 1555 this->base_ir = ir->condition; 1556 1557 if (intel->gen == 6) { 1558 emit_if_gen6(ir); 1559 } else { 1560 emit_bool_to_cond_code(ir->condition); 1561 1562 inst = emit(BRW_OPCODE_IF); 1563 inst->predicated = true; 1564 } 1565 1566 foreach_list(node, &ir->then_instructions) { 1567 ir_instruction *ir = (ir_instruction *)node; 1568 this->base_ir = ir; 1569 1570 ir->accept(this); 1571 } 1572 1573 if (!ir->else_instructions.is_empty()) { 1574 emit(BRW_OPCODE_ELSE); 1575 1576 foreach_list(node, &ir->else_instructions) { 1577 ir_instruction *ir = (ir_instruction *)node; 1578 this->base_ir = ir; 1579 1580 ir->accept(this); 1581 } 1582 } 1583 1584 emit(BRW_OPCODE_ENDIF); 1585} 1586 1587void 1588fs_visitor::visit(ir_loop *ir) 1589{ 1590 fs_reg counter = reg_undef; 1591 1592 if (c->dispatch_width == 16) { 1593 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1594 } 1595 1596 if (ir->counter) { 1597 this->base_ir = ir->counter; 1598 ir->counter->accept(this); 1599 counter = *(variable_storage(ir->counter)); 1600 1601 if (ir->from) { 1602 this->base_ir = ir->from; 1603 ir->from->accept(this); 1604 1605 emit(BRW_OPCODE_MOV, counter, this->result); 1606 } 1607 } 1608 1609 emit(BRW_OPCODE_DO); 1610 1611 if (ir->to) { 1612 this->base_ir = ir->to; 1613 ir->to->accept(this); 1614 1615 fs_inst *inst = emit(BRW_OPCODE_CMP, reg_null_cmp, counter, this->result); 1616 inst->conditional_mod = brw_conditional_for_comparison(ir->cmp); 1617 1618 inst = emit(BRW_OPCODE_BREAK); 1619 inst->predicated = true; 1620 } 1621 1622 foreach_list(node, &ir->body_instructions) { 1623 ir_instruction *ir = (ir_instruction *)node; 1624 1625 this->base_ir = ir; 1626 ir->accept(this); 1627 } 1628 1629 if (ir->increment) { 1630 this->base_ir = ir->increment; 1631 ir->increment->accept(this); 1632 emit(BRW_OPCODE_ADD, counter, counter, this->result); 1633 } 1634 1635 emit(BRW_OPCODE_WHILE); 1636} 1637 1638void 1639fs_visitor::visit(ir_loop_jump *ir) 1640{ 1641 switch (ir->mode) { 1642 case ir_loop_jump::jump_break: 1643 emit(BRW_OPCODE_BREAK); 1644 break; 1645 case ir_loop_jump::jump_continue: 1646 emit(BRW_OPCODE_CONTINUE); 1647 break; 1648 } 1649} 1650 1651void 1652fs_visitor::visit(ir_call *ir) 1653{ 1654 assert(!"FINISHME"); 1655} 1656 1657void 1658fs_visitor::visit(ir_return *ir) 1659{ 1660 assert(!"FINISHME"); 1661} 1662 1663void 1664fs_visitor::visit(ir_function *ir) 1665{ 1666 /* Ignore function bodies other than main() -- we shouldn't see calls to 1667 * them since they should all be inlined before we get to ir_to_mesa. 1668 */ 1669 if (strcmp(ir->name, "main") == 0) { 1670 const ir_function_signature *sig; 1671 exec_list empty; 1672 1673 sig = ir->matching_signature(&empty); 1674 1675 assert(sig); 1676 1677 foreach_list(node, &sig->body) { 1678 ir_instruction *ir = (ir_instruction *)node; 1679 this->base_ir = ir; 1680 1681 ir->accept(this); 1682 } 1683 } 1684} 1685 1686void 1687fs_visitor::visit(ir_function_signature *ir) 1688{ 1689 assert(!"not reached"); 1690 (void)ir; 1691} 1692 1693fs_inst * 1694fs_visitor::emit(fs_inst inst) 1695{ 1696 fs_inst *list_inst = new(mem_ctx) fs_inst; 1697 *list_inst = inst; 1698 1699 if (force_uncompressed_stack > 0) 1700 list_inst->force_uncompressed = true; 1701 else if (force_sechalf_stack > 0) 1702 list_inst->force_sechalf = true; 1703 1704 list_inst->annotation = this->current_annotation; 1705 list_inst->ir = this->base_ir; 1706 1707 this->instructions.push_tail(list_inst); 1708 1709 return list_inst; 1710} 1711 1712/** Emits a dummy fragment shader consisting of magenta for bringup purposes. */ 1713void 1714fs_visitor::emit_dummy_fs() 1715{ 1716 /* Everyone's favorite color. */ 1717 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2), fs_reg(1.0f)); 1718 emit(BRW_OPCODE_MOV, fs_reg(MRF, 3), fs_reg(0.0f)); 1719 emit(BRW_OPCODE_MOV, fs_reg(MRF, 4), fs_reg(1.0f)); 1720 emit(BRW_OPCODE_MOV, fs_reg(MRF, 5), fs_reg(0.0f)); 1721 1722 fs_inst *write; 1723 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0)); 1724 write->base_mrf = 2; 1725} 1726 1727/* The register location here is relative to the start of the URB 1728 * data. It will get adjusted to be a real location before 1729 * generate_code() time. 1730 */ 1731struct brw_reg 1732fs_visitor::interp_reg(int location, int channel) 1733{ 1734 int regnr = urb_setup[location] * 2 + channel / 2; 1735 int stride = (channel & 1) * 4; 1736 1737 assert(urb_setup[location] != -1); 1738 1739 return brw_vec1_grf(regnr, stride); 1740} 1741 1742/** Emits the interpolation for the varying inputs. */ 1743void 1744fs_visitor::emit_interpolation_setup_gen4() 1745{ 1746 this->current_annotation = "compute pixel centers"; 1747 this->pixel_x = fs_reg(this, glsl_type::uint_type); 1748 this->pixel_y = fs_reg(this, glsl_type::uint_type); 1749 this->pixel_x.type = BRW_REGISTER_TYPE_UW; 1750 this->pixel_y.type = BRW_REGISTER_TYPE_UW; 1751 1752 emit(FS_OPCODE_PIXEL_X, this->pixel_x); 1753 emit(FS_OPCODE_PIXEL_Y, this->pixel_y); 1754 1755 this->current_annotation = "compute pixel deltas from v0"; 1756 if (brw->has_pln) { 1757 this->delta_x = fs_reg(this, glsl_type::vec2_type); 1758 this->delta_y = this->delta_x; 1759 this->delta_y.reg_offset++; 1760 } else { 1761 this->delta_x = fs_reg(this, glsl_type::float_type); 1762 this->delta_y = fs_reg(this, glsl_type::float_type); 1763 } 1764 emit(BRW_OPCODE_ADD, this->delta_x, 1765 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))); 1766 emit(BRW_OPCODE_ADD, this->delta_y, 1767 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))); 1768 1769 this->current_annotation = "compute pos.w and 1/pos.w"; 1770 /* Compute wpos.w. It's always in our setup, since it's needed to 1771 * interpolate the other attributes. 1772 */ 1773 this->wpos_w = fs_reg(this, glsl_type::float_type); 1774 emit(FS_OPCODE_LINTERP, wpos_w, this->delta_x, this->delta_y, 1775 interp_reg(FRAG_ATTRIB_WPOS, 3)); 1776 /* Compute the pixel 1/W value from wpos.w. */ 1777 this->pixel_w = fs_reg(this, glsl_type::float_type); 1778 emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w); 1779 this->current_annotation = NULL; 1780} 1781 1782/** Emits the interpolation for the varying inputs. */ 1783void 1784fs_visitor::emit_interpolation_setup_gen6() 1785{ 1786 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); 1787 1788 /* If the pixel centers end up used, the setup is the same as for gen4. */ 1789 this->current_annotation = "compute pixel centers"; 1790 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type); 1791 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type); 1792 int_pixel_x.type = BRW_REGISTER_TYPE_UW; 1793 int_pixel_y.type = BRW_REGISTER_TYPE_UW; 1794 emit(BRW_OPCODE_ADD, 1795 int_pixel_x, 1796 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), 1797 fs_reg(brw_imm_v(0x10101010))); 1798 emit(BRW_OPCODE_ADD, 1799 int_pixel_y, 1800 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), 1801 fs_reg(brw_imm_v(0x11001100))); 1802 1803 /* As of gen6, we can no longer mix float and int sources. We have 1804 * to turn the integer pixel centers into floats for their actual 1805 * use. 1806 */ 1807 this->pixel_x = fs_reg(this, glsl_type::float_type); 1808 this->pixel_y = fs_reg(this, glsl_type::float_type); 1809 emit(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x); 1810 emit(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y); 1811 1812 this->current_annotation = "compute pos.w"; 1813 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0)); 1814 this->wpos_w = fs_reg(this, glsl_type::float_type); 1815 emit_math(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w); 1816 1817 this->delta_x = fs_reg(brw_vec8_grf(2, 0)); 1818 this->delta_y = fs_reg(brw_vec8_grf(3, 0)); 1819 1820 this->current_annotation = NULL; 1821} 1822 1823void 1824fs_visitor::emit_color_write(int index, int first_color_mrf, fs_reg color) 1825{ 1826 int reg_width = c->dispatch_width / 8; 1827 fs_inst *inst; 1828 1829 if (c->dispatch_width == 8 || intel->gen >= 6) { 1830 /* SIMD8 write looks like: 1831 * m + 0: r0 1832 * m + 1: r1 1833 * m + 2: g0 1834 * m + 3: g1 1835 * 1836 * gen6 SIMD16 DP write looks like: 1837 * m + 0: r0 1838 * m + 1: r1 1839 * m + 2: g0 1840 * m + 3: g1 1841 * m + 4: b0 1842 * m + 5: b1 1843 * m + 6: a0 1844 * m + 7: a1 1845 */ 1846 inst = emit(BRW_OPCODE_MOV, 1847 fs_reg(MRF, first_color_mrf + index * reg_width), 1848 color); 1849 inst->saturate = c->key.clamp_fragment_color; 1850 } else { 1851 /* pre-gen6 SIMD16 single source DP write looks like: 1852 * m + 0: r0 1853 * m + 1: g0 1854 * m + 2: b0 1855 * m + 3: a0 1856 * m + 4: r1 1857 * m + 5: g1 1858 * m + 6: b1 1859 * m + 7: a1 1860 */ 1861 if (brw->has_compr4) { 1862 /* By setting the high bit of the MRF register number, we 1863 * indicate that we want COMPR4 mode - instead of doing the 1864 * usual destination + 1 for the second half we get 1865 * destination + 4. 1866 */ 1867 inst = emit(BRW_OPCODE_MOV, 1868 fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index), 1869 color); 1870 inst->saturate = c->key.clamp_fragment_color; 1871 } else { 1872 push_force_uncompressed(); 1873 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index), 1874 color); 1875 inst->saturate = c->key.clamp_fragment_color; 1876 pop_force_uncompressed(); 1877 1878 push_force_sechalf(); 1879 color.sechalf = true; 1880 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index + 4), 1881 color); 1882 inst->saturate = c->key.clamp_fragment_color; 1883 pop_force_sechalf(); 1884 color.sechalf = false; 1885 } 1886 } 1887} 1888 1889void 1890fs_visitor::emit_fb_writes() 1891{ 1892 this->current_annotation = "FB write header"; 1893 bool header_present = true; 1894 int base_mrf = 2; 1895 int nr = base_mrf; 1896 int reg_width = c->dispatch_width / 8; 1897 1898 if (intel->gen >= 6 && 1899 !this->kill_emitted && 1900 c->key.nr_color_regions == 1) { 1901 header_present = false; 1902 } 1903 1904 if (header_present) { 1905 /* m2, m3 header */ 1906 nr += 2; 1907 } 1908 1909 if (c->aa_dest_stencil_reg) { 1910 push_force_uncompressed(); 1911 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++), 1912 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))); 1913 pop_force_uncompressed(); 1914 } 1915 1916 /* Reserve space for color. It'll be filled in per MRT below. */ 1917 int color_mrf = nr; 1918 nr += 4 * reg_width; 1919 1920 if (c->source_depth_to_render_target) { 1921 if (intel->gen == 6 && c->dispatch_width == 16) { 1922 /* For outputting oDepth on gen6, SIMD8 writes have to be 1923 * used. This would require 8-wide moves of each half to 1924 * message regs, kind of like pre-gen5 SIMD16 FB writes. 1925 * Just bail on doing so for now. 1926 */ 1927 fail("Missing support for simd16 depth writes on gen6\n"); 1928 } 1929 1930 if (c->computes_depth) { 1931 /* Hand over gl_FragDepth. */ 1932 assert(this->frag_depth); 1933 fs_reg depth = *(variable_storage(this->frag_depth)); 1934 1935 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), depth); 1936 } else { 1937 /* Pass through the payload depth. */ 1938 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1939 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))); 1940 } 1941 nr += reg_width; 1942 } 1943 1944 if (c->dest_depth_reg) { 1945 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1946 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))); 1947 nr += reg_width; 1948 } 1949 1950 fs_reg color = reg_undef; 1951 if (this->frag_color) 1952 color = *(variable_storage(this->frag_color)); 1953 else if (this->frag_data) { 1954 color = *(variable_storage(this->frag_data)); 1955 color.type = BRW_REGISTER_TYPE_F; 1956 } 1957 1958 for (int target = 0; target < c->key.nr_color_regions; target++) { 1959 this->current_annotation = ralloc_asprintf(this->mem_ctx, 1960 "FB write target %d", 1961 target); 1962 if (this->frag_color || this->frag_data) { 1963 for (int i = 0; i < 4; i++) { 1964 emit_color_write(i, color_mrf, color); 1965 color.reg_offset++; 1966 } 1967 } 1968 1969 if (this->frag_color) 1970 color.reg_offset -= 4; 1971 1972 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1973 inst->target = target; 1974 inst->base_mrf = base_mrf; 1975 inst->mlen = nr - base_mrf; 1976 if (target == c->key.nr_color_regions - 1) 1977 inst->eot = true; 1978 inst->header_present = header_present; 1979 } 1980 1981 if (c->key.nr_color_regions == 0) { 1982 if (c->key.alpha_test && (this->frag_color || this->frag_data)) { 1983 /* If the alpha test is enabled but there's no color buffer, 1984 * we still need to send alpha out the pipeline to our null 1985 * renderbuffer. 1986 */ 1987 color.reg_offset += 3; 1988 emit_color_write(3, color_mrf, color); 1989 } 1990 1991 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1992 inst->base_mrf = base_mrf; 1993 inst->mlen = nr - base_mrf; 1994 inst->eot = true; 1995 inst->header_present = header_present; 1996 } 1997 1998 this->current_annotation = NULL; 1999} 2000 2001void 2002fs_visitor::resolve_ud_negate(fs_reg *reg) 2003{ 2004 if (reg->type != BRW_REGISTER_TYPE_UD || 2005 !reg->negate) 2006 return; 2007 2008 fs_reg temp = fs_reg(this, glsl_type::uint_type); 2009 emit(BRW_OPCODE_MOV, temp, *reg); 2010 *reg = temp; 2011} 2012