brw_fs_visitor.cpp revision 7c857a6b159debf76d4661f494fd2c97d205b5b1
1/* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24/** @file brw_fs_visitor.cpp 25 * 26 * This file supports generating the FS LIR from the GLSL IR. The LIR 27 * makes it easier to do backend-specific optimizations than doing so 28 * in the GLSL IR or in the native code. 29 */ 30extern "C" { 31 32#include <sys/types.h> 33 34#include "main/macros.h" 35#include "main/shaderobj.h" 36#include "main/uniforms.h" 37#include "program/prog_parameter.h" 38#include "program/prog_print.h" 39#include "program/prog_optimize.h" 40#include "program/register_allocate.h" 41#include "program/sampler.h" 42#include "program/hash_table.h" 43#include "brw_context.h" 44#include "brw_eu.h" 45#include "brw_wm.h" 46} 47#include "brw_shader.h" 48#include "brw_fs.h" 49#include "glsl/glsl_types.h" 50#include "glsl/ir_optimization.h" 51#include "glsl/ir_print_visitor.h" 52 53void 54fs_visitor::visit(ir_variable *ir) 55{ 56 fs_reg *reg = NULL; 57 58 if (variable_storage(ir)) 59 return; 60 61 if (ir->mode == ir_var_in) { 62 if (!strcmp(ir->name, "gl_FragCoord")) { 63 reg = emit_fragcoord_interpolation(ir); 64 } else if (!strcmp(ir->name, "gl_FrontFacing")) { 65 reg = emit_frontfacing_interpolation(ir); 66 } else { 67 reg = emit_general_interpolation(ir); 68 } 69 assert(reg); 70 hash_table_insert(this->variable_ht, reg, ir); 71 return; 72 } else if (ir->mode == ir_var_out) { 73 reg = new(this->mem_ctx) fs_reg(this, ir->type); 74 75 if (ir->location == FRAG_RESULT_COLOR) { 76 /* Writing gl_FragColor outputs to all color regions. */ 77 for (int i = 0; i < MAX2(c->key.nr_color_regions, 1); i++) { 78 this->outputs[i] = *reg; 79 } 80 } else if (ir->location == FRAG_RESULT_DEPTH) { 81 this->frag_depth = ir; 82 } else { 83 /* gl_FragData or a user-defined FS output */ 84 assert(ir->location >= FRAG_RESULT_DATA0 && 85 ir->location < FRAG_RESULT_DATA0 + BRW_MAX_DRAW_BUFFERS); 86 87 /* General color output. */ 88 for (unsigned int i = 0; i < MAX2(1, ir->type->length); i++) { 89 int output = ir->location - FRAG_RESULT_DATA0 + i; 90 this->outputs[output] = *reg; 91 this->outputs[output].reg_offset += 4 * i; 92 } 93 } 94 } else if (ir->mode == ir_var_uniform) { 95 int param_index = c->prog_data.nr_params; 96 97 if (c->dispatch_width == 16) { 98 if (!variable_storage(ir)) { 99 fail("Failed to find uniform '%s' in 16-wide\n", ir->name); 100 } 101 return; 102 } 103 104 if (!strncmp(ir->name, "gl_", 3)) { 105 setup_builtin_uniform_values(ir); 106 } else { 107 setup_uniform_values(ir->location, ir->type); 108 } 109 110 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index); 111 reg->type = brw_type_for_base_type(ir->type); 112 } 113 114 if (!reg) 115 reg = new(this->mem_ctx) fs_reg(this, ir->type); 116 117 hash_table_insert(this->variable_ht, reg, ir); 118} 119 120void 121fs_visitor::visit(ir_dereference_variable *ir) 122{ 123 fs_reg *reg = variable_storage(ir->var); 124 this->result = *reg; 125} 126 127void 128fs_visitor::visit(ir_dereference_record *ir) 129{ 130 const glsl_type *struct_type = ir->record->type; 131 132 ir->record->accept(this); 133 134 unsigned int offset = 0; 135 for (unsigned int i = 0; i < struct_type->length; i++) { 136 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0) 137 break; 138 offset += type_size(struct_type->fields.structure[i].type); 139 } 140 this->result.reg_offset += offset; 141 this->result.type = brw_type_for_base_type(ir->type); 142} 143 144void 145fs_visitor::visit(ir_dereference_array *ir) 146{ 147 ir_constant *index; 148 int element_size; 149 150 ir->array->accept(this); 151 index = ir->array_index->as_constant(); 152 153 element_size = type_size(ir->type); 154 this->result.type = brw_type_for_base_type(ir->type); 155 156 if (index) { 157 assert(this->result.file == UNIFORM || this->result.file == GRF); 158 this->result.reg_offset += index->value.i[0] * element_size; 159 } else { 160 assert(!"FINISHME: non-constant array element"); 161 } 162} 163 164/* Instruction selection: Produce a MOV.sat instead of 165 * MIN(MAX(val, 0), 1) when possible. 166 */ 167bool 168fs_visitor::try_emit_saturate(ir_expression *ir) 169{ 170 ir_rvalue *sat_val = ir->as_rvalue_to_saturate(); 171 172 if (!sat_val) 173 return false; 174 175 sat_val->accept(this); 176 fs_reg src = this->result; 177 178 this->result = fs_reg(this, ir->type); 179 fs_inst *inst = emit(BRW_OPCODE_MOV, this->result, src); 180 inst->saturate = true; 181 182 return true; 183} 184 185void 186fs_visitor::visit(ir_expression *ir) 187{ 188 unsigned int operand; 189 fs_reg op[2], temp; 190 fs_inst *inst; 191 192 assert(ir->get_num_operands() <= 2); 193 194 if (try_emit_saturate(ir)) 195 return; 196 197 for (operand = 0; operand < ir->get_num_operands(); operand++) { 198 ir->operands[operand]->accept(this); 199 if (this->result.file == BAD_FILE) { 200 ir_print_visitor v; 201 fail("Failed to get tree for expression operand:\n"); 202 ir->operands[operand]->accept(&v); 203 } 204 op[operand] = this->result; 205 206 /* Matrix expression operands should have been broken down to vector 207 * operations already. 208 */ 209 assert(!ir->operands[operand]->type->is_matrix()); 210 /* And then those vector operands should have been broken down to scalar. 211 */ 212 assert(!ir->operands[operand]->type->is_vector()); 213 } 214 215 /* Storage for our result. If our result goes into an assignment, it will 216 * just get copy-propagated out, so no worries. 217 */ 218 this->result = fs_reg(this, ir->type); 219 220 switch (ir->operation) { 221 case ir_unop_logic_not: 222 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is 223 * ones complement of the whole register, not just bit 0. 224 */ 225 emit(BRW_OPCODE_XOR, this->result, op[0], fs_reg(1)); 226 break; 227 case ir_unop_neg: 228 op[0].negate = !op[0].negate; 229 this->result = op[0]; 230 break; 231 case ir_unop_abs: 232 op[0].abs = true; 233 op[0].negate = false; 234 this->result = op[0]; 235 break; 236 case ir_unop_sign: 237 temp = fs_reg(this, ir->type); 238 239 emit(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)); 240 241 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 242 inst->conditional_mod = BRW_CONDITIONAL_G; 243 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)); 244 inst->predicated = true; 245 246 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 247 inst->conditional_mod = BRW_CONDITIONAL_L; 248 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)); 249 inst->predicated = true; 250 251 break; 252 case ir_unop_rcp: 253 emit_math(SHADER_OPCODE_RCP, this->result, op[0]); 254 break; 255 256 case ir_unop_exp2: 257 emit_math(SHADER_OPCODE_EXP2, this->result, op[0]); 258 break; 259 case ir_unop_log2: 260 emit_math(SHADER_OPCODE_LOG2, this->result, op[0]); 261 break; 262 case ir_unop_exp: 263 case ir_unop_log: 264 assert(!"not reached: should be handled by ir_explog_to_explog2"); 265 break; 266 case ir_unop_sin: 267 case ir_unop_sin_reduced: 268 emit_math(SHADER_OPCODE_SIN, this->result, op[0]); 269 break; 270 case ir_unop_cos: 271 case ir_unop_cos_reduced: 272 emit_math(SHADER_OPCODE_COS, this->result, op[0]); 273 break; 274 275 case ir_unop_dFdx: 276 emit(FS_OPCODE_DDX, this->result, op[0]); 277 break; 278 case ir_unop_dFdy: 279 emit(FS_OPCODE_DDY, this->result, op[0]); 280 break; 281 282 case ir_binop_add: 283 emit(BRW_OPCODE_ADD, this->result, op[0], op[1]); 284 break; 285 case ir_binop_sub: 286 assert(!"not reached: should be handled by ir_sub_to_add_neg"); 287 break; 288 289 case ir_binop_mul: 290 if (ir->type->is_integer()) { 291 /* For integer multiplication, the MUL uses the low 16 bits 292 * of one of the operands (src0 on gen6, src1 on gen7). The 293 * MACH accumulates in the contribution of the upper 16 bits 294 * of that operand. 295 * 296 * FINISHME: Emit just the MUL if we know an operand is small 297 * enough. 298 */ 299 struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_D); 300 301 emit(BRW_OPCODE_MUL, acc, op[0], op[1]); 302 emit(BRW_OPCODE_MACH, reg_null_d, op[0], op[1]); 303 emit(BRW_OPCODE_MOV, this->result, fs_reg(acc)); 304 } else { 305 emit(BRW_OPCODE_MUL, this->result, op[0], op[1]); 306 } 307 break; 308 case ir_binop_div: 309 if (intel->gen >= 7 && c->dispatch_width == 16) 310 fail("16-wide INTDIV unsupported\n"); 311 312 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */ 313 assert(ir->type->is_integer()); 314 emit_math(SHADER_OPCODE_INT_QUOTIENT, this->result, op[0], op[1]); 315 break; 316 case ir_binop_mod: 317 if (intel->gen >= 7 && c->dispatch_width == 16) 318 fail("16-wide INTDIV unsupported\n"); 319 320 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */ 321 assert(ir->type->is_integer()); 322 emit_math(SHADER_OPCODE_INT_REMAINDER, this->result, op[0], op[1]); 323 break; 324 325 case ir_binop_less: 326 case ir_binop_greater: 327 case ir_binop_lequal: 328 case ir_binop_gequal: 329 case ir_binop_equal: 330 case ir_binop_all_equal: 331 case ir_binop_nequal: 332 case ir_binop_any_nequal: 333 temp = this->result; 334 /* original gen4 does implicit conversion before comparison. */ 335 if (intel->gen < 5) 336 temp.type = op[0].type; 337 338 resolve_ud_negate(&op[0]); 339 resolve_ud_negate(&op[1]); 340 341 inst = emit(BRW_OPCODE_CMP, temp, op[0], op[1]); 342 inst->conditional_mod = brw_conditional_for_comparison(ir->operation); 343 emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)); 344 break; 345 346 case ir_binop_logic_xor: 347 emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 348 break; 349 350 case ir_binop_logic_or: 351 emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 352 break; 353 354 case ir_binop_logic_and: 355 emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 356 break; 357 358 case ir_binop_dot: 359 case ir_unop_any: 360 assert(!"not reached: should be handled by brw_fs_channel_expressions"); 361 break; 362 363 case ir_unop_noise: 364 assert(!"not reached: should be handled by lower_noise"); 365 break; 366 367 case ir_quadop_vector: 368 assert(!"not reached: should be handled by lower_quadop_vector"); 369 break; 370 371 case ir_unop_sqrt: 372 emit_math(SHADER_OPCODE_SQRT, this->result, op[0]); 373 break; 374 375 case ir_unop_rsq: 376 emit_math(SHADER_OPCODE_RSQ, this->result, op[0]); 377 break; 378 379 case ir_unop_i2u: 380 op[0].type = BRW_REGISTER_TYPE_UD; 381 this->result = op[0]; 382 break; 383 case ir_unop_u2i: 384 op[0].type = BRW_REGISTER_TYPE_D; 385 this->result = op[0]; 386 break; 387 case ir_unop_i2f: 388 case ir_unop_u2f: 389 case ir_unop_b2f: 390 case ir_unop_b2i: 391 case ir_unop_f2i: 392 emit(BRW_OPCODE_MOV, this->result, op[0]); 393 break; 394 case ir_unop_f2b: 395 case ir_unop_i2b: 396 temp = this->result; 397 /* original gen4 does implicit conversion before comparison. */ 398 if (intel->gen < 5) 399 temp.type = op[0].type; 400 401 resolve_ud_negate(&op[0]); 402 403 inst = emit(BRW_OPCODE_CMP, temp, op[0], fs_reg(0.0f)); 404 inst->conditional_mod = BRW_CONDITIONAL_NZ; 405 inst = emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(1)); 406 break; 407 408 case ir_unop_trunc: 409 emit(BRW_OPCODE_RNDZ, this->result, op[0]); 410 break; 411 case ir_unop_ceil: 412 op[0].negate = !op[0].negate; 413 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 414 this->result.negate = true; 415 break; 416 case ir_unop_floor: 417 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 418 break; 419 case ir_unop_fract: 420 inst = emit(BRW_OPCODE_FRC, this->result, op[0]); 421 break; 422 case ir_unop_round_even: 423 emit(BRW_OPCODE_RNDE, this->result, op[0]); 424 break; 425 426 case ir_binop_min: 427 resolve_ud_negate(&op[0]); 428 resolve_ud_negate(&op[1]); 429 430 if (intel->gen >= 6) { 431 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 432 inst->conditional_mod = BRW_CONDITIONAL_L; 433 } else { 434 /* Unalias the destination */ 435 this->result = fs_reg(this, ir->type); 436 437 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 438 inst->conditional_mod = BRW_CONDITIONAL_L; 439 440 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 441 inst->predicated = true; 442 } 443 break; 444 case ir_binop_max: 445 resolve_ud_negate(&op[0]); 446 resolve_ud_negate(&op[1]); 447 448 if (intel->gen >= 6) { 449 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 450 inst->conditional_mod = BRW_CONDITIONAL_GE; 451 } else { 452 /* Unalias the destination */ 453 this->result = fs_reg(this, ir->type); 454 455 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 456 inst->conditional_mod = BRW_CONDITIONAL_G; 457 458 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 459 inst->predicated = true; 460 } 461 break; 462 463 case ir_binop_pow: 464 emit_math(SHADER_OPCODE_POW, this->result, op[0], op[1]); 465 break; 466 467 case ir_unop_bit_not: 468 inst = emit(BRW_OPCODE_NOT, this->result, op[0]); 469 break; 470 case ir_binop_bit_and: 471 inst = emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 472 break; 473 case ir_binop_bit_xor: 474 inst = emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 475 break; 476 case ir_binop_bit_or: 477 inst = emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 478 break; 479 480 case ir_binop_lshift: 481 inst = emit(BRW_OPCODE_SHL, this->result, op[0], op[1]); 482 break; 483 484 case ir_binop_rshift: 485 if (ir->type->base_type == GLSL_TYPE_INT) 486 inst = emit(BRW_OPCODE_ASR, this->result, op[0], op[1]); 487 else 488 inst = emit(BRW_OPCODE_SHR, this->result, op[0], op[1]); 489 break; 490 } 491} 492 493void 494fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r, 495 const glsl_type *type, bool predicated) 496{ 497 switch (type->base_type) { 498 case GLSL_TYPE_FLOAT: 499 case GLSL_TYPE_UINT: 500 case GLSL_TYPE_INT: 501 case GLSL_TYPE_BOOL: 502 for (unsigned int i = 0; i < type->components(); i++) { 503 l.type = brw_type_for_base_type(type); 504 r.type = brw_type_for_base_type(type); 505 506 if (predicated || !l.equals(&r)) { 507 fs_inst *inst = emit(BRW_OPCODE_MOV, l, r); 508 inst->predicated = predicated; 509 } 510 511 l.reg_offset++; 512 r.reg_offset++; 513 } 514 break; 515 case GLSL_TYPE_ARRAY: 516 for (unsigned int i = 0; i < type->length; i++) { 517 emit_assignment_writes(l, r, type->fields.array, predicated); 518 } 519 break; 520 521 case GLSL_TYPE_STRUCT: 522 for (unsigned int i = 0; i < type->length; i++) { 523 emit_assignment_writes(l, r, type->fields.structure[i].type, 524 predicated); 525 } 526 break; 527 528 case GLSL_TYPE_SAMPLER: 529 break; 530 531 default: 532 assert(!"not reached"); 533 break; 534 } 535} 536 537/* If the RHS processing resulted in an instruction generating a 538 * temporary value, and it would be easy to rewrite the instruction to 539 * generate its result right into the LHS instead, do so. This ends 540 * up reliably removing instructions where it can be tricky to do so 541 * later without real UD chain information. 542 */ 543bool 544fs_visitor::try_rewrite_rhs_to_dst(ir_assignment *ir, 545 fs_reg dst, 546 fs_reg src, 547 fs_inst *pre_rhs_inst, 548 fs_inst *last_rhs_inst) 549{ 550 if (pre_rhs_inst == last_rhs_inst) 551 return false; /* No instructions generated to work with. */ 552 553 /* Only attempt if we're doing a direct assignment. */ 554 if (ir->condition || 555 !(ir->lhs->type->is_scalar() || 556 (ir->lhs->type->is_vector() && 557 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1))) 558 return false; 559 560 /* Make sure the last instruction generated our source reg. */ 561 if (last_rhs_inst->predicated || 562 last_rhs_inst->force_uncompressed || 563 last_rhs_inst->force_sechalf || 564 !src.equals(&last_rhs_inst->dst)) 565 return false; 566 567 /* Success! Rewrite the instruction. */ 568 last_rhs_inst->dst = dst; 569 570 return true; 571} 572 573void 574fs_visitor::visit(ir_assignment *ir) 575{ 576 fs_reg l, r; 577 fs_inst *inst; 578 579 /* FINISHME: arrays on the lhs */ 580 ir->lhs->accept(this); 581 l = this->result; 582 583 fs_inst *pre_rhs_inst = (fs_inst *) this->instructions.get_tail(); 584 585 ir->rhs->accept(this); 586 r = this->result; 587 588 fs_inst *last_rhs_inst = (fs_inst *) this->instructions.get_tail(); 589 590 assert(l.file != BAD_FILE); 591 assert(r.file != BAD_FILE); 592 593 if (try_rewrite_rhs_to_dst(ir, l, r, pre_rhs_inst, last_rhs_inst)) 594 return; 595 596 if (ir->condition) { 597 emit_bool_to_cond_code(ir->condition); 598 } 599 600 if (ir->lhs->type->is_scalar() || 601 ir->lhs->type->is_vector()) { 602 for (int i = 0; i < ir->lhs->type->vector_elements; i++) { 603 if (ir->write_mask & (1 << i)) { 604 inst = emit(BRW_OPCODE_MOV, l, r); 605 if (ir->condition) 606 inst->predicated = true; 607 r.reg_offset++; 608 } 609 l.reg_offset++; 610 } 611 } else { 612 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL); 613 } 614} 615 616fs_inst * 617fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate, 618 int sampler) 619{ 620 int mlen; 621 int base_mrf = 1; 622 bool simd16 = false; 623 fs_reg orig_dst; 624 625 /* g0 header. */ 626 mlen = 1; 627 628 if (ir->shadow_comparitor && ir->op != ir_txd) { 629 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 630 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); 631 coordinate.reg_offset++; 632 } 633 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 634 mlen += 3; 635 636 if (ir->op == ir_tex) { 637 /* There's no plain shadow compare message, so we use shadow 638 * compare with a bias of 0.0. 639 */ 640 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)); 641 mlen++; 642 } else if (ir->op == ir_txb) { 643 ir->lod_info.bias->accept(this); 644 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 645 mlen++; 646 } else { 647 assert(ir->op == ir_txl); 648 ir->lod_info.lod->accept(this); 649 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 650 mlen++; 651 } 652 653 ir->shadow_comparitor->accept(this); 654 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 655 mlen++; 656 } else if (ir->op == ir_tex) { 657 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 658 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); 659 coordinate.reg_offset++; 660 } 661 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 662 mlen += 3; 663 } else if (ir->op == ir_txd) { 664 ir->lod_info.grad.dPdx->accept(this); 665 fs_reg dPdx = this->result; 666 667 ir->lod_info.grad.dPdy->accept(this); 668 fs_reg dPdy = this->result; 669 670 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 671 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); 672 coordinate.reg_offset++; 673 } 674 /* the slots for u and v are always present, but r is optional */ 675 mlen += MAX2(ir->coordinate->type->vector_elements, 2); 676 677 /* P = u, v, r 678 * dPdx = dudx, dvdx, drdx 679 * dPdy = dudy, dvdy, drdy 680 * 681 * 1-arg: Does not exist. 682 * 683 * 2-arg: dudx dvdx dudy dvdy 684 * dPdx.x dPdx.y dPdy.x dPdy.y 685 * m4 m5 m6 m7 686 * 687 * 3-arg: dudx dvdx drdx dudy dvdy drdy 688 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z 689 * m5 m6 m7 m8 m9 m10 690 */ 691 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 692 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 693 dPdx.reg_offset++; 694 } 695 mlen += MAX2(ir->lod_info.grad.dPdx->type->vector_elements, 2); 696 697 for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) { 698 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 699 dPdy.reg_offset++; 700 } 701 mlen += MAX2(ir->lod_info.grad.dPdy->type->vector_elements, 2); 702 } else if (ir->op == ir_txs) { 703 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */ 704 simd16 = true; 705 ir->lod_info.lod->accept(this); 706 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 707 mlen += 2; 708 } else { 709 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod 710 * instructions. We'll need to do SIMD16 here. 711 */ 712 simd16 = true; 713 assert(ir->op == ir_txb || ir->op == ir_txl || ir->op == ir_txf); 714 715 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 716 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i * 2, coordinate.type), 717 coordinate); 718 coordinate.reg_offset++; 719 } 720 721 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to 722 * be necessary for TXF (ld), but seems wise to do for all messages. 723 */ 724 for (int i = ir->coordinate->type->vector_elements; i < 3; i++) { 725 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i * 2), fs_reg(0.0f)); 726 } 727 728 /* lod/bias appears after u/v/r. */ 729 mlen += 6; 730 731 if (ir->op == ir_txb) { 732 ir->lod_info.bias->accept(this); 733 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 734 mlen++; 735 } else { 736 ir->lod_info.lod->accept(this); 737 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, this->result.type), 738 this->result); 739 mlen++; 740 } 741 742 /* The unused upper half. */ 743 mlen++; 744 } 745 746 if (simd16) { 747 /* Now, since we're doing simd16, the return is 2 interleaved 748 * vec4s where the odd-indexed ones are junk. We'll need to move 749 * this weirdness around to the expected layout. 750 */ 751 orig_dst = dst; 752 const glsl_type *vec_type = 753 glsl_type::get_instance(ir->type->base_type, 4, 1); 754 dst = fs_reg(this, glsl_type::get_array_instance(vec_type, 2)); 755 dst.type = intel->is_g4x ? brw_type_for_base_type(ir->type) 756 : BRW_REGISTER_TYPE_F; 757 } 758 759 fs_inst *inst = NULL; 760 switch (ir->op) { 761 case ir_tex: 762 inst = emit(SHADER_OPCODE_TEX, dst); 763 break; 764 case ir_txb: 765 inst = emit(FS_OPCODE_TXB, dst); 766 break; 767 case ir_txl: 768 inst = emit(SHADER_OPCODE_TXL, dst); 769 break; 770 case ir_txd: 771 inst = emit(SHADER_OPCODE_TXD, dst); 772 break; 773 case ir_txs: 774 inst = emit(SHADER_OPCODE_TXS, dst); 775 break; 776 case ir_txf: 777 inst = emit(SHADER_OPCODE_TXF, dst); 778 break; 779 } 780 inst->base_mrf = base_mrf; 781 inst->mlen = mlen; 782 inst->header_present = true; 783 784 if (simd16) { 785 for (int i = 0; i < 4; i++) { 786 emit(BRW_OPCODE_MOV, orig_dst, dst); 787 orig_dst.reg_offset++; 788 dst.reg_offset += 2; 789 } 790 } 791 792 return inst; 793} 794 795/* gen5's sampler has slots for u, v, r, array index, then optional 796 * parameters like shadow comparitor or LOD bias. If optional 797 * parameters aren't present, those base slots are optional and don't 798 * need to be included in the message. 799 * 800 * We don't fill in the unnecessary slots regardless, which may look 801 * surprising in the disassembly. 802 */ 803fs_inst * 804fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate, 805 int sampler) 806{ 807 int mlen = 0; 808 int base_mrf = 2; 809 int reg_width = c->dispatch_width / 8; 810 bool header_present = false; 811 const int vector_elements = 812 ir->coordinate ? ir->coordinate->type->vector_elements : 0; 813 814 if (ir->offset) { 815 /* The offsets set up by the ir_texture visitor are in the 816 * m1 header, so we can't go headerless. 817 */ 818 header_present = true; 819 mlen++; 820 base_mrf--; 821 } 822 823 for (int i = 0; i < vector_elements; i++) { 824 emit(BRW_OPCODE_MOV, 825 fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type), 826 coordinate); 827 coordinate.reg_offset++; 828 } 829 mlen += vector_elements * reg_width; 830 831 if (ir->shadow_comparitor && ir->op != ir_txd) { 832 mlen = MAX2(mlen, header_present + 4 * reg_width); 833 834 ir->shadow_comparitor->accept(this); 835 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 836 mlen += reg_width; 837 } 838 839 fs_inst *inst = NULL; 840 switch (ir->op) { 841 case ir_tex: 842 inst = emit(SHADER_OPCODE_TEX, dst); 843 break; 844 case ir_txb: 845 ir->lod_info.bias->accept(this); 846 mlen = MAX2(mlen, header_present + 4 * reg_width); 847 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 848 mlen += reg_width; 849 850 inst = emit(FS_OPCODE_TXB, dst); 851 852 break; 853 case ir_txl: 854 ir->lod_info.lod->accept(this); 855 mlen = MAX2(mlen, header_present + 4 * reg_width); 856 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 857 mlen += reg_width; 858 859 inst = emit(SHADER_OPCODE_TXL, dst); 860 break; 861 case ir_txd: { 862 ir->lod_info.grad.dPdx->accept(this); 863 fs_reg dPdx = this->result; 864 865 ir->lod_info.grad.dPdy->accept(this); 866 fs_reg dPdy = this->result; 867 868 mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */ 869 870 /** 871 * P = u, v, r 872 * dPdx = dudx, dvdx, drdx 873 * dPdy = dudy, dvdy, drdy 874 * 875 * Load up these values: 876 * - dudx dudy dvdx dvdy drdx drdy 877 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z 878 */ 879 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 880 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 881 dPdx.reg_offset++; 882 mlen += reg_width; 883 884 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 885 dPdy.reg_offset++; 886 mlen += reg_width; 887 } 888 889 inst = emit(SHADER_OPCODE_TXD, dst); 890 break; 891 } 892 case ir_txs: 893 ir->lod_info.lod->accept(this); 894 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 895 mlen += reg_width; 896 inst = emit(SHADER_OPCODE_TXS, dst); 897 break; 898 case ir_txf: 899 mlen = header_present + 4 * reg_width; 900 901 ir->lod_info.lod->accept(this); 902 emit(BRW_OPCODE_MOV, 903 fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), 904 this->result); 905 inst = emit(SHADER_OPCODE_TXF, dst); 906 break; 907 } 908 inst->base_mrf = base_mrf; 909 inst->mlen = mlen; 910 inst->header_present = header_present; 911 912 if (mlen > 11) { 913 fail("Message length >11 disallowed by hardware\n"); 914 } 915 916 return inst; 917} 918 919fs_inst * 920fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate, 921 int sampler) 922{ 923 int mlen = 0; 924 int base_mrf = 2; 925 int reg_width = c->dispatch_width / 8; 926 bool header_present = false; 927 928 if (ir->offset) { 929 /* The offsets set up by the ir_texture visitor are in the 930 * m1 header, so we can't go headerless. 931 */ 932 header_present = true; 933 mlen++; 934 base_mrf--; 935 } 936 937 if (ir->shadow_comparitor && ir->op != ir_txd) { 938 ir->shadow_comparitor->accept(this); 939 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 940 mlen += reg_width; 941 } 942 943 /* Set up the LOD info */ 944 switch (ir->op) { 945 case ir_tex: 946 break; 947 case ir_txb: 948 ir->lod_info.bias->accept(this); 949 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 950 mlen += reg_width; 951 break; 952 case ir_txl: 953 ir->lod_info.lod->accept(this); 954 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 955 mlen += reg_width; 956 break; 957 case ir_txd: { 958 if (c->dispatch_width == 16) 959 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode."); 960 961 ir->lod_info.grad.dPdx->accept(this); 962 fs_reg dPdx = this->result; 963 964 ir->lod_info.grad.dPdy->accept(this); 965 fs_reg dPdy = this->result; 966 967 /* Load dPdx and the coordinate together: 968 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z 969 */ 970 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 971 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), coordinate); 972 coordinate.reg_offset++; 973 mlen += reg_width; 974 975 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 976 dPdx.reg_offset++; 977 mlen += reg_width; 978 979 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 980 dPdy.reg_offset++; 981 mlen += reg_width; 982 } 983 break; 984 } 985 case ir_txs: 986 ir->lod_info.lod->accept(this); 987 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 988 mlen += reg_width; 989 break; 990 case ir_txf: 991 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */ 992 emit(BRW_OPCODE_MOV, 993 fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), coordinate); 994 coordinate.reg_offset++; 995 mlen += reg_width; 996 997 ir->lod_info.lod->accept(this); 998 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), this->result); 999 mlen += reg_width; 1000 1001 for (int i = 1; i < ir->coordinate->type->vector_elements; i++) { 1002 emit(BRW_OPCODE_MOV, 1003 fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), coordinate); 1004 coordinate.reg_offset++; 1005 mlen += reg_width; 1006 } 1007 break; 1008 } 1009 1010 /* Set up the coordinate (except for cases where it was done above) */ 1011 if (ir->op != ir_txd && ir->op != ir_txs && ir->op != ir_txf) { 1012 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 1013 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), coordinate); 1014 coordinate.reg_offset++; 1015 mlen += reg_width; 1016 } 1017 } 1018 1019 /* Generate the SEND */ 1020 fs_inst *inst = NULL; 1021 switch (ir->op) { 1022 case ir_tex: inst = emit(SHADER_OPCODE_TEX, dst); break; 1023 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break; 1024 case ir_txl: inst = emit(SHADER_OPCODE_TXL, dst); break; 1025 case ir_txd: inst = emit(SHADER_OPCODE_TXD, dst); break; 1026 case ir_txf: inst = emit(SHADER_OPCODE_TXF, dst); break; 1027 case ir_txs: inst = emit(SHADER_OPCODE_TXS, dst); break; 1028 } 1029 inst->base_mrf = base_mrf; 1030 inst->mlen = mlen; 1031 inst->header_present = header_present; 1032 1033 if (mlen > 11) { 1034 fail("Message length >11 disallowed by hardware\n"); 1035 } 1036 1037 return inst; 1038} 1039 1040void 1041fs_visitor::visit(ir_texture *ir) 1042{ 1043 fs_inst *inst = NULL; 1044 1045 int sampler = _mesa_get_sampler_uniform_value(ir->sampler, prog, &fp->Base); 1046 sampler = fp->Base.SamplerUnits[sampler]; 1047 1048 /* Our hardware doesn't have a sample_d_c message, so shadow compares 1049 * for textureGrad/TXD need to be emulated with instructions. 1050 */ 1051 bool hw_compare_supported = ir->op != ir_txd; 1052 if (ir->shadow_comparitor && !hw_compare_supported) { 1053 assert(c->key.tex.compare_funcs[sampler] != GL_NONE); 1054 /* No need to even sample for GL_ALWAYS or GL_NEVER...bail early */ 1055 if (c->key.tex.compare_funcs[sampler] == GL_ALWAYS) 1056 return swizzle_result(ir, fs_reg(1.0f), sampler); 1057 else if (c->key.tex.compare_funcs[sampler] == GL_NEVER) 1058 return swizzle_result(ir, fs_reg(0.0f), sampler); 1059 } 1060 1061 if (ir->coordinate) 1062 ir->coordinate->accept(this); 1063 fs_reg coordinate = this->result; 1064 1065 if (ir->offset != NULL) { 1066 uint32_t offset_bits = brw_texture_offset(ir->offset->as_constant()); 1067 1068 /* Explicitly set up the message header by copying g0 to msg reg m1. */ 1069 emit(BRW_OPCODE_MOV, fs_reg(MRF, 1, BRW_REGISTER_TYPE_UD), 1070 fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD))); 1071 1072 /* Then set the offset bits in DWord 2 of the message header. */ 1073 emit(BRW_OPCODE_MOV, 1074 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 1, 2), 1075 BRW_REGISTER_TYPE_UD)), 1076 fs_reg(brw_imm_uw(offset_bits))); 1077 } 1078 1079 /* Should be lowered by do_lower_texture_projection */ 1080 assert(!ir->projector); 1081 1082 bool needs_gl_clamp = true; 1083 1084 fs_reg scale_x, scale_y; 1085 1086 /* The 965 requires the EU to do the normalization of GL rectangle 1087 * texture coordinates. We use the program parameter state 1088 * tracking to get the scaling factor. 1089 */ 1090 if (ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT && 1091 (intel->gen < 6 || 1092 (intel->gen >= 6 && (c->key.tex.gl_clamp_mask[0] & (1 << sampler) || 1093 c->key.tex.gl_clamp_mask[1] & (1 << sampler))))) { 1094 struct gl_program_parameter_list *params = c->fp->program.Base.Parameters; 1095 int tokens[STATE_LENGTH] = { 1096 STATE_INTERNAL, 1097 STATE_TEXRECT_SCALE, 1098 sampler, 1099 0, 1100 0 1101 }; 1102 1103 if (c->dispatch_width == 16) { 1104 fail("rectangle scale uniform setup not supported on 16-wide\n"); 1105 this->result = fs_reg(this, ir->type); 1106 return; 1107 } 1108 1109 c->prog_data.param_convert[c->prog_data.nr_params] = 1110 PARAM_NO_CONVERT; 1111 c->prog_data.param_convert[c->prog_data.nr_params + 1] = 1112 PARAM_NO_CONVERT; 1113 1114 scale_x = fs_reg(UNIFORM, c->prog_data.nr_params); 1115 scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1); 1116 1117 GLuint index = _mesa_add_state_reference(params, 1118 (gl_state_index *)tokens); 1119 1120 this->param_index[c->prog_data.nr_params] = index; 1121 this->param_offset[c->prog_data.nr_params] = 0; 1122 c->prog_data.nr_params++; 1123 this->param_index[c->prog_data.nr_params] = index; 1124 this->param_offset[c->prog_data.nr_params] = 1; 1125 c->prog_data.nr_params++; 1126 } 1127 1128 /* The 965 requires the EU to do the normalization of GL rectangle 1129 * texture coordinates. We use the program parameter state 1130 * tracking to get the scaling factor. 1131 */ 1132 if (intel->gen < 6 && 1133 ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) { 1134 fs_reg dst = fs_reg(this, ir->coordinate->type); 1135 fs_reg src = coordinate; 1136 coordinate = dst; 1137 1138 emit(BRW_OPCODE_MUL, dst, src, scale_x); 1139 dst.reg_offset++; 1140 src.reg_offset++; 1141 emit(BRW_OPCODE_MUL, dst, src, scale_y); 1142 } else if (ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) { 1143 /* On gen6+, the sampler handles the rectangle coordinates 1144 * natively, without needing rescaling. But that means we have 1145 * to do GL_CLAMP clamping at the [0, width], [0, height] scale, 1146 * not [0, 1] like the default case below. 1147 */ 1148 needs_gl_clamp = false; 1149 1150 for (int i = 0; i < 2; i++) { 1151 if (c->key.tex.gl_clamp_mask[i] & (1 << sampler)) { 1152 fs_reg chan = coordinate; 1153 chan.reg_offset += i; 1154 1155 inst = emit(BRW_OPCODE_SEL, chan, chan, brw_imm_f(0.0)); 1156 inst->conditional_mod = BRW_CONDITIONAL_G; 1157 1158 /* Our parameter comes in as 1.0/width or 1.0/height, 1159 * because that's what people normally want for doing 1160 * texture rectangle handling. We need width or height 1161 * for clamping, but we don't care enough to make a new 1162 * parameter type, so just invert back. 1163 */ 1164 fs_reg limit = fs_reg(this, glsl_type::float_type); 1165 emit(BRW_OPCODE_MOV, limit, i == 0 ? scale_x : scale_y); 1166 emit(SHADER_OPCODE_RCP, limit, limit); 1167 1168 inst = emit(BRW_OPCODE_SEL, chan, chan, limit); 1169 inst->conditional_mod = BRW_CONDITIONAL_L; 1170 } 1171 } 1172 } 1173 1174 if (ir->coordinate && needs_gl_clamp) { 1175 for (int i = 0; i < MIN2(ir->coordinate->type->vector_elements, 3); i++) { 1176 if (c->key.tex.gl_clamp_mask[i] & (1 << sampler)) { 1177 fs_reg chan = coordinate; 1178 chan.reg_offset += i; 1179 1180 fs_inst *inst = emit(BRW_OPCODE_MOV, chan, chan); 1181 inst->saturate = true; 1182 } 1183 } 1184 } 1185 1186 /* Writemasking doesn't eliminate channels on SIMD8 texture 1187 * samples, so don't worry about them. 1188 */ 1189 fs_reg dst = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 4, 1)); 1190 1191 if (intel->gen >= 7) { 1192 inst = emit_texture_gen7(ir, dst, coordinate, sampler); 1193 } else if (intel->gen >= 5) { 1194 inst = emit_texture_gen5(ir, dst, coordinate, sampler); 1195 } else { 1196 inst = emit_texture_gen4(ir, dst, coordinate, sampler); 1197 } 1198 1199 /* If there's an offset, we already set up m1. To avoid the implied move, 1200 * use the null register. Otherwise, we want an implied move from g0. 1201 */ 1202 if (ir->offset != NULL || !inst->header_present) 1203 inst->src[0] = reg_undef; 1204 else 1205 inst->src[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW)); 1206 1207 inst->sampler = sampler; 1208 1209 if (ir->shadow_comparitor) { 1210 if (hw_compare_supported) { 1211 inst->shadow_compare = true; 1212 } else { 1213 ir->shadow_comparitor->accept(this); 1214 fs_reg ref = this->result; 1215 1216 fs_reg value = dst; 1217 dst = fs_reg(this, glsl_type::vec4_type); 1218 1219 /* FINISHME: This needs to be done pre-filtering. */ 1220 1221 uint32_t conditional = 0; 1222 switch (c->key.tex.compare_funcs[sampler]) { 1223 /* GL_ALWAYS and GL_NEVER were handled at the top of the function */ 1224 case GL_LESS: conditional = BRW_CONDITIONAL_L; break; 1225 case GL_GREATER: conditional = BRW_CONDITIONAL_G; break; 1226 case GL_LEQUAL: conditional = BRW_CONDITIONAL_LE; break; 1227 case GL_GEQUAL: conditional = BRW_CONDITIONAL_GE; break; 1228 case GL_EQUAL: conditional = BRW_CONDITIONAL_EQ; break; 1229 case GL_NOTEQUAL: conditional = BRW_CONDITIONAL_NEQ; break; 1230 default: assert(!"Should not get here: bad shadow compare function"); 1231 } 1232 1233 /* Use conditional moves to load 0 or 1 as the result */ 1234 this->current_annotation = "manual shadow comparison"; 1235 for (int i = 0; i < 4; i++) { 1236 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(0.0f)); 1237 1238 inst = emit(BRW_OPCODE_CMP, reg_null_f, ref, value); 1239 inst->conditional_mod = conditional; 1240 1241 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(1.0f)); 1242 inst->predicated = true; 1243 1244 dst.reg_offset++; 1245 value.reg_offset++; 1246 } 1247 dst.reg_offset = 0; 1248 } 1249 } 1250 1251 swizzle_result(ir, dst, sampler); 1252} 1253 1254/** 1255 * Swizzle the result of a texture result. This is necessary for 1256 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons. 1257 */ 1258void 1259fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler) 1260{ 1261 this->result = orig_val; 1262 1263 if (ir->op == ir_txs) 1264 return; 1265 1266 if (ir->type == glsl_type::float_type) { 1267 /* Ignore DEPTH_TEXTURE_MODE swizzling. */ 1268 assert(ir->sampler->type->sampler_shadow); 1269 } else if (c->key.tex.swizzles[sampler] != SWIZZLE_NOOP) { 1270 fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type); 1271 1272 for (int i = 0; i < 4; i++) { 1273 int swiz = GET_SWZ(c->key.tex.swizzles[sampler], i); 1274 fs_reg l = swizzled_result; 1275 l.reg_offset += i; 1276 1277 if (swiz == SWIZZLE_ZERO) { 1278 emit(BRW_OPCODE_MOV, l, fs_reg(0.0f)); 1279 } else if (swiz == SWIZZLE_ONE) { 1280 emit(BRW_OPCODE_MOV, l, fs_reg(1.0f)); 1281 } else { 1282 fs_reg r = orig_val; 1283 r.reg_offset += GET_SWZ(c->key.tex.swizzles[sampler], i); 1284 emit(BRW_OPCODE_MOV, l, r); 1285 } 1286 } 1287 this->result = swizzled_result; 1288 } 1289} 1290 1291void 1292fs_visitor::visit(ir_swizzle *ir) 1293{ 1294 ir->val->accept(this); 1295 fs_reg val = this->result; 1296 1297 if (ir->type->vector_elements == 1) { 1298 this->result.reg_offset += ir->mask.x; 1299 return; 1300 } 1301 1302 fs_reg result = fs_reg(this, ir->type); 1303 this->result = result; 1304 1305 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 1306 fs_reg channel = val; 1307 int swiz = 0; 1308 1309 switch (i) { 1310 case 0: 1311 swiz = ir->mask.x; 1312 break; 1313 case 1: 1314 swiz = ir->mask.y; 1315 break; 1316 case 2: 1317 swiz = ir->mask.z; 1318 break; 1319 case 3: 1320 swiz = ir->mask.w; 1321 break; 1322 } 1323 1324 channel.reg_offset += swiz; 1325 emit(BRW_OPCODE_MOV, result, channel); 1326 result.reg_offset++; 1327 } 1328} 1329 1330void 1331fs_visitor::visit(ir_discard *ir) 1332{ 1333 assert(ir->condition == NULL); /* FINISHME */ 1334 1335 emit(FS_OPCODE_DISCARD); 1336 kill_emitted = true; 1337} 1338 1339void 1340fs_visitor::visit(ir_constant *ir) 1341{ 1342 /* Set this->result to reg at the bottom of the function because some code 1343 * paths will cause this visitor to be applied to other fields. This will 1344 * cause the value stored in this->result to be modified. 1345 * 1346 * Make reg constant so that it doesn't get accidentally modified along the 1347 * way. Yes, I actually had this problem. :( 1348 */ 1349 const fs_reg reg(this, ir->type); 1350 fs_reg dst_reg = reg; 1351 1352 if (ir->type->is_array()) { 1353 const unsigned size = type_size(ir->type->fields.array); 1354 1355 for (unsigned i = 0; i < ir->type->length; i++) { 1356 ir->array_elements[i]->accept(this); 1357 fs_reg src_reg = this->result; 1358 1359 dst_reg.type = src_reg.type; 1360 for (unsigned j = 0; j < size; j++) { 1361 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1362 src_reg.reg_offset++; 1363 dst_reg.reg_offset++; 1364 } 1365 } 1366 } else if (ir->type->is_record()) { 1367 foreach_list(node, &ir->components) { 1368 ir_instruction *const field = (ir_instruction *) node; 1369 const unsigned size = type_size(field->type); 1370 1371 field->accept(this); 1372 fs_reg src_reg = this->result; 1373 1374 dst_reg.type = src_reg.type; 1375 for (unsigned j = 0; j < size; j++) { 1376 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1377 src_reg.reg_offset++; 1378 dst_reg.reg_offset++; 1379 } 1380 } 1381 } else { 1382 const unsigned size = type_size(ir->type); 1383 1384 for (unsigned i = 0; i < size; i++) { 1385 switch (ir->type->base_type) { 1386 case GLSL_TYPE_FLOAT: 1387 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i])); 1388 break; 1389 case GLSL_TYPE_UINT: 1390 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i])); 1391 break; 1392 case GLSL_TYPE_INT: 1393 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.i[i])); 1394 break; 1395 case GLSL_TYPE_BOOL: 1396 emit(BRW_OPCODE_MOV, dst_reg, fs_reg((int)ir->value.b[i])); 1397 break; 1398 default: 1399 assert(!"Non-float/uint/int/bool constant"); 1400 } 1401 dst_reg.reg_offset++; 1402 } 1403 } 1404 1405 this->result = reg; 1406} 1407 1408void 1409fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir) 1410{ 1411 ir_expression *expr = ir->as_expression(); 1412 1413 if (expr) { 1414 fs_reg op[2]; 1415 fs_inst *inst; 1416 1417 assert(expr->get_num_operands() <= 2); 1418 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1419 assert(expr->operands[i]->type->is_scalar()); 1420 1421 expr->operands[i]->accept(this); 1422 op[i] = this->result; 1423 1424 resolve_ud_negate(&op[i]); 1425 } 1426 1427 switch (expr->operation) { 1428 case ir_unop_logic_not: 1429 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1)); 1430 inst->conditional_mod = BRW_CONDITIONAL_Z; 1431 break; 1432 1433 case ir_binop_logic_xor: 1434 inst = emit(BRW_OPCODE_XOR, reg_null_d, op[0], op[1]); 1435 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1436 break; 1437 1438 case ir_binop_logic_or: 1439 inst = emit(BRW_OPCODE_OR, reg_null_d, op[0], op[1]); 1440 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1441 break; 1442 1443 case ir_binop_logic_and: 1444 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], op[1]); 1445 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1446 break; 1447 1448 case ir_unop_f2b: 1449 if (intel->gen >= 6) { 1450 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0.0f)); 1451 } else { 1452 inst = emit(BRW_OPCODE_MOV, reg_null_f, op[0]); 1453 } 1454 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1455 break; 1456 1457 case ir_unop_i2b: 1458 if (intel->gen >= 6) { 1459 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0)); 1460 } else { 1461 inst = emit(BRW_OPCODE_MOV, reg_null_d, op[0]); 1462 } 1463 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1464 break; 1465 1466 case ir_binop_greater: 1467 case ir_binop_gequal: 1468 case ir_binop_less: 1469 case ir_binop_lequal: 1470 case ir_binop_equal: 1471 case ir_binop_all_equal: 1472 case ir_binop_nequal: 1473 case ir_binop_any_nequal: 1474 inst = emit(BRW_OPCODE_CMP, reg_null_cmp, op[0], op[1]); 1475 inst->conditional_mod = 1476 brw_conditional_for_comparison(expr->operation); 1477 break; 1478 1479 default: 1480 assert(!"not reached"); 1481 fail("bad cond code\n"); 1482 break; 1483 } 1484 return; 1485 } 1486 1487 ir->accept(this); 1488 1489 if (intel->gen >= 6) { 1490 fs_inst *inst = emit(BRW_OPCODE_AND, reg_null_d, this->result, fs_reg(1)); 1491 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1492 } else { 1493 fs_inst *inst = emit(BRW_OPCODE_MOV, reg_null_d, this->result); 1494 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1495 } 1496} 1497 1498/** 1499 * Emit a gen6 IF statement with the comparison folded into the IF 1500 * instruction. 1501 */ 1502void 1503fs_visitor::emit_if_gen6(ir_if *ir) 1504{ 1505 ir_expression *expr = ir->condition->as_expression(); 1506 1507 if (expr) { 1508 fs_reg op[2]; 1509 fs_inst *inst; 1510 fs_reg temp; 1511 1512 assert(expr->get_num_operands() <= 2); 1513 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1514 assert(expr->operands[i]->type->is_scalar()); 1515 1516 expr->operands[i]->accept(this); 1517 op[i] = this->result; 1518 } 1519 1520 switch (expr->operation) { 1521 case ir_unop_logic_not: 1522 inst = emit(BRW_OPCODE_IF, temp, op[0], fs_reg(0)); 1523 inst->conditional_mod = BRW_CONDITIONAL_Z; 1524 return; 1525 1526 case ir_binop_logic_xor: 1527 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1528 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1529 return; 1530 1531 case ir_binop_logic_or: 1532 temp = fs_reg(this, glsl_type::bool_type); 1533 emit(BRW_OPCODE_OR, temp, op[0], op[1]); 1534 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1535 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1536 return; 1537 1538 case ir_binop_logic_and: 1539 temp = fs_reg(this, glsl_type::bool_type); 1540 emit(BRW_OPCODE_AND, temp, op[0], op[1]); 1541 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1542 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1543 return; 1544 1545 case ir_unop_f2b: 1546 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0)); 1547 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1548 return; 1549 1550 case ir_unop_i2b: 1551 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1552 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1553 return; 1554 1555 case ir_binop_greater: 1556 case ir_binop_gequal: 1557 case ir_binop_less: 1558 case ir_binop_lequal: 1559 case ir_binop_equal: 1560 case ir_binop_all_equal: 1561 case ir_binop_nequal: 1562 case ir_binop_any_nequal: 1563 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1564 inst->conditional_mod = 1565 brw_conditional_for_comparison(expr->operation); 1566 return; 1567 default: 1568 assert(!"not reached"); 1569 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1570 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1571 fail("bad condition\n"); 1572 return; 1573 } 1574 return; 1575 } 1576 1577 ir->condition->accept(this); 1578 1579 fs_inst *inst = emit(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0)); 1580 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1581} 1582 1583void 1584fs_visitor::visit(ir_if *ir) 1585{ 1586 fs_inst *inst; 1587 1588 if (intel->gen < 6 && c->dispatch_width == 16) { 1589 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1590 } 1591 1592 /* Don't point the annotation at the if statement, because then it plus 1593 * the then and else blocks get printed. 1594 */ 1595 this->base_ir = ir->condition; 1596 1597 if (intel->gen == 6) { 1598 emit_if_gen6(ir); 1599 } else { 1600 emit_bool_to_cond_code(ir->condition); 1601 1602 inst = emit(BRW_OPCODE_IF); 1603 inst->predicated = true; 1604 } 1605 1606 foreach_list(node, &ir->then_instructions) { 1607 ir_instruction *ir = (ir_instruction *)node; 1608 this->base_ir = ir; 1609 1610 ir->accept(this); 1611 } 1612 1613 if (!ir->else_instructions.is_empty()) { 1614 emit(BRW_OPCODE_ELSE); 1615 1616 foreach_list(node, &ir->else_instructions) { 1617 ir_instruction *ir = (ir_instruction *)node; 1618 this->base_ir = ir; 1619 1620 ir->accept(this); 1621 } 1622 } 1623 1624 emit(BRW_OPCODE_ENDIF); 1625} 1626 1627void 1628fs_visitor::visit(ir_loop *ir) 1629{ 1630 fs_reg counter = reg_undef; 1631 1632 if (c->dispatch_width == 16) { 1633 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1634 } 1635 1636 if (ir->counter) { 1637 this->base_ir = ir->counter; 1638 ir->counter->accept(this); 1639 counter = *(variable_storage(ir->counter)); 1640 1641 if (ir->from) { 1642 this->base_ir = ir->from; 1643 ir->from->accept(this); 1644 1645 emit(BRW_OPCODE_MOV, counter, this->result); 1646 } 1647 } 1648 1649 emit(BRW_OPCODE_DO); 1650 1651 if (ir->to) { 1652 this->base_ir = ir->to; 1653 ir->to->accept(this); 1654 1655 fs_inst *inst = emit(BRW_OPCODE_CMP, reg_null_cmp, counter, this->result); 1656 inst->conditional_mod = brw_conditional_for_comparison(ir->cmp); 1657 1658 inst = emit(BRW_OPCODE_BREAK); 1659 inst->predicated = true; 1660 } 1661 1662 foreach_list(node, &ir->body_instructions) { 1663 ir_instruction *ir = (ir_instruction *)node; 1664 1665 this->base_ir = ir; 1666 ir->accept(this); 1667 } 1668 1669 if (ir->increment) { 1670 this->base_ir = ir->increment; 1671 ir->increment->accept(this); 1672 emit(BRW_OPCODE_ADD, counter, counter, this->result); 1673 } 1674 1675 emit(BRW_OPCODE_WHILE); 1676} 1677 1678void 1679fs_visitor::visit(ir_loop_jump *ir) 1680{ 1681 switch (ir->mode) { 1682 case ir_loop_jump::jump_break: 1683 emit(BRW_OPCODE_BREAK); 1684 break; 1685 case ir_loop_jump::jump_continue: 1686 emit(BRW_OPCODE_CONTINUE); 1687 break; 1688 } 1689} 1690 1691void 1692fs_visitor::visit(ir_call *ir) 1693{ 1694 assert(!"FINISHME"); 1695} 1696 1697void 1698fs_visitor::visit(ir_return *ir) 1699{ 1700 assert(!"FINISHME"); 1701} 1702 1703void 1704fs_visitor::visit(ir_function *ir) 1705{ 1706 /* Ignore function bodies other than main() -- we shouldn't see calls to 1707 * them since they should all be inlined before we get to ir_to_mesa. 1708 */ 1709 if (strcmp(ir->name, "main") == 0) { 1710 const ir_function_signature *sig; 1711 exec_list empty; 1712 1713 sig = ir->matching_signature(&empty); 1714 1715 assert(sig); 1716 1717 foreach_list(node, &sig->body) { 1718 ir_instruction *ir = (ir_instruction *)node; 1719 this->base_ir = ir; 1720 1721 ir->accept(this); 1722 } 1723 } 1724} 1725 1726void 1727fs_visitor::visit(ir_function_signature *ir) 1728{ 1729 assert(!"not reached"); 1730 (void)ir; 1731} 1732 1733fs_inst * 1734fs_visitor::emit(fs_inst inst) 1735{ 1736 fs_inst *list_inst = new(mem_ctx) fs_inst; 1737 *list_inst = inst; 1738 1739 if (force_uncompressed_stack > 0) 1740 list_inst->force_uncompressed = true; 1741 else if (force_sechalf_stack > 0) 1742 list_inst->force_sechalf = true; 1743 1744 list_inst->annotation = this->current_annotation; 1745 list_inst->ir = this->base_ir; 1746 1747 this->instructions.push_tail(list_inst); 1748 1749 return list_inst; 1750} 1751 1752/** Emits a dummy fragment shader consisting of magenta for bringup purposes. */ 1753void 1754fs_visitor::emit_dummy_fs() 1755{ 1756 /* Everyone's favorite color. */ 1757 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2), fs_reg(1.0f)); 1758 emit(BRW_OPCODE_MOV, fs_reg(MRF, 3), fs_reg(0.0f)); 1759 emit(BRW_OPCODE_MOV, fs_reg(MRF, 4), fs_reg(1.0f)); 1760 emit(BRW_OPCODE_MOV, fs_reg(MRF, 5), fs_reg(0.0f)); 1761 1762 fs_inst *write; 1763 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0)); 1764 write->base_mrf = 2; 1765} 1766 1767/* The register location here is relative to the start of the URB 1768 * data. It will get adjusted to be a real location before 1769 * generate_code() time. 1770 */ 1771struct brw_reg 1772fs_visitor::interp_reg(int location, int channel) 1773{ 1774 int regnr = urb_setup[location] * 2 + channel / 2; 1775 int stride = (channel & 1) * 4; 1776 1777 assert(urb_setup[location] != -1); 1778 1779 return brw_vec1_grf(regnr, stride); 1780} 1781 1782/** Emits the interpolation for the varying inputs. */ 1783void 1784fs_visitor::emit_interpolation_setup_gen4() 1785{ 1786 this->current_annotation = "compute pixel centers"; 1787 this->pixel_x = fs_reg(this, glsl_type::uint_type); 1788 this->pixel_y = fs_reg(this, glsl_type::uint_type); 1789 this->pixel_x.type = BRW_REGISTER_TYPE_UW; 1790 this->pixel_y.type = BRW_REGISTER_TYPE_UW; 1791 1792 emit(FS_OPCODE_PIXEL_X, this->pixel_x); 1793 emit(FS_OPCODE_PIXEL_Y, this->pixel_y); 1794 1795 this->current_annotation = "compute pixel deltas from v0"; 1796 if (brw->has_pln) { 1797 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] = 1798 fs_reg(this, glsl_type::vec2_type); 1799 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] = 1800 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC]; 1801 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].reg_offset++; 1802 } else { 1803 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] = 1804 fs_reg(this, glsl_type::float_type); 1805 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] = 1806 fs_reg(this, glsl_type::float_type); 1807 } 1808 emit(BRW_OPCODE_ADD, this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC], 1809 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))); 1810 emit(BRW_OPCODE_ADD, this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC], 1811 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))); 1812 1813 this->current_annotation = "compute pos.w and 1/pos.w"; 1814 /* Compute wpos.w. It's always in our setup, since it's needed to 1815 * interpolate the other attributes. 1816 */ 1817 this->wpos_w = fs_reg(this, glsl_type::float_type); 1818 emit(FS_OPCODE_LINTERP, wpos_w, 1819 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC], 1820 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC], 1821 interp_reg(FRAG_ATTRIB_WPOS, 3)); 1822 /* Compute the pixel 1/W value from wpos.w. */ 1823 this->pixel_w = fs_reg(this, glsl_type::float_type); 1824 emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w); 1825 this->current_annotation = NULL; 1826} 1827 1828/** Emits the interpolation for the varying inputs. */ 1829void 1830fs_visitor::emit_interpolation_setup_gen6() 1831{ 1832 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); 1833 1834 /* If the pixel centers end up used, the setup is the same as for gen4. */ 1835 this->current_annotation = "compute pixel centers"; 1836 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type); 1837 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type); 1838 int_pixel_x.type = BRW_REGISTER_TYPE_UW; 1839 int_pixel_y.type = BRW_REGISTER_TYPE_UW; 1840 emit(BRW_OPCODE_ADD, 1841 int_pixel_x, 1842 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), 1843 fs_reg(brw_imm_v(0x10101010))); 1844 emit(BRW_OPCODE_ADD, 1845 int_pixel_y, 1846 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), 1847 fs_reg(brw_imm_v(0x11001100))); 1848 1849 /* As of gen6, we can no longer mix float and int sources. We have 1850 * to turn the integer pixel centers into floats for their actual 1851 * use. 1852 */ 1853 this->pixel_x = fs_reg(this, glsl_type::float_type); 1854 this->pixel_y = fs_reg(this, glsl_type::float_type); 1855 emit(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x); 1856 emit(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y); 1857 1858 this->current_annotation = "compute pos.w"; 1859 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0)); 1860 this->wpos_w = fs_reg(this, glsl_type::float_type); 1861 emit_math(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w); 1862 1863 for (int i = 0; i < BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT; ++i) { 1864 uint8_t reg = c->barycentric_coord_reg[i]; 1865 this->delta_x[i] = fs_reg(brw_vec8_grf(reg, 0)); 1866 this->delta_y[i] = fs_reg(brw_vec8_grf(reg + 1, 0)); 1867 } 1868 1869 this->current_annotation = NULL; 1870} 1871 1872void 1873fs_visitor::emit_color_write(int target, int index, int first_color_mrf) 1874{ 1875 int reg_width = c->dispatch_width / 8; 1876 fs_inst *inst; 1877 fs_reg color = outputs[target]; 1878 fs_reg mrf; 1879 1880 /* If there's no color data to be written, skip it. */ 1881 if (color.file == BAD_FILE) 1882 return; 1883 1884 color.reg_offset += index; 1885 1886 if (c->dispatch_width == 8 || intel->gen >= 6) { 1887 /* SIMD8 write looks like: 1888 * m + 0: r0 1889 * m + 1: r1 1890 * m + 2: g0 1891 * m + 3: g1 1892 * 1893 * gen6 SIMD16 DP write looks like: 1894 * m + 0: r0 1895 * m + 1: r1 1896 * m + 2: g0 1897 * m + 3: g1 1898 * m + 4: b0 1899 * m + 5: b1 1900 * m + 6: a0 1901 * m + 7: a1 1902 */ 1903 inst = emit(BRW_OPCODE_MOV, 1904 fs_reg(MRF, first_color_mrf + index * reg_width, color.type), 1905 color); 1906 inst->saturate = c->key.clamp_fragment_color; 1907 } else { 1908 /* pre-gen6 SIMD16 single source DP write looks like: 1909 * m + 0: r0 1910 * m + 1: g0 1911 * m + 2: b0 1912 * m + 3: a0 1913 * m + 4: r1 1914 * m + 5: g1 1915 * m + 6: b1 1916 * m + 7: a1 1917 */ 1918 if (brw->has_compr4) { 1919 /* By setting the high bit of the MRF register number, we 1920 * indicate that we want COMPR4 mode - instead of doing the 1921 * usual destination + 1 for the second half we get 1922 * destination + 4. 1923 */ 1924 inst = emit(BRW_OPCODE_MOV, 1925 fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index, 1926 color.type), 1927 color); 1928 inst->saturate = c->key.clamp_fragment_color; 1929 } else { 1930 push_force_uncompressed(); 1931 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index, 1932 color.type), 1933 color); 1934 inst->saturate = c->key.clamp_fragment_color; 1935 pop_force_uncompressed(); 1936 1937 push_force_sechalf(); 1938 color.sechalf = true; 1939 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index + 4, 1940 color.type), 1941 color); 1942 inst->saturate = c->key.clamp_fragment_color; 1943 pop_force_sechalf(); 1944 color.sechalf = false; 1945 } 1946 } 1947} 1948 1949void 1950fs_visitor::emit_fb_writes() 1951{ 1952 this->current_annotation = "FB write header"; 1953 bool header_present = true; 1954 int base_mrf = 2; 1955 int nr = base_mrf; 1956 int reg_width = c->dispatch_width / 8; 1957 1958 if (intel->gen >= 6 && 1959 !this->kill_emitted && 1960 c->key.nr_color_regions == 1) { 1961 header_present = false; 1962 } 1963 1964 if (header_present) { 1965 /* m2, m3 header */ 1966 nr += 2; 1967 } 1968 1969 if (c->aa_dest_stencil_reg) { 1970 push_force_uncompressed(); 1971 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++), 1972 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))); 1973 pop_force_uncompressed(); 1974 } 1975 1976 /* Reserve space for color. It'll be filled in per MRT below. */ 1977 int color_mrf = nr; 1978 nr += 4 * reg_width; 1979 1980 if (c->source_depth_to_render_target) { 1981 if (intel->gen == 6 && c->dispatch_width == 16) { 1982 /* For outputting oDepth on gen6, SIMD8 writes have to be 1983 * used. This would require 8-wide moves of each half to 1984 * message regs, kind of like pre-gen5 SIMD16 FB writes. 1985 * Just bail on doing so for now. 1986 */ 1987 fail("Missing support for simd16 depth writes on gen6\n"); 1988 } 1989 1990 if (c->computes_depth) { 1991 /* Hand over gl_FragDepth. */ 1992 assert(this->frag_depth); 1993 fs_reg depth = *(variable_storage(this->frag_depth)); 1994 1995 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), depth); 1996 } else { 1997 /* Pass through the payload depth. */ 1998 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1999 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))); 2000 } 2001 nr += reg_width; 2002 } 2003 2004 if (c->dest_depth_reg) { 2005 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 2006 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))); 2007 nr += reg_width; 2008 } 2009 2010 for (int target = 0; target < c->key.nr_color_regions; target++) { 2011 this->current_annotation = ralloc_asprintf(this->mem_ctx, 2012 "FB write target %d", 2013 target); 2014 for (int i = 0; i < 4; i++) 2015 emit_color_write(target, i, color_mrf); 2016 2017 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 2018 inst->target = target; 2019 inst->base_mrf = base_mrf; 2020 inst->mlen = nr - base_mrf; 2021 if (target == c->key.nr_color_regions - 1) 2022 inst->eot = true; 2023 inst->header_present = header_present; 2024 } 2025 2026 if (c->key.nr_color_regions == 0) { 2027 if (c->key.alpha_test) { 2028 /* If the alpha test is enabled but there's no color buffer, 2029 * we still need to send alpha out the pipeline to our null 2030 * renderbuffer. 2031 */ 2032 emit_color_write(0, 3, color_mrf); 2033 } 2034 2035 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 2036 inst->base_mrf = base_mrf; 2037 inst->mlen = nr - base_mrf; 2038 inst->eot = true; 2039 inst->header_present = header_present; 2040 } 2041 2042 this->current_annotation = NULL; 2043} 2044 2045void 2046fs_visitor::resolve_ud_negate(fs_reg *reg) 2047{ 2048 if (reg->type != BRW_REGISTER_TYPE_UD || 2049 !reg->negate) 2050 return; 2051 2052 fs_reg temp = fs_reg(this, glsl_type::uint_type); 2053 emit(BRW_OPCODE_MOV, temp, *reg); 2054 *reg = temp; 2055} 2056