brw_fs_visitor.cpp revision 7de6e749df90a214d1547956dd66cfec6edcb446
1/* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24/** @file brw_fs_visitor.cpp 25 * 26 * This file supports generating the FS LIR from the GLSL IR. The LIR 27 * makes it easier to do backend-specific optimizations than doing so 28 * in the GLSL IR or in the native code. 29 */ 30extern "C" { 31 32#include <sys/types.h> 33 34#include "main/macros.h" 35#include "main/shaderobj.h" 36#include "main/uniforms.h" 37#include "program/prog_parameter.h" 38#include "program/prog_print.h" 39#include "program/prog_optimize.h" 40#include "program/register_allocate.h" 41#include "program/sampler.h" 42#include "program/hash_table.h" 43#include "brw_context.h" 44#include "brw_eu.h" 45#include "brw_wm.h" 46} 47#include "brw_shader.h" 48#include "brw_fs.h" 49#include "glsl/glsl_types.h" 50#include "glsl/ir_optimization.h" 51#include "glsl/ir_print_visitor.h" 52 53void 54fs_visitor::visit(ir_variable *ir) 55{ 56 fs_reg *reg = NULL; 57 58 if (variable_storage(ir)) 59 return; 60 61 if (strcmp(ir->name, "gl_FragColor") == 0) { 62 this->frag_color = ir; 63 } else if (strcmp(ir->name, "gl_FragData") == 0) { 64 this->frag_data = ir; 65 } else if (strcmp(ir->name, "gl_FragDepth") == 0) { 66 this->frag_depth = ir; 67 } 68 69 if (ir->mode == ir_var_in) { 70 if (!strcmp(ir->name, "gl_FragCoord")) { 71 reg = emit_fragcoord_interpolation(ir); 72 } else if (!strcmp(ir->name, "gl_FrontFacing")) { 73 reg = emit_frontfacing_interpolation(ir); 74 } else { 75 reg = emit_general_interpolation(ir); 76 } 77 assert(reg); 78 hash_table_insert(this->variable_ht, reg, ir); 79 return; 80 } 81 82 if (ir->mode == ir_var_uniform) { 83 int param_index = c->prog_data.nr_params; 84 85 if (c->dispatch_width == 16) { 86 if (!variable_storage(ir)) { 87 fail("Failed to find uniform '%s' in 16-wide\n", ir->name); 88 } 89 return; 90 } 91 92 if (!strncmp(ir->name, "gl_", 3)) { 93 setup_builtin_uniform_values(ir); 94 } else { 95 setup_uniform_values(ir->location, ir->type); 96 } 97 98 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index); 99 reg->type = brw_type_for_base_type(ir->type); 100 } 101 102 if (!reg) 103 reg = new(this->mem_ctx) fs_reg(this, ir->type); 104 105 hash_table_insert(this->variable_ht, reg, ir); 106} 107 108void 109fs_visitor::visit(ir_dereference_variable *ir) 110{ 111 fs_reg *reg = variable_storage(ir->var); 112 this->result = *reg; 113} 114 115void 116fs_visitor::visit(ir_dereference_record *ir) 117{ 118 const glsl_type *struct_type = ir->record->type; 119 120 ir->record->accept(this); 121 122 unsigned int offset = 0; 123 for (unsigned int i = 0; i < struct_type->length; i++) { 124 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0) 125 break; 126 offset += type_size(struct_type->fields.structure[i].type); 127 } 128 this->result.reg_offset += offset; 129 this->result.type = brw_type_for_base_type(ir->type); 130} 131 132void 133fs_visitor::visit(ir_dereference_array *ir) 134{ 135 ir_constant *index; 136 int element_size; 137 138 ir->array->accept(this); 139 index = ir->array_index->as_constant(); 140 141 element_size = type_size(ir->type); 142 this->result.type = brw_type_for_base_type(ir->type); 143 144 if (index) { 145 assert(this->result.file == UNIFORM || this->result.file == GRF); 146 this->result.reg_offset += index->value.i[0] * element_size; 147 } else { 148 assert(!"FINISHME: non-constant array element"); 149 } 150} 151 152/* Instruction selection: Produce a MOV.sat instead of 153 * MIN(MAX(val, 0), 1) when possible. 154 */ 155bool 156fs_visitor::try_emit_saturate(ir_expression *ir) 157{ 158 ir_rvalue *sat_val = ir->as_rvalue_to_saturate(); 159 160 if (!sat_val) 161 return false; 162 163 sat_val->accept(this); 164 fs_reg src = this->result; 165 166 this->result = fs_reg(this, ir->type); 167 fs_inst *inst = emit(BRW_OPCODE_MOV, this->result, src); 168 inst->saturate = true; 169 170 return true; 171} 172 173void 174fs_visitor::visit(ir_expression *ir) 175{ 176 unsigned int operand; 177 fs_reg op[2], temp; 178 fs_inst *inst; 179 180 assert(ir->get_num_operands() <= 2); 181 182 if (try_emit_saturate(ir)) 183 return; 184 185 for (operand = 0; operand < ir->get_num_operands(); operand++) { 186 ir->operands[operand]->accept(this); 187 if (this->result.file == BAD_FILE) { 188 ir_print_visitor v; 189 fail("Failed to get tree for expression operand:\n"); 190 ir->operands[operand]->accept(&v); 191 } 192 op[operand] = this->result; 193 194 /* Matrix expression operands should have been broken down to vector 195 * operations already. 196 */ 197 assert(!ir->operands[operand]->type->is_matrix()); 198 /* And then those vector operands should have been broken down to scalar. 199 */ 200 assert(!ir->operands[operand]->type->is_vector()); 201 } 202 203 /* Storage for our result. If our result goes into an assignment, it will 204 * just get copy-propagated out, so no worries. 205 */ 206 this->result = fs_reg(this, ir->type); 207 208 switch (ir->operation) { 209 case ir_unop_logic_not: 210 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is 211 * ones complement of the whole register, not just bit 0. 212 */ 213 emit(BRW_OPCODE_XOR, this->result, op[0], fs_reg(1)); 214 break; 215 case ir_unop_neg: 216 op[0].negate = !op[0].negate; 217 this->result = op[0]; 218 break; 219 case ir_unop_abs: 220 op[0].abs = true; 221 op[0].negate = false; 222 this->result = op[0]; 223 break; 224 case ir_unop_sign: 225 temp = fs_reg(this, ir->type); 226 227 emit(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)); 228 229 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 230 inst->conditional_mod = BRW_CONDITIONAL_G; 231 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)); 232 inst->predicated = true; 233 234 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 235 inst->conditional_mod = BRW_CONDITIONAL_L; 236 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)); 237 inst->predicated = true; 238 239 break; 240 case ir_unop_rcp: 241 emit_math(SHADER_OPCODE_RCP, this->result, op[0]); 242 break; 243 244 case ir_unop_exp2: 245 emit_math(SHADER_OPCODE_EXP2, this->result, op[0]); 246 break; 247 case ir_unop_log2: 248 emit_math(SHADER_OPCODE_LOG2, this->result, op[0]); 249 break; 250 case ir_unop_exp: 251 case ir_unop_log: 252 assert(!"not reached: should be handled by ir_explog_to_explog2"); 253 break; 254 case ir_unop_sin: 255 case ir_unop_sin_reduced: 256 emit_math(SHADER_OPCODE_SIN, this->result, op[0]); 257 break; 258 case ir_unop_cos: 259 case ir_unop_cos_reduced: 260 emit_math(SHADER_OPCODE_COS, this->result, op[0]); 261 break; 262 263 case ir_unop_dFdx: 264 emit(FS_OPCODE_DDX, this->result, op[0]); 265 break; 266 case ir_unop_dFdy: 267 emit(FS_OPCODE_DDY, this->result, op[0]); 268 break; 269 270 case ir_binop_add: 271 emit(BRW_OPCODE_ADD, this->result, op[0], op[1]); 272 break; 273 case ir_binop_sub: 274 assert(!"not reached: should be handled by ir_sub_to_add_neg"); 275 break; 276 277 case ir_binop_mul: 278 if (ir->type->is_integer()) { 279 /* For integer multiplication, the MUL uses the low 16 bits 280 * of one of the operands (src0 on gen6, src1 on gen7). The 281 * MACH accumulates in the contribution of the upper 16 bits 282 * of that operand. 283 * 284 * FINISHME: Emit just the MUL if we know an operand is small 285 * enough. 286 */ 287 struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_D); 288 289 emit(BRW_OPCODE_MUL, acc, op[0], op[1]); 290 emit(BRW_OPCODE_MACH, reg_null_d, op[0], op[1]); 291 emit(BRW_OPCODE_MOV, this->result, fs_reg(acc)); 292 } else { 293 emit(BRW_OPCODE_MUL, this->result, op[0], op[1]); 294 } 295 break; 296 case ir_binop_div: 297 assert(!"not reached: should be handled by ir_div_to_mul_rcp"); 298 break; 299 case ir_binop_mod: 300 assert(!"ir_binop_mod should have been converted to b * fract(a/b)"); 301 break; 302 303 case ir_binop_less: 304 case ir_binop_greater: 305 case ir_binop_lequal: 306 case ir_binop_gequal: 307 case ir_binop_equal: 308 case ir_binop_all_equal: 309 case ir_binop_nequal: 310 case ir_binop_any_nequal: 311 temp = this->result; 312 /* original gen4 does implicit conversion before comparison. */ 313 if (intel->gen < 5) 314 temp.type = op[0].type; 315 316 inst = emit(BRW_OPCODE_CMP, temp, op[0], op[1]); 317 inst->conditional_mod = brw_conditional_for_comparison(ir->operation); 318 emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)); 319 break; 320 321 case ir_binop_logic_xor: 322 emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 323 break; 324 325 case ir_binop_logic_or: 326 emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 327 break; 328 329 case ir_binop_logic_and: 330 emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 331 break; 332 333 case ir_binop_dot: 334 case ir_unop_any: 335 assert(!"not reached: should be handled by brw_fs_channel_expressions"); 336 break; 337 338 case ir_unop_noise: 339 assert(!"not reached: should be handled by lower_noise"); 340 break; 341 342 case ir_quadop_vector: 343 assert(!"not reached: should be handled by lower_quadop_vector"); 344 break; 345 346 case ir_unop_sqrt: 347 emit_math(SHADER_OPCODE_SQRT, this->result, op[0]); 348 break; 349 350 case ir_unop_rsq: 351 emit_math(SHADER_OPCODE_RSQ, this->result, op[0]); 352 break; 353 354 case ir_unop_i2u: 355 op[0].type = BRW_REGISTER_TYPE_UD; 356 this->result = op[0]; 357 break; 358 case ir_unop_u2i: 359 op[0].type = BRW_REGISTER_TYPE_D; 360 this->result = op[0]; 361 break; 362 case ir_unop_i2f: 363 case ir_unop_u2f: 364 case ir_unop_b2f: 365 case ir_unop_b2i: 366 case ir_unop_f2i: 367 emit(BRW_OPCODE_MOV, this->result, op[0]); 368 break; 369 case ir_unop_f2b: 370 case ir_unop_i2b: 371 temp = this->result; 372 /* original gen4 does implicit conversion before comparison. */ 373 if (intel->gen < 5) 374 temp.type = op[0].type; 375 376 inst = emit(BRW_OPCODE_CMP, temp, op[0], fs_reg(0.0f)); 377 inst->conditional_mod = BRW_CONDITIONAL_NZ; 378 inst = emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(1)); 379 break; 380 381 case ir_unop_trunc: 382 emit(BRW_OPCODE_RNDZ, this->result, op[0]); 383 break; 384 case ir_unop_ceil: 385 op[0].negate = !op[0].negate; 386 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 387 this->result.negate = true; 388 break; 389 case ir_unop_floor: 390 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 391 break; 392 case ir_unop_fract: 393 inst = emit(BRW_OPCODE_FRC, this->result, op[0]); 394 break; 395 case ir_unop_round_even: 396 emit(BRW_OPCODE_RNDE, this->result, op[0]); 397 break; 398 399 case ir_binop_min: 400 if (intel->gen >= 6) { 401 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 402 inst->conditional_mod = BRW_CONDITIONAL_L; 403 } else { 404 /* Unalias the destination */ 405 this->result = fs_reg(this, ir->type); 406 407 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 408 inst->conditional_mod = BRW_CONDITIONAL_L; 409 410 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 411 inst->predicated = true; 412 } 413 break; 414 case ir_binop_max: 415 if (intel->gen >= 6) { 416 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 417 inst->conditional_mod = BRW_CONDITIONAL_GE; 418 } else { 419 /* Unalias the destination */ 420 this->result = fs_reg(this, ir->type); 421 422 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 423 inst->conditional_mod = BRW_CONDITIONAL_G; 424 425 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 426 inst->predicated = true; 427 } 428 break; 429 430 case ir_binop_pow: 431 emit_math(SHADER_OPCODE_POW, this->result, op[0], op[1]); 432 break; 433 434 case ir_unop_bit_not: 435 inst = emit(BRW_OPCODE_NOT, this->result, op[0]); 436 break; 437 case ir_binop_bit_and: 438 inst = emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 439 break; 440 case ir_binop_bit_xor: 441 inst = emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 442 break; 443 case ir_binop_bit_or: 444 inst = emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 445 break; 446 447 case ir_binop_lshift: 448 inst = emit(BRW_OPCODE_SHL, this->result, op[0], op[1]); 449 break; 450 451 case ir_binop_rshift: 452 if (ir->type->base_type == GLSL_TYPE_INT) 453 inst = emit(BRW_OPCODE_ASR, this->result, op[0], op[1]); 454 else 455 inst = emit(BRW_OPCODE_SHR, this->result, op[0], op[1]); 456 break; 457 } 458} 459 460void 461fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r, 462 const glsl_type *type, bool predicated) 463{ 464 switch (type->base_type) { 465 case GLSL_TYPE_FLOAT: 466 case GLSL_TYPE_UINT: 467 case GLSL_TYPE_INT: 468 case GLSL_TYPE_BOOL: 469 for (unsigned int i = 0; i < type->components(); i++) { 470 l.type = brw_type_for_base_type(type); 471 r.type = brw_type_for_base_type(type); 472 473 if (predicated || !l.equals(&r)) { 474 fs_inst *inst = emit(BRW_OPCODE_MOV, l, r); 475 inst->predicated = predicated; 476 } 477 478 l.reg_offset++; 479 r.reg_offset++; 480 } 481 break; 482 case GLSL_TYPE_ARRAY: 483 for (unsigned int i = 0; i < type->length; i++) { 484 emit_assignment_writes(l, r, type->fields.array, predicated); 485 } 486 break; 487 488 case GLSL_TYPE_STRUCT: 489 for (unsigned int i = 0; i < type->length; i++) { 490 emit_assignment_writes(l, r, type->fields.structure[i].type, 491 predicated); 492 } 493 break; 494 495 case GLSL_TYPE_SAMPLER: 496 break; 497 498 default: 499 assert(!"not reached"); 500 break; 501 } 502} 503 504/* If the RHS processing resulted in an instruction generating a 505 * temporary value, and it would be easy to rewrite the instruction to 506 * generate its result right into the LHS instead, do so. This ends 507 * up reliably removing instructions where it can be tricky to do so 508 * later without real UD chain information. 509 */ 510bool 511fs_visitor::try_rewrite_rhs_to_dst(ir_assignment *ir, 512 fs_reg dst, 513 fs_reg src, 514 fs_inst *pre_rhs_inst, 515 fs_inst *last_rhs_inst) 516{ 517 if (pre_rhs_inst == last_rhs_inst) 518 return false; /* No instructions generated to work with. */ 519 520 /* Only attempt if we're doing a direct assignment. */ 521 if (ir->condition || 522 !(ir->lhs->type->is_scalar() || 523 (ir->lhs->type->is_vector() && 524 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1))) 525 return false; 526 527 /* Make sure the last instruction generated our source reg. */ 528 if (last_rhs_inst->predicated || 529 last_rhs_inst->force_uncompressed || 530 last_rhs_inst->force_sechalf || 531 !src.equals(&last_rhs_inst->dst)) 532 return false; 533 534 /* Success! Rewrite the instruction. */ 535 last_rhs_inst->dst = dst; 536 537 return true; 538} 539 540void 541fs_visitor::visit(ir_assignment *ir) 542{ 543 fs_reg l, r; 544 fs_inst *inst; 545 546 /* FINISHME: arrays on the lhs */ 547 ir->lhs->accept(this); 548 l = this->result; 549 550 fs_inst *pre_rhs_inst = (fs_inst *) this->instructions.get_tail(); 551 552 ir->rhs->accept(this); 553 r = this->result; 554 555 fs_inst *last_rhs_inst = (fs_inst *) this->instructions.get_tail(); 556 557 assert(l.file != BAD_FILE); 558 assert(r.file != BAD_FILE); 559 560 if (try_rewrite_rhs_to_dst(ir, l, r, pre_rhs_inst, last_rhs_inst)) 561 return; 562 563 if (ir->condition) { 564 emit_bool_to_cond_code(ir->condition); 565 } 566 567 if (ir->lhs->type->is_scalar() || 568 ir->lhs->type->is_vector()) { 569 for (int i = 0; i < ir->lhs->type->vector_elements; i++) { 570 if (ir->write_mask & (1 << i)) { 571 inst = emit(BRW_OPCODE_MOV, l, r); 572 if (ir->condition) 573 inst->predicated = true; 574 r.reg_offset++; 575 } 576 l.reg_offset++; 577 } 578 } else { 579 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL); 580 } 581} 582 583fs_inst * 584fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate, 585 int sampler) 586{ 587 int mlen; 588 int base_mrf = 1; 589 bool simd16 = false; 590 fs_reg orig_dst; 591 592 /* g0 header. */ 593 mlen = 1; 594 595 if (ir->shadow_comparitor && ir->op != ir_txd) { 596 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 597 fs_inst *inst = emit(BRW_OPCODE_MOV, 598 fs_reg(MRF, base_mrf + mlen + i), coordinate); 599 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 600 inst->saturate = true; 601 602 coordinate.reg_offset++; 603 } 604 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 605 mlen += 3; 606 607 if (ir->op == ir_tex) { 608 /* There's no plain shadow compare message, so we use shadow 609 * compare with a bias of 0.0. 610 */ 611 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)); 612 mlen++; 613 } else if (ir->op == ir_txb) { 614 ir->lod_info.bias->accept(this); 615 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 616 mlen++; 617 } else { 618 assert(ir->op == ir_txl); 619 ir->lod_info.lod->accept(this); 620 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 621 mlen++; 622 } 623 624 ir->shadow_comparitor->accept(this); 625 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 626 mlen++; 627 } else if (ir->op == ir_tex) { 628 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 629 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), 630 coordinate); 631 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 632 inst->saturate = true; 633 coordinate.reg_offset++; 634 } 635 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 636 mlen += 3; 637 } else if (ir->op == ir_txd) { 638 ir->lod_info.grad.dPdx->accept(this); 639 fs_reg dPdx = this->result; 640 641 ir->lod_info.grad.dPdy->accept(this); 642 fs_reg dPdy = this->result; 643 644 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 645 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); 646 coordinate.reg_offset++; 647 } 648 /* the slots for u and v are always present, but r is optional */ 649 mlen += MAX2(ir->coordinate->type->vector_elements, 2); 650 651 /* P = u, v, r 652 * dPdx = dudx, dvdx, drdx 653 * dPdy = dudy, dvdy, drdy 654 * 655 * 1-arg: Does not exist. 656 * 657 * 2-arg: dudx dvdx dudy dvdy 658 * dPdx.x dPdx.y dPdy.x dPdy.y 659 * m4 m5 m6 m7 660 * 661 * 3-arg: dudx dvdx drdx dudy dvdy drdy 662 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z 663 * m5 m6 m7 m8 m9 m10 664 */ 665 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 666 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 667 dPdx.reg_offset++; 668 } 669 mlen += MAX2(ir->lod_info.grad.dPdx->type->vector_elements, 2); 670 671 for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) { 672 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 673 dPdy.reg_offset++; 674 } 675 mlen += MAX2(ir->lod_info.grad.dPdy->type->vector_elements, 2); 676 } else if (ir->op == ir_txs) { 677 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */ 678 simd16 = true; 679 ir->lod_info.lod->accept(this); 680 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 681 mlen += 2; 682 } else { 683 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod 684 * instructions. We'll need to do SIMD16 here. 685 */ 686 simd16 = true; 687 assert(ir->op == ir_txb || ir->op == ir_txl || ir->op == ir_txf); 688 689 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 690 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, 691 base_mrf + mlen + i * 2, 692 coordinate.type), 693 coordinate); 694 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 695 inst->saturate = true; 696 coordinate.reg_offset++; 697 } 698 699 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to 700 * be necessary for TXF (ld), but seems wise to do for all messages. 701 */ 702 for (int i = ir->coordinate->type->vector_elements; i < 3; i++) { 703 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i * 2), fs_reg(0.0f)); 704 } 705 706 /* lod/bias appears after u/v/r. */ 707 mlen += 6; 708 709 if (ir->op == ir_txb) { 710 ir->lod_info.bias->accept(this); 711 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 712 mlen++; 713 } else { 714 ir->lod_info.lod->accept(this); 715 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, this->result.type), 716 this->result); 717 mlen++; 718 } 719 720 /* The unused upper half. */ 721 mlen++; 722 } 723 724 if (simd16) { 725 /* Now, since we're doing simd16, the return is 2 interleaved 726 * vec4s where the odd-indexed ones are junk. We'll need to move 727 * this weirdness around to the expected layout. 728 */ 729 orig_dst = dst; 730 const glsl_type *vec_type = 731 glsl_type::get_instance(ir->type->base_type, 4, 1); 732 dst = fs_reg(this, glsl_type::get_array_instance(vec_type, 2)); 733 dst.type = intel->is_g4x ? brw_type_for_base_type(ir->type) 734 : BRW_REGISTER_TYPE_F; 735 } 736 737 fs_inst *inst = NULL; 738 switch (ir->op) { 739 case ir_tex: 740 inst = emit(FS_OPCODE_TEX, dst); 741 break; 742 case ir_txb: 743 inst = emit(FS_OPCODE_TXB, dst); 744 break; 745 case ir_txl: 746 inst = emit(FS_OPCODE_TXL, dst); 747 break; 748 case ir_txd: 749 inst = emit(FS_OPCODE_TXD, dst); 750 break; 751 case ir_txs: 752 inst = emit(FS_OPCODE_TXS, dst); 753 break; 754 case ir_txf: 755 inst = emit(FS_OPCODE_TXF, dst); 756 break; 757 } 758 inst->base_mrf = base_mrf; 759 inst->mlen = mlen; 760 inst->header_present = true; 761 762 if (simd16) { 763 for (int i = 0; i < 4; i++) { 764 emit(BRW_OPCODE_MOV, orig_dst, dst); 765 orig_dst.reg_offset++; 766 dst.reg_offset += 2; 767 } 768 } 769 770 return inst; 771} 772 773/* gen5's sampler has slots for u, v, r, array index, then optional 774 * parameters like shadow comparitor or LOD bias. If optional 775 * parameters aren't present, those base slots are optional and don't 776 * need to be included in the message. 777 * 778 * We don't fill in the unnecessary slots regardless, which may look 779 * surprising in the disassembly. 780 */ 781fs_inst * 782fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate, 783 int sampler) 784{ 785 int mlen = 0; 786 int base_mrf = 2; 787 int reg_width = c->dispatch_width / 8; 788 bool header_present = false; 789 const int vector_elements = 790 ir->coordinate ? ir->coordinate->type->vector_elements : 0; 791 792 if (ir->offset) { 793 /* The offsets set up by the ir_texture visitor are in the 794 * m1 header, so we can't go headerless. 795 */ 796 header_present = true; 797 mlen++; 798 base_mrf--; 799 } 800 801 for (int i = 0; i < vector_elements; i++) { 802 fs_inst *inst = emit(BRW_OPCODE_MOV, 803 fs_reg(MRF, base_mrf + mlen + i * reg_width, 804 coordinate.type), 805 coordinate); 806 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 807 inst->saturate = true; 808 coordinate.reg_offset++; 809 } 810 mlen += vector_elements * reg_width; 811 812 if (ir->shadow_comparitor && ir->op != ir_txd) { 813 mlen = MAX2(mlen, header_present + 4 * reg_width); 814 815 ir->shadow_comparitor->accept(this); 816 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 817 mlen += reg_width; 818 } 819 820 fs_inst *inst = NULL; 821 switch (ir->op) { 822 case ir_tex: 823 inst = emit(FS_OPCODE_TEX, dst); 824 break; 825 case ir_txb: 826 ir->lod_info.bias->accept(this); 827 mlen = MAX2(mlen, header_present + 4 * reg_width); 828 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 829 mlen += reg_width; 830 831 inst = emit(FS_OPCODE_TXB, dst); 832 833 break; 834 case ir_txl: 835 ir->lod_info.lod->accept(this); 836 mlen = MAX2(mlen, header_present + 4 * reg_width); 837 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 838 mlen += reg_width; 839 840 inst = emit(FS_OPCODE_TXL, dst); 841 break; 842 case ir_txd: { 843 ir->lod_info.grad.dPdx->accept(this); 844 fs_reg dPdx = this->result; 845 846 ir->lod_info.grad.dPdy->accept(this); 847 fs_reg dPdy = this->result; 848 849 mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */ 850 851 /** 852 * P = u, v, r 853 * dPdx = dudx, dvdx, drdx 854 * dPdy = dudy, dvdy, drdy 855 * 856 * Load up these values: 857 * - dudx dudy dvdx dvdy drdx drdy 858 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z 859 */ 860 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 861 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 862 dPdx.reg_offset++; 863 mlen += reg_width; 864 865 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 866 dPdy.reg_offset++; 867 mlen += reg_width; 868 } 869 870 inst = emit(FS_OPCODE_TXD, dst); 871 break; 872 } 873 case ir_txs: 874 ir->lod_info.lod->accept(this); 875 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 876 mlen += reg_width; 877 inst = emit(FS_OPCODE_TXS, dst); 878 break; 879 case ir_txf: 880 mlen = header_present + 4 * reg_width; 881 882 ir->lod_info.lod->accept(this); 883 emit(BRW_OPCODE_MOV, 884 fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), 885 this->result); 886 inst = emit(FS_OPCODE_TXF, dst); 887 break; 888 } 889 inst->base_mrf = base_mrf; 890 inst->mlen = mlen; 891 inst->header_present = header_present; 892 893 if (mlen > 11) { 894 fail("Message length >11 disallowed by hardware\n"); 895 } 896 897 return inst; 898} 899 900fs_inst * 901fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate, 902 int sampler) 903{ 904 int mlen = 0; 905 int base_mrf = 2; 906 int reg_width = c->dispatch_width / 8; 907 bool header_present = false; 908 909 if (ir->offset) { 910 /* The offsets set up by the ir_texture visitor are in the 911 * m1 header, so we can't go headerless. 912 */ 913 header_present = true; 914 mlen++; 915 base_mrf--; 916 } 917 918 if (ir->shadow_comparitor && ir->op != ir_txd) { 919 ir->shadow_comparitor->accept(this); 920 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 921 mlen += reg_width; 922 } 923 924 /* Set up the LOD info */ 925 switch (ir->op) { 926 case ir_tex: 927 break; 928 case ir_txb: 929 ir->lod_info.bias->accept(this); 930 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 931 mlen += reg_width; 932 break; 933 case ir_txl: 934 ir->lod_info.lod->accept(this); 935 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 936 mlen += reg_width; 937 break; 938 case ir_txd: { 939 if (c->dispatch_width == 16) 940 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode."); 941 942 ir->lod_info.grad.dPdx->accept(this); 943 fs_reg dPdx = this->result; 944 945 ir->lod_info.grad.dPdy->accept(this); 946 fs_reg dPdy = this->result; 947 948 /* Load dPdx and the coordinate together: 949 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z 950 */ 951 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 952 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 953 coordinate); 954 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 955 inst->saturate = true; 956 coordinate.reg_offset++; 957 mlen += reg_width; 958 959 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 960 dPdx.reg_offset++; 961 mlen += reg_width; 962 963 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 964 dPdy.reg_offset++; 965 mlen += reg_width; 966 } 967 break; 968 } 969 case ir_txs: 970 ir->lod_info.lod->accept(this); 971 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 972 mlen += reg_width; 973 break; 974 case ir_txf: 975 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */ 976 emit(BRW_OPCODE_MOV, 977 fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), coordinate); 978 coordinate.reg_offset++; 979 mlen += reg_width; 980 981 ir->lod_info.lod->accept(this); 982 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), this->result); 983 mlen += reg_width; 984 985 for (int i = 1; i < ir->coordinate->type->vector_elements; i++) { 986 emit(BRW_OPCODE_MOV, 987 fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), coordinate); 988 coordinate.reg_offset++; 989 mlen += reg_width; 990 } 991 break; 992 } 993 994 /* Set up the coordinate (except for cases where it was done above) */ 995 if (ir->op != ir_txd && ir->op != ir_txs && ir->op != ir_txf) { 996 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 997 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 998 coordinate); 999 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 1000 inst->saturate = true; 1001 coordinate.reg_offset++; 1002 mlen += reg_width; 1003 } 1004 } 1005 1006 /* Generate the SEND */ 1007 fs_inst *inst = NULL; 1008 switch (ir->op) { 1009 case ir_tex: inst = emit(FS_OPCODE_TEX, dst); break; 1010 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break; 1011 case ir_txl: inst = emit(FS_OPCODE_TXL, dst); break; 1012 case ir_txd: inst = emit(FS_OPCODE_TXD, dst); break; 1013 case ir_txf: inst = emit(FS_OPCODE_TXF, dst); break; 1014 case ir_txs: inst = emit(FS_OPCODE_TXS, dst); break; 1015 } 1016 inst->base_mrf = base_mrf; 1017 inst->mlen = mlen; 1018 inst->header_present = header_present; 1019 1020 if (mlen > 11) { 1021 fail("Message length >11 disallowed by hardware\n"); 1022 } 1023 1024 return inst; 1025} 1026 1027void 1028fs_visitor::visit(ir_texture *ir) 1029{ 1030 fs_inst *inst = NULL; 1031 1032 int sampler = _mesa_get_sampler_uniform_value(ir->sampler, prog, &fp->Base); 1033 sampler = fp->Base.SamplerUnits[sampler]; 1034 1035 /* Our hardware doesn't have a sample_d_c message, so shadow compares 1036 * for textureGrad/TXD need to be emulated with instructions. 1037 */ 1038 bool hw_compare_supported = ir->op != ir_txd; 1039 if (ir->shadow_comparitor && !hw_compare_supported) { 1040 assert(c->key.compare_funcs[sampler] != GL_NONE); 1041 /* No need to even sample for GL_ALWAYS or GL_NEVER...bail early */ 1042 if (c->key.compare_funcs[sampler] == GL_ALWAYS) 1043 return swizzle_result(ir, fs_reg(1.0f), sampler); 1044 else if (c->key.compare_funcs[sampler] == GL_NEVER) 1045 return swizzle_result(ir, fs_reg(0.0f), sampler); 1046 } 1047 1048 if (ir->coordinate) 1049 ir->coordinate->accept(this); 1050 fs_reg coordinate = this->result; 1051 1052 if (ir->offset != NULL) { 1053 ir_constant *offset = ir->offset->as_constant(); 1054 assert(offset != NULL); 1055 1056 signed char offsets[3]; 1057 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) 1058 offsets[i] = (signed char) offset->value.i[i]; 1059 1060 /* Combine all three offsets into a single unsigned dword: 1061 * 1062 * bits 11:8 - U Offset (X component) 1063 * bits 7:4 - V Offset (Y component) 1064 * bits 3:0 - R Offset (Z component) 1065 */ 1066 unsigned offset_bits = 0; 1067 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) { 1068 const unsigned shift = 4 * (2 - i); 1069 offset_bits |= (offsets[i] << shift) & (0xF << shift); 1070 } 1071 1072 /* Explicitly set up the message header by copying g0 to msg reg m1. */ 1073 emit(BRW_OPCODE_MOV, fs_reg(MRF, 1, BRW_REGISTER_TYPE_UD), 1074 fs_reg(GRF, 0, BRW_REGISTER_TYPE_UD)); 1075 1076 /* Then set the offset bits in DWord 2 of the message header. */ 1077 emit(BRW_OPCODE_MOV, 1078 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 1, 2), 1079 BRW_REGISTER_TYPE_UD)), 1080 fs_reg(brw_imm_uw(offset_bits))); 1081 } 1082 1083 /* Should be lowered by do_lower_texture_projection */ 1084 assert(!ir->projector); 1085 1086 /* The 965 requires the EU to do the normalization of GL rectangle 1087 * texture coordinates. We use the program parameter state 1088 * tracking to get the scaling factor. 1089 */ 1090 if (intel->gen < 6 && 1091 ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) { 1092 struct gl_program_parameter_list *params = c->fp->program.Base.Parameters; 1093 int tokens[STATE_LENGTH] = { 1094 STATE_INTERNAL, 1095 STATE_TEXRECT_SCALE, 1096 sampler, 1097 0, 1098 0 1099 }; 1100 1101 if (c->dispatch_width == 16) { 1102 fail("rectangle scale uniform setup not supported on 16-wide\n"); 1103 this->result = fs_reg(this, ir->type); 1104 return; 1105 } 1106 1107 c->prog_data.param_convert[c->prog_data.nr_params] = 1108 PARAM_NO_CONVERT; 1109 c->prog_data.param_convert[c->prog_data.nr_params + 1] = 1110 PARAM_NO_CONVERT; 1111 1112 fs_reg scale_x = fs_reg(UNIFORM, c->prog_data.nr_params); 1113 fs_reg scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1); 1114 GLuint index = _mesa_add_state_reference(params, 1115 (gl_state_index *)tokens); 1116 1117 this->param_index[c->prog_data.nr_params] = index; 1118 this->param_offset[c->prog_data.nr_params] = 0; 1119 c->prog_data.nr_params++; 1120 this->param_index[c->prog_data.nr_params] = index; 1121 this->param_offset[c->prog_data.nr_params] = 1; 1122 c->prog_data.nr_params++; 1123 1124 fs_reg dst = fs_reg(this, ir->coordinate->type); 1125 fs_reg src = coordinate; 1126 coordinate = dst; 1127 1128 emit(BRW_OPCODE_MUL, dst, src, scale_x); 1129 dst.reg_offset++; 1130 src.reg_offset++; 1131 emit(BRW_OPCODE_MUL, dst, src, scale_y); 1132 } 1133 1134 /* Writemasking doesn't eliminate channels on SIMD8 texture 1135 * samples, so don't worry about them. 1136 */ 1137 fs_reg dst = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 4, 1)); 1138 1139 if (intel->gen >= 7) { 1140 inst = emit_texture_gen7(ir, dst, coordinate, sampler); 1141 } else if (intel->gen >= 5) { 1142 inst = emit_texture_gen5(ir, dst, coordinate, sampler); 1143 } else { 1144 inst = emit_texture_gen4(ir, dst, coordinate, sampler); 1145 } 1146 1147 /* If there's an offset, we already set up m1. To avoid the implied move, 1148 * use the null register. Otherwise, we want an implied move from g0. 1149 */ 1150 if (ir->offset != NULL || !inst->header_present) 1151 inst->src[0] = reg_undef; 1152 else 1153 inst->src[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW)); 1154 1155 inst->sampler = sampler; 1156 1157 if (ir->shadow_comparitor) { 1158 if (hw_compare_supported) { 1159 inst->shadow_compare = true; 1160 } else { 1161 ir->shadow_comparitor->accept(this); 1162 fs_reg ref = this->result; 1163 1164 fs_reg value = dst; 1165 dst = fs_reg(this, glsl_type::vec4_type); 1166 1167 /* FINISHME: This needs to be done pre-filtering. */ 1168 1169 uint32_t conditional = 0; 1170 switch (c->key.compare_funcs[sampler]) { 1171 /* GL_ALWAYS and GL_NEVER were handled at the top of the function */ 1172 case GL_LESS: conditional = BRW_CONDITIONAL_L; break; 1173 case GL_GREATER: conditional = BRW_CONDITIONAL_G; break; 1174 case GL_LEQUAL: conditional = BRW_CONDITIONAL_LE; break; 1175 case GL_GEQUAL: conditional = BRW_CONDITIONAL_GE; break; 1176 case GL_EQUAL: conditional = BRW_CONDITIONAL_EQ; break; 1177 case GL_NOTEQUAL: conditional = BRW_CONDITIONAL_NEQ; break; 1178 default: assert(!"Should not get here: bad shadow compare function"); 1179 } 1180 1181 /* Use conditional moves to load 0 or 1 as the result */ 1182 this->current_annotation = "manual shadow comparison"; 1183 for (int i = 0; i < 4; i++) { 1184 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(0.0f)); 1185 1186 inst = emit(BRW_OPCODE_CMP, reg_null_f, ref, value); 1187 inst->conditional_mod = conditional; 1188 1189 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(1.0f)); 1190 inst->predicated = true; 1191 1192 dst.reg_offset++; 1193 value.reg_offset++; 1194 } 1195 dst.reg_offset = 0; 1196 } 1197 } 1198 1199 swizzle_result(ir, dst, sampler); 1200} 1201 1202/** 1203 * Swizzle the result of a texture result. This is necessary for 1204 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons. 1205 */ 1206void 1207fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler) 1208{ 1209 this->result = orig_val; 1210 1211 if (ir->type == glsl_type::float_type) { 1212 /* Ignore DEPTH_TEXTURE_MODE swizzling. */ 1213 assert(ir->sampler->type->sampler_shadow); 1214 } else if (c->key.tex_swizzles[sampler] != SWIZZLE_NOOP) { 1215 fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type); 1216 1217 for (int i = 0; i < 4; i++) { 1218 int swiz = GET_SWZ(c->key.tex_swizzles[sampler], i); 1219 fs_reg l = swizzled_result; 1220 l.reg_offset += i; 1221 1222 if (swiz == SWIZZLE_ZERO) { 1223 emit(BRW_OPCODE_MOV, l, fs_reg(0.0f)); 1224 } else if (swiz == SWIZZLE_ONE) { 1225 emit(BRW_OPCODE_MOV, l, fs_reg(1.0f)); 1226 } else { 1227 fs_reg r = orig_val; 1228 r.reg_offset += GET_SWZ(c->key.tex_swizzles[sampler], i); 1229 emit(BRW_OPCODE_MOV, l, r); 1230 } 1231 } 1232 this->result = swizzled_result; 1233 } 1234} 1235 1236void 1237fs_visitor::visit(ir_swizzle *ir) 1238{ 1239 ir->val->accept(this); 1240 fs_reg val = this->result; 1241 1242 if (ir->type->vector_elements == 1) { 1243 this->result.reg_offset += ir->mask.x; 1244 return; 1245 } 1246 1247 fs_reg result = fs_reg(this, ir->type); 1248 this->result = result; 1249 1250 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 1251 fs_reg channel = val; 1252 int swiz = 0; 1253 1254 switch (i) { 1255 case 0: 1256 swiz = ir->mask.x; 1257 break; 1258 case 1: 1259 swiz = ir->mask.y; 1260 break; 1261 case 2: 1262 swiz = ir->mask.z; 1263 break; 1264 case 3: 1265 swiz = ir->mask.w; 1266 break; 1267 } 1268 1269 channel.reg_offset += swiz; 1270 emit(BRW_OPCODE_MOV, result, channel); 1271 result.reg_offset++; 1272 } 1273} 1274 1275void 1276fs_visitor::visit(ir_discard *ir) 1277{ 1278 assert(ir->condition == NULL); /* FINISHME */ 1279 1280 emit(FS_OPCODE_DISCARD); 1281 kill_emitted = true; 1282} 1283 1284void 1285fs_visitor::visit(ir_constant *ir) 1286{ 1287 /* Set this->result to reg at the bottom of the function because some code 1288 * paths will cause this visitor to be applied to other fields. This will 1289 * cause the value stored in this->result to be modified. 1290 * 1291 * Make reg constant so that it doesn't get accidentally modified along the 1292 * way. Yes, I actually had this problem. :( 1293 */ 1294 const fs_reg reg(this, ir->type); 1295 fs_reg dst_reg = reg; 1296 1297 if (ir->type->is_array()) { 1298 const unsigned size = type_size(ir->type->fields.array); 1299 1300 for (unsigned i = 0; i < ir->type->length; i++) { 1301 ir->array_elements[i]->accept(this); 1302 fs_reg src_reg = this->result; 1303 1304 dst_reg.type = src_reg.type; 1305 for (unsigned j = 0; j < size; j++) { 1306 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1307 src_reg.reg_offset++; 1308 dst_reg.reg_offset++; 1309 } 1310 } 1311 } else if (ir->type->is_record()) { 1312 foreach_list(node, &ir->components) { 1313 ir_instruction *const field = (ir_instruction *) node; 1314 const unsigned size = type_size(field->type); 1315 1316 field->accept(this); 1317 fs_reg src_reg = this->result; 1318 1319 dst_reg.type = src_reg.type; 1320 for (unsigned j = 0; j < size; j++) { 1321 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1322 src_reg.reg_offset++; 1323 dst_reg.reg_offset++; 1324 } 1325 } 1326 } else { 1327 const unsigned size = type_size(ir->type); 1328 1329 for (unsigned i = 0; i < size; i++) { 1330 switch (ir->type->base_type) { 1331 case GLSL_TYPE_FLOAT: 1332 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i])); 1333 break; 1334 case GLSL_TYPE_UINT: 1335 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i])); 1336 break; 1337 case GLSL_TYPE_INT: 1338 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.i[i])); 1339 break; 1340 case GLSL_TYPE_BOOL: 1341 emit(BRW_OPCODE_MOV, dst_reg, fs_reg((int)ir->value.b[i])); 1342 break; 1343 default: 1344 assert(!"Non-float/uint/int/bool constant"); 1345 } 1346 dst_reg.reg_offset++; 1347 } 1348 } 1349 1350 this->result = reg; 1351} 1352 1353void 1354fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir) 1355{ 1356 ir_expression *expr = ir->as_expression(); 1357 1358 if (expr) { 1359 fs_reg op[2]; 1360 fs_inst *inst; 1361 1362 assert(expr->get_num_operands() <= 2); 1363 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1364 assert(expr->operands[i]->type->is_scalar()); 1365 1366 expr->operands[i]->accept(this); 1367 op[i] = this->result; 1368 } 1369 1370 switch (expr->operation) { 1371 case ir_unop_logic_not: 1372 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1)); 1373 inst->conditional_mod = BRW_CONDITIONAL_Z; 1374 break; 1375 1376 case ir_binop_logic_xor: 1377 inst = emit(BRW_OPCODE_XOR, reg_null_d, op[0], op[1]); 1378 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1379 break; 1380 1381 case ir_binop_logic_or: 1382 inst = emit(BRW_OPCODE_OR, reg_null_d, op[0], op[1]); 1383 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1384 break; 1385 1386 case ir_binop_logic_and: 1387 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], op[1]); 1388 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1389 break; 1390 1391 case ir_unop_f2b: 1392 if (intel->gen >= 6) { 1393 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0.0f)); 1394 } else { 1395 inst = emit(BRW_OPCODE_MOV, reg_null_f, op[0]); 1396 } 1397 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1398 break; 1399 1400 case ir_unop_i2b: 1401 if (intel->gen >= 6) { 1402 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0)); 1403 } else { 1404 inst = emit(BRW_OPCODE_MOV, reg_null_d, op[0]); 1405 } 1406 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1407 break; 1408 1409 case ir_binop_greater: 1410 case ir_binop_gequal: 1411 case ir_binop_less: 1412 case ir_binop_lequal: 1413 case ir_binop_equal: 1414 case ir_binop_all_equal: 1415 case ir_binop_nequal: 1416 case ir_binop_any_nequal: 1417 inst = emit(BRW_OPCODE_CMP, reg_null_cmp, op[0], op[1]); 1418 inst->conditional_mod = 1419 brw_conditional_for_comparison(expr->operation); 1420 break; 1421 1422 default: 1423 assert(!"not reached"); 1424 fail("bad cond code\n"); 1425 break; 1426 } 1427 return; 1428 } 1429 1430 ir->accept(this); 1431 1432 if (intel->gen >= 6) { 1433 fs_inst *inst = emit(BRW_OPCODE_AND, reg_null_d, this->result, fs_reg(1)); 1434 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1435 } else { 1436 fs_inst *inst = emit(BRW_OPCODE_MOV, reg_null_d, this->result); 1437 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1438 } 1439} 1440 1441/** 1442 * Emit a gen6 IF statement with the comparison folded into the IF 1443 * instruction. 1444 */ 1445void 1446fs_visitor::emit_if_gen6(ir_if *ir) 1447{ 1448 ir_expression *expr = ir->condition->as_expression(); 1449 1450 if (expr) { 1451 fs_reg op[2]; 1452 fs_inst *inst; 1453 fs_reg temp; 1454 1455 assert(expr->get_num_operands() <= 2); 1456 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1457 assert(expr->operands[i]->type->is_scalar()); 1458 1459 expr->operands[i]->accept(this); 1460 op[i] = this->result; 1461 } 1462 1463 switch (expr->operation) { 1464 case ir_unop_logic_not: 1465 inst = emit(BRW_OPCODE_IF, temp, op[0], fs_reg(0)); 1466 inst->conditional_mod = BRW_CONDITIONAL_Z; 1467 return; 1468 1469 case ir_binop_logic_xor: 1470 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1471 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1472 return; 1473 1474 case ir_binop_logic_or: 1475 temp = fs_reg(this, glsl_type::bool_type); 1476 emit(BRW_OPCODE_OR, temp, op[0], op[1]); 1477 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1478 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1479 return; 1480 1481 case ir_binop_logic_and: 1482 temp = fs_reg(this, glsl_type::bool_type); 1483 emit(BRW_OPCODE_AND, temp, op[0], op[1]); 1484 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1485 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1486 return; 1487 1488 case ir_unop_f2b: 1489 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0)); 1490 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1491 return; 1492 1493 case ir_unop_i2b: 1494 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1495 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1496 return; 1497 1498 case ir_binop_greater: 1499 case ir_binop_gequal: 1500 case ir_binop_less: 1501 case ir_binop_lequal: 1502 case ir_binop_equal: 1503 case ir_binop_all_equal: 1504 case ir_binop_nequal: 1505 case ir_binop_any_nequal: 1506 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1507 inst->conditional_mod = 1508 brw_conditional_for_comparison(expr->operation); 1509 return; 1510 default: 1511 assert(!"not reached"); 1512 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1513 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1514 fail("bad condition\n"); 1515 return; 1516 } 1517 return; 1518 } 1519 1520 ir->condition->accept(this); 1521 1522 fs_inst *inst = emit(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0)); 1523 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1524} 1525 1526void 1527fs_visitor::visit(ir_if *ir) 1528{ 1529 fs_inst *inst; 1530 1531 if (intel->gen < 6 && c->dispatch_width == 16) { 1532 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1533 } 1534 1535 /* Don't point the annotation at the if statement, because then it plus 1536 * the then and else blocks get printed. 1537 */ 1538 this->base_ir = ir->condition; 1539 1540 if (intel->gen == 6) { 1541 emit_if_gen6(ir); 1542 } else { 1543 emit_bool_to_cond_code(ir->condition); 1544 1545 inst = emit(BRW_OPCODE_IF); 1546 inst->predicated = true; 1547 } 1548 1549 foreach_list(node, &ir->then_instructions) { 1550 ir_instruction *ir = (ir_instruction *)node; 1551 this->base_ir = ir; 1552 1553 ir->accept(this); 1554 } 1555 1556 if (!ir->else_instructions.is_empty()) { 1557 emit(BRW_OPCODE_ELSE); 1558 1559 foreach_list(node, &ir->else_instructions) { 1560 ir_instruction *ir = (ir_instruction *)node; 1561 this->base_ir = ir; 1562 1563 ir->accept(this); 1564 } 1565 } 1566 1567 emit(BRW_OPCODE_ENDIF); 1568} 1569 1570void 1571fs_visitor::visit(ir_loop *ir) 1572{ 1573 fs_reg counter = reg_undef; 1574 1575 if (c->dispatch_width == 16) { 1576 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1577 } 1578 1579 if (ir->counter) { 1580 this->base_ir = ir->counter; 1581 ir->counter->accept(this); 1582 counter = *(variable_storage(ir->counter)); 1583 1584 if (ir->from) { 1585 this->base_ir = ir->from; 1586 ir->from->accept(this); 1587 1588 emit(BRW_OPCODE_MOV, counter, this->result); 1589 } 1590 } 1591 1592 emit(BRW_OPCODE_DO); 1593 1594 if (ir->to) { 1595 this->base_ir = ir->to; 1596 ir->to->accept(this); 1597 1598 fs_inst *inst = emit(BRW_OPCODE_CMP, reg_null_cmp, counter, this->result); 1599 inst->conditional_mod = brw_conditional_for_comparison(ir->cmp); 1600 1601 inst = emit(BRW_OPCODE_BREAK); 1602 inst->predicated = true; 1603 } 1604 1605 foreach_list(node, &ir->body_instructions) { 1606 ir_instruction *ir = (ir_instruction *)node; 1607 1608 this->base_ir = ir; 1609 ir->accept(this); 1610 } 1611 1612 if (ir->increment) { 1613 this->base_ir = ir->increment; 1614 ir->increment->accept(this); 1615 emit(BRW_OPCODE_ADD, counter, counter, this->result); 1616 } 1617 1618 emit(BRW_OPCODE_WHILE); 1619} 1620 1621void 1622fs_visitor::visit(ir_loop_jump *ir) 1623{ 1624 switch (ir->mode) { 1625 case ir_loop_jump::jump_break: 1626 emit(BRW_OPCODE_BREAK); 1627 break; 1628 case ir_loop_jump::jump_continue: 1629 emit(BRW_OPCODE_CONTINUE); 1630 break; 1631 } 1632} 1633 1634void 1635fs_visitor::visit(ir_call *ir) 1636{ 1637 assert(!"FINISHME"); 1638} 1639 1640void 1641fs_visitor::visit(ir_return *ir) 1642{ 1643 assert(!"FINISHME"); 1644} 1645 1646void 1647fs_visitor::visit(ir_function *ir) 1648{ 1649 /* Ignore function bodies other than main() -- we shouldn't see calls to 1650 * them since they should all be inlined before we get to ir_to_mesa. 1651 */ 1652 if (strcmp(ir->name, "main") == 0) { 1653 const ir_function_signature *sig; 1654 exec_list empty; 1655 1656 sig = ir->matching_signature(&empty); 1657 1658 assert(sig); 1659 1660 foreach_list(node, &sig->body) { 1661 ir_instruction *ir = (ir_instruction *)node; 1662 this->base_ir = ir; 1663 1664 ir->accept(this); 1665 } 1666 } 1667} 1668 1669void 1670fs_visitor::visit(ir_function_signature *ir) 1671{ 1672 assert(!"not reached"); 1673 (void)ir; 1674} 1675 1676fs_inst * 1677fs_visitor::emit(fs_inst inst) 1678{ 1679 fs_inst *list_inst = new(mem_ctx) fs_inst; 1680 *list_inst = inst; 1681 1682 if (force_uncompressed_stack > 0) 1683 list_inst->force_uncompressed = true; 1684 else if (force_sechalf_stack > 0) 1685 list_inst->force_sechalf = true; 1686 1687 list_inst->annotation = this->current_annotation; 1688 list_inst->ir = this->base_ir; 1689 1690 this->instructions.push_tail(list_inst); 1691 1692 return list_inst; 1693} 1694 1695/** Emits a dummy fragment shader consisting of magenta for bringup purposes. */ 1696void 1697fs_visitor::emit_dummy_fs() 1698{ 1699 /* Everyone's favorite color. */ 1700 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2), fs_reg(1.0f)); 1701 emit(BRW_OPCODE_MOV, fs_reg(MRF, 3), fs_reg(0.0f)); 1702 emit(BRW_OPCODE_MOV, fs_reg(MRF, 4), fs_reg(1.0f)); 1703 emit(BRW_OPCODE_MOV, fs_reg(MRF, 5), fs_reg(0.0f)); 1704 1705 fs_inst *write; 1706 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0)); 1707 write->base_mrf = 2; 1708} 1709 1710/* The register location here is relative to the start of the URB 1711 * data. It will get adjusted to be a real location before 1712 * generate_code() time. 1713 */ 1714struct brw_reg 1715fs_visitor::interp_reg(int location, int channel) 1716{ 1717 int regnr = urb_setup[location] * 2 + channel / 2; 1718 int stride = (channel & 1) * 4; 1719 1720 assert(urb_setup[location] != -1); 1721 1722 return brw_vec1_grf(regnr, stride); 1723} 1724 1725/** Emits the interpolation for the varying inputs. */ 1726void 1727fs_visitor::emit_interpolation_setup_gen4() 1728{ 1729 this->current_annotation = "compute pixel centers"; 1730 this->pixel_x = fs_reg(this, glsl_type::uint_type); 1731 this->pixel_y = fs_reg(this, glsl_type::uint_type); 1732 this->pixel_x.type = BRW_REGISTER_TYPE_UW; 1733 this->pixel_y.type = BRW_REGISTER_TYPE_UW; 1734 1735 emit(FS_OPCODE_PIXEL_X, this->pixel_x); 1736 emit(FS_OPCODE_PIXEL_Y, this->pixel_y); 1737 1738 this->current_annotation = "compute pixel deltas from v0"; 1739 if (brw->has_pln) { 1740 this->delta_x = fs_reg(this, glsl_type::vec2_type); 1741 this->delta_y = this->delta_x; 1742 this->delta_y.reg_offset++; 1743 } else { 1744 this->delta_x = fs_reg(this, glsl_type::float_type); 1745 this->delta_y = fs_reg(this, glsl_type::float_type); 1746 } 1747 emit(BRW_OPCODE_ADD, this->delta_x, 1748 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))); 1749 emit(BRW_OPCODE_ADD, this->delta_y, 1750 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))); 1751 1752 this->current_annotation = "compute pos.w and 1/pos.w"; 1753 /* Compute wpos.w. It's always in our setup, since it's needed to 1754 * interpolate the other attributes. 1755 */ 1756 this->wpos_w = fs_reg(this, glsl_type::float_type); 1757 emit(FS_OPCODE_LINTERP, wpos_w, this->delta_x, this->delta_y, 1758 interp_reg(FRAG_ATTRIB_WPOS, 3)); 1759 /* Compute the pixel 1/W value from wpos.w. */ 1760 this->pixel_w = fs_reg(this, glsl_type::float_type); 1761 emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w); 1762 this->current_annotation = NULL; 1763} 1764 1765/** Emits the interpolation for the varying inputs. */ 1766void 1767fs_visitor::emit_interpolation_setup_gen6() 1768{ 1769 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); 1770 1771 /* If the pixel centers end up used, the setup is the same as for gen4. */ 1772 this->current_annotation = "compute pixel centers"; 1773 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type); 1774 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type); 1775 int_pixel_x.type = BRW_REGISTER_TYPE_UW; 1776 int_pixel_y.type = BRW_REGISTER_TYPE_UW; 1777 emit(BRW_OPCODE_ADD, 1778 int_pixel_x, 1779 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), 1780 fs_reg(brw_imm_v(0x10101010))); 1781 emit(BRW_OPCODE_ADD, 1782 int_pixel_y, 1783 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), 1784 fs_reg(brw_imm_v(0x11001100))); 1785 1786 /* As of gen6, we can no longer mix float and int sources. We have 1787 * to turn the integer pixel centers into floats for their actual 1788 * use. 1789 */ 1790 this->pixel_x = fs_reg(this, glsl_type::float_type); 1791 this->pixel_y = fs_reg(this, glsl_type::float_type); 1792 emit(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x); 1793 emit(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y); 1794 1795 this->current_annotation = "compute pos.w"; 1796 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0)); 1797 this->wpos_w = fs_reg(this, glsl_type::float_type); 1798 emit_math(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w); 1799 1800 this->delta_x = fs_reg(brw_vec8_grf(2, 0)); 1801 this->delta_y = fs_reg(brw_vec8_grf(3, 0)); 1802 1803 this->current_annotation = NULL; 1804} 1805 1806void 1807fs_visitor::emit_color_write(int index, int first_color_mrf, fs_reg color) 1808{ 1809 int reg_width = c->dispatch_width / 8; 1810 fs_inst *inst; 1811 1812 if (c->dispatch_width == 8 || intel->gen >= 6) { 1813 /* SIMD8 write looks like: 1814 * m + 0: r0 1815 * m + 1: r1 1816 * m + 2: g0 1817 * m + 3: g1 1818 * 1819 * gen6 SIMD16 DP write looks like: 1820 * m + 0: r0 1821 * m + 1: r1 1822 * m + 2: g0 1823 * m + 3: g1 1824 * m + 4: b0 1825 * m + 5: b1 1826 * m + 6: a0 1827 * m + 7: a1 1828 */ 1829 inst = emit(BRW_OPCODE_MOV, 1830 fs_reg(MRF, first_color_mrf + index * reg_width), 1831 color); 1832 inst->saturate = c->key.clamp_fragment_color; 1833 } else { 1834 /* pre-gen6 SIMD16 single source DP write looks like: 1835 * m + 0: r0 1836 * m + 1: g0 1837 * m + 2: b0 1838 * m + 3: a0 1839 * m + 4: r1 1840 * m + 5: g1 1841 * m + 6: b1 1842 * m + 7: a1 1843 */ 1844 if (brw->has_compr4) { 1845 /* By setting the high bit of the MRF register number, we 1846 * indicate that we want COMPR4 mode - instead of doing the 1847 * usual destination + 1 for the second half we get 1848 * destination + 4. 1849 */ 1850 inst = emit(BRW_OPCODE_MOV, 1851 fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index), 1852 color); 1853 inst->saturate = c->key.clamp_fragment_color; 1854 } else { 1855 push_force_uncompressed(); 1856 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index), 1857 color); 1858 inst->saturate = c->key.clamp_fragment_color; 1859 pop_force_uncompressed(); 1860 1861 push_force_sechalf(); 1862 color.sechalf = true; 1863 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index + 4), 1864 color); 1865 inst->saturate = c->key.clamp_fragment_color; 1866 pop_force_sechalf(); 1867 color.sechalf = false; 1868 } 1869 } 1870} 1871 1872void 1873fs_visitor::emit_fb_writes() 1874{ 1875 this->current_annotation = "FB write header"; 1876 GLboolean header_present = GL_TRUE; 1877 int base_mrf = 2; 1878 int nr = base_mrf; 1879 int reg_width = c->dispatch_width / 8; 1880 1881 if (intel->gen >= 6 && 1882 !this->kill_emitted && 1883 c->key.nr_color_regions == 1) { 1884 header_present = false; 1885 } 1886 1887 if (header_present) { 1888 /* m2, m3 header */ 1889 nr += 2; 1890 } 1891 1892 if (c->aa_dest_stencil_reg) { 1893 push_force_uncompressed(); 1894 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++), 1895 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))); 1896 pop_force_uncompressed(); 1897 } 1898 1899 /* Reserve space for color. It'll be filled in per MRT below. */ 1900 int color_mrf = nr; 1901 nr += 4 * reg_width; 1902 1903 if (c->source_depth_to_render_target) { 1904 if (intel->gen == 6 && c->dispatch_width == 16) { 1905 /* For outputting oDepth on gen6, SIMD8 writes have to be 1906 * used. This would require 8-wide moves of each half to 1907 * message regs, kind of like pre-gen5 SIMD16 FB writes. 1908 * Just bail on doing so for now. 1909 */ 1910 fail("Missing support for simd16 depth writes on gen6\n"); 1911 } 1912 1913 if (c->computes_depth) { 1914 /* Hand over gl_FragDepth. */ 1915 assert(this->frag_depth); 1916 fs_reg depth = *(variable_storage(this->frag_depth)); 1917 1918 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), depth); 1919 } else { 1920 /* Pass through the payload depth. */ 1921 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1922 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))); 1923 } 1924 nr += reg_width; 1925 } 1926 1927 if (c->dest_depth_reg) { 1928 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1929 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))); 1930 nr += reg_width; 1931 } 1932 1933 fs_reg color = reg_undef; 1934 if (this->frag_color) 1935 color = *(variable_storage(this->frag_color)); 1936 else if (this->frag_data) { 1937 color = *(variable_storage(this->frag_data)); 1938 color.type = BRW_REGISTER_TYPE_F; 1939 } 1940 1941 for (int target = 0; target < c->key.nr_color_regions; target++) { 1942 this->current_annotation = ralloc_asprintf(this->mem_ctx, 1943 "FB write target %d", 1944 target); 1945 if (this->frag_color || this->frag_data) { 1946 for (int i = 0; i < 4; i++) { 1947 emit_color_write(i, color_mrf, color); 1948 color.reg_offset++; 1949 } 1950 } 1951 1952 if (this->frag_color) 1953 color.reg_offset -= 4; 1954 1955 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1956 inst->target = target; 1957 inst->base_mrf = base_mrf; 1958 inst->mlen = nr - base_mrf; 1959 if (target == c->key.nr_color_regions - 1) 1960 inst->eot = true; 1961 inst->header_present = header_present; 1962 } 1963 1964 if (c->key.nr_color_regions == 0) { 1965 if (c->key.alpha_test && (this->frag_color || this->frag_data)) { 1966 /* If the alpha test is enabled but there's no color buffer, 1967 * we still need to send alpha out the pipeline to our null 1968 * renderbuffer. 1969 */ 1970 color.reg_offset += 3; 1971 emit_color_write(3, color_mrf, color); 1972 } 1973 1974 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1975 inst->base_mrf = base_mrf; 1976 inst->mlen = nr - base_mrf; 1977 inst->eot = true; 1978 inst->header_present = header_present; 1979 } 1980 1981 this->current_annotation = NULL; 1982} 1983