brw_fs_visitor.cpp revision 83df7fbe62be2798d557142a47e01af86ec9e2e2
1/* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24/** @file brw_fs_visitor.cpp 25 * 26 * This file supports generating the FS LIR from the GLSL IR. The LIR 27 * makes it easier to do backend-specific optimizations than doing so 28 * in the GLSL IR or in the native code. 29 */ 30extern "C" { 31 32#include <sys/types.h> 33 34#include "main/macros.h" 35#include "main/shaderobj.h" 36#include "main/uniforms.h" 37#include "program/prog_parameter.h" 38#include "program/prog_print.h" 39#include "program/prog_optimize.h" 40#include "program/register_allocate.h" 41#include "program/sampler.h" 42#include "program/hash_table.h" 43#include "brw_context.h" 44#include "brw_eu.h" 45#include "brw_wm.h" 46} 47#include "brw_shader.h" 48#include "brw_fs.h" 49#include "glsl/glsl_types.h" 50#include "glsl/ir_optimization.h" 51#include "glsl/ir_print_visitor.h" 52 53void 54fs_visitor::visit(ir_variable *ir) 55{ 56 fs_reg *reg = NULL; 57 58 if (variable_storage(ir)) 59 return; 60 61 if (strcmp(ir->name, "gl_FragColor") == 0) { 62 this->frag_color = ir; 63 } else if (strcmp(ir->name, "gl_FragData") == 0) { 64 this->frag_data = ir; 65 } else if (strcmp(ir->name, "gl_FragDepth") == 0) { 66 this->frag_depth = ir; 67 } 68 69 if (ir->mode == ir_var_in) { 70 if (!strcmp(ir->name, "gl_FragCoord")) { 71 reg = emit_fragcoord_interpolation(ir); 72 } else if (!strcmp(ir->name, "gl_FrontFacing")) { 73 reg = emit_frontfacing_interpolation(ir); 74 } else { 75 reg = emit_general_interpolation(ir); 76 } 77 assert(reg); 78 hash_table_insert(this->variable_ht, reg, ir); 79 return; 80 } 81 82 if (ir->mode == ir_var_uniform) { 83 int param_index = c->prog_data.nr_params; 84 85 if (c->dispatch_width == 16) { 86 if (!variable_storage(ir)) { 87 fail("Failed to find uniform '%s' in 16-wide\n", ir->name); 88 } 89 return; 90 } 91 92 if (!strncmp(ir->name, "gl_", 3)) { 93 setup_builtin_uniform_values(ir); 94 } else { 95 setup_uniform_values(ir->location, ir->type); 96 } 97 98 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index); 99 reg->type = brw_type_for_base_type(ir->type); 100 } 101 102 if (!reg) 103 reg = new(this->mem_ctx) fs_reg(this, ir->type); 104 105 hash_table_insert(this->variable_ht, reg, ir); 106} 107 108void 109fs_visitor::visit(ir_dereference_variable *ir) 110{ 111 fs_reg *reg = variable_storage(ir->var); 112 this->result = *reg; 113} 114 115void 116fs_visitor::visit(ir_dereference_record *ir) 117{ 118 const glsl_type *struct_type = ir->record->type; 119 120 ir->record->accept(this); 121 122 unsigned int offset = 0; 123 for (unsigned int i = 0; i < struct_type->length; i++) { 124 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0) 125 break; 126 offset += type_size(struct_type->fields.structure[i].type); 127 } 128 this->result.reg_offset += offset; 129 this->result.type = brw_type_for_base_type(ir->type); 130} 131 132void 133fs_visitor::visit(ir_dereference_array *ir) 134{ 135 ir_constant *index; 136 int element_size; 137 138 ir->array->accept(this); 139 index = ir->array_index->as_constant(); 140 141 element_size = type_size(ir->type); 142 this->result.type = brw_type_for_base_type(ir->type); 143 144 if (index) { 145 assert(this->result.file == UNIFORM || this->result.file == GRF); 146 this->result.reg_offset += index->value.i[0] * element_size; 147 } else { 148 assert(!"FINISHME: non-constant array element"); 149 } 150} 151 152/* Instruction selection: Produce a MOV.sat instead of 153 * MIN(MAX(val, 0), 1) when possible. 154 */ 155bool 156fs_visitor::try_emit_saturate(ir_expression *ir) 157{ 158 ir_rvalue *sat_val = ir->as_rvalue_to_saturate(); 159 160 if (!sat_val) 161 return false; 162 163 sat_val->accept(this); 164 fs_reg src = this->result; 165 166 this->result = fs_reg(this, ir->type); 167 fs_inst *inst = emit(BRW_OPCODE_MOV, this->result, src); 168 inst->saturate = true; 169 170 return true; 171} 172 173void 174fs_visitor::visit(ir_expression *ir) 175{ 176 unsigned int operand; 177 fs_reg op[2], temp; 178 fs_inst *inst; 179 180 assert(ir->get_num_operands() <= 2); 181 182 if (try_emit_saturate(ir)) 183 return; 184 185 for (operand = 0; operand < ir->get_num_operands(); operand++) { 186 ir->operands[operand]->accept(this); 187 if (this->result.file == BAD_FILE) { 188 ir_print_visitor v; 189 fail("Failed to get tree for expression operand:\n"); 190 ir->operands[operand]->accept(&v); 191 } 192 op[operand] = this->result; 193 194 /* Matrix expression operands should have been broken down to vector 195 * operations already. 196 */ 197 assert(!ir->operands[operand]->type->is_matrix()); 198 /* And then those vector operands should have been broken down to scalar. 199 */ 200 assert(!ir->operands[operand]->type->is_vector()); 201 } 202 203 /* Storage for our result. If our result goes into an assignment, it will 204 * just get copy-propagated out, so no worries. 205 */ 206 this->result = fs_reg(this, ir->type); 207 208 switch (ir->operation) { 209 case ir_unop_logic_not: 210 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is 211 * ones complement of the whole register, not just bit 0. 212 */ 213 emit(BRW_OPCODE_XOR, this->result, op[0], fs_reg(1)); 214 break; 215 case ir_unop_neg: 216 op[0].negate = !op[0].negate; 217 this->result = op[0]; 218 break; 219 case ir_unop_abs: 220 op[0].abs = true; 221 op[0].negate = false; 222 this->result = op[0]; 223 break; 224 case ir_unop_sign: 225 temp = fs_reg(this, ir->type); 226 227 emit(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)); 228 229 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 230 inst->conditional_mod = BRW_CONDITIONAL_G; 231 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)); 232 inst->predicated = true; 233 234 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 235 inst->conditional_mod = BRW_CONDITIONAL_L; 236 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)); 237 inst->predicated = true; 238 239 break; 240 case ir_unop_rcp: 241 emit_math(SHADER_OPCODE_RCP, this->result, op[0]); 242 break; 243 244 case ir_unop_exp2: 245 emit_math(SHADER_OPCODE_EXP2, this->result, op[0]); 246 break; 247 case ir_unop_log2: 248 emit_math(SHADER_OPCODE_LOG2, this->result, op[0]); 249 break; 250 case ir_unop_exp: 251 case ir_unop_log: 252 assert(!"not reached: should be handled by ir_explog_to_explog2"); 253 break; 254 case ir_unop_sin: 255 case ir_unop_sin_reduced: 256 emit_math(SHADER_OPCODE_SIN, this->result, op[0]); 257 break; 258 case ir_unop_cos: 259 case ir_unop_cos_reduced: 260 emit_math(SHADER_OPCODE_COS, this->result, op[0]); 261 break; 262 263 case ir_unop_dFdx: 264 emit(FS_OPCODE_DDX, this->result, op[0]); 265 break; 266 case ir_unop_dFdy: 267 emit(FS_OPCODE_DDY, this->result, op[0]); 268 break; 269 270 case ir_binop_add: 271 emit(BRW_OPCODE_ADD, this->result, op[0], op[1]); 272 break; 273 case ir_binop_sub: 274 assert(!"not reached: should be handled by ir_sub_to_add_neg"); 275 break; 276 277 case ir_binop_mul: 278 if (ir->type->is_integer()) { 279 /* For integer multiplication, the MUL uses the low 16 bits 280 * of one of the operands (src0 on gen6, src1 on gen7). The 281 * MACH accumulates in the contribution of the upper 16 bits 282 * of that operand. 283 * 284 * FINISHME: Emit just the MUL if we know an operand is small 285 * enough. 286 */ 287 struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_D); 288 289 emit(BRW_OPCODE_MUL, acc, op[0], op[1]); 290 emit(BRW_OPCODE_MACH, reg_null_d, op[0], op[1]); 291 emit(BRW_OPCODE_MOV, this->result, fs_reg(acc)); 292 } else { 293 emit(BRW_OPCODE_MUL, this->result, op[0], op[1]); 294 } 295 break; 296 case ir_binop_div: 297 assert(!"not reached: should be handled by ir_div_to_mul_rcp"); 298 break; 299 case ir_binop_mod: 300 assert(!"ir_binop_mod should have been converted to b * fract(a/b)"); 301 break; 302 303 case ir_binop_less: 304 case ir_binop_greater: 305 case ir_binop_lequal: 306 case ir_binop_gequal: 307 case ir_binop_equal: 308 case ir_binop_all_equal: 309 case ir_binop_nequal: 310 case ir_binop_any_nequal: 311 temp = this->result; 312 /* original gen4 does implicit conversion before comparison. */ 313 if (intel->gen < 5) 314 temp.type = op[0].type; 315 316 inst = emit(BRW_OPCODE_CMP, temp, op[0], op[1]); 317 inst->conditional_mod = brw_conditional_for_comparison(ir->operation); 318 emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)); 319 break; 320 321 case ir_binop_logic_xor: 322 emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 323 break; 324 325 case ir_binop_logic_or: 326 emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 327 break; 328 329 case ir_binop_logic_and: 330 emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 331 break; 332 333 case ir_binop_dot: 334 case ir_unop_any: 335 assert(!"not reached: should be handled by brw_fs_channel_expressions"); 336 break; 337 338 case ir_unop_noise: 339 assert(!"not reached: should be handled by lower_noise"); 340 break; 341 342 case ir_quadop_vector: 343 assert(!"not reached: should be handled by lower_quadop_vector"); 344 break; 345 346 case ir_unop_sqrt: 347 emit_math(SHADER_OPCODE_SQRT, this->result, op[0]); 348 break; 349 350 case ir_unop_rsq: 351 emit_math(SHADER_OPCODE_RSQ, this->result, op[0]); 352 break; 353 354 case ir_unop_i2u: 355 op[0].type = BRW_REGISTER_TYPE_UD; 356 this->result = op[0]; 357 break; 358 case ir_unop_u2i: 359 op[0].type = BRW_REGISTER_TYPE_D; 360 this->result = op[0]; 361 break; 362 case ir_unop_i2f: 363 case ir_unop_u2f: 364 case ir_unop_b2f: 365 case ir_unop_b2i: 366 case ir_unop_f2i: 367 emit(BRW_OPCODE_MOV, this->result, op[0]); 368 break; 369 case ir_unop_f2b: 370 case ir_unop_i2b: 371 temp = this->result; 372 /* original gen4 does implicit conversion before comparison. */ 373 if (intel->gen < 5) 374 temp.type = op[0].type; 375 376 inst = emit(BRW_OPCODE_CMP, temp, op[0], fs_reg(0.0f)); 377 inst->conditional_mod = BRW_CONDITIONAL_NZ; 378 inst = emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(1)); 379 break; 380 381 case ir_unop_trunc: 382 emit(BRW_OPCODE_RNDZ, this->result, op[0]); 383 break; 384 case ir_unop_ceil: 385 op[0].negate = !op[0].negate; 386 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 387 this->result.negate = true; 388 break; 389 case ir_unop_floor: 390 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 391 break; 392 case ir_unop_fract: 393 inst = emit(BRW_OPCODE_FRC, this->result, op[0]); 394 break; 395 case ir_unop_round_even: 396 emit(BRW_OPCODE_RNDE, this->result, op[0]); 397 break; 398 399 case ir_binop_min: 400 if (intel->gen >= 6) { 401 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 402 inst->conditional_mod = BRW_CONDITIONAL_L; 403 } else { 404 /* Unalias the destination */ 405 this->result = fs_reg(this, ir->type); 406 407 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 408 inst->conditional_mod = BRW_CONDITIONAL_L; 409 410 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 411 inst->predicated = true; 412 } 413 break; 414 case ir_binop_max: 415 if (intel->gen >= 6) { 416 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 417 inst->conditional_mod = BRW_CONDITIONAL_GE; 418 } else { 419 /* Unalias the destination */ 420 this->result = fs_reg(this, ir->type); 421 422 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 423 inst->conditional_mod = BRW_CONDITIONAL_G; 424 425 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 426 inst->predicated = true; 427 } 428 break; 429 430 case ir_binop_pow: 431 emit_math(SHADER_OPCODE_POW, this->result, op[0], op[1]); 432 break; 433 434 case ir_unop_bit_not: 435 inst = emit(BRW_OPCODE_NOT, this->result, op[0]); 436 break; 437 case ir_binop_bit_and: 438 inst = emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 439 break; 440 case ir_binop_bit_xor: 441 inst = emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 442 break; 443 case ir_binop_bit_or: 444 inst = emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 445 break; 446 447 case ir_binop_lshift: 448 case ir_binop_rshift: 449 assert(!"GLSL 1.30 features unsupported"); 450 break; 451 } 452} 453 454void 455fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r, 456 const glsl_type *type, bool predicated) 457{ 458 switch (type->base_type) { 459 case GLSL_TYPE_FLOAT: 460 case GLSL_TYPE_UINT: 461 case GLSL_TYPE_INT: 462 case GLSL_TYPE_BOOL: 463 for (unsigned int i = 0; i < type->components(); i++) { 464 l.type = brw_type_for_base_type(type); 465 r.type = brw_type_for_base_type(type); 466 467 if (predicated || !l.equals(&r)) { 468 fs_inst *inst = emit(BRW_OPCODE_MOV, l, r); 469 inst->predicated = predicated; 470 } 471 472 l.reg_offset++; 473 r.reg_offset++; 474 } 475 break; 476 case GLSL_TYPE_ARRAY: 477 for (unsigned int i = 0; i < type->length; i++) { 478 emit_assignment_writes(l, r, type->fields.array, predicated); 479 } 480 break; 481 482 case GLSL_TYPE_STRUCT: 483 for (unsigned int i = 0; i < type->length; i++) { 484 emit_assignment_writes(l, r, type->fields.structure[i].type, 485 predicated); 486 } 487 break; 488 489 case GLSL_TYPE_SAMPLER: 490 break; 491 492 default: 493 assert(!"not reached"); 494 break; 495 } 496} 497 498/* If the RHS processing resulted in an instruction generating a 499 * temporary value, and it would be easy to rewrite the instruction to 500 * generate its result right into the LHS instead, do so. This ends 501 * up reliably removing instructions where it can be tricky to do so 502 * later without real UD chain information. 503 */ 504bool 505fs_visitor::try_rewrite_rhs_to_dst(ir_assignment *ir, 506 fs_reg dst, 507 fs_reg src, 508 fs_inst *pre_rhs_inst, 509 fs_inst *last_rhs_inst) 510{ 511 if (pre_rhs_inst == last_rhs_inst) 512 return false; /* No instructions generated to work with. */ 513 514 /* Only attempt if we're doing a direct assignment. */ 515 if (ir->condition || 516 !(ir->lhs->type->is_scalar() || 517 (ir->lhs->type->is_vector() && 518 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1))) 519 return false; 520 521 /* Make sure the last instruction generated our source reg. */ 522 if (last_rhs_inst->predicated || 523 last_rhs_inst->force_uncompressed || 524 last_rhs_inst->force_sechalf || 525 !src.equals(&last_rhs_inst->dst)) 526 return false; 527 528 /* Success! Rewrite the instruction. */ 529 last_rhs_inst->dst = dst; 530 531 return true; 532} 533 534void 535fs_visitor::visit(ir_assignment *ir) 536{ 537 fs_reg l, r; 538 fs_inst *inst; 539 540 /* FINISHME: arrays on the lhs */ 541 ir->lhs->accept(this); 542 l = this->result; 543 544 fs_inst *pre_rhs_inst = (fs_inst *) this->instructions.get_tail(); 545 546 ir->rhs->accept(this); 547 r = this->result; 548 549 fs_inst *last_rhs_inst = (fs_inst *) this->instructions.get_tail(); 550 551 assert(l.file != BAD_FILE); 552 assert(r.file != BAD_FILE); 553 554 if (try_rewrite_rhs_to_dst(ir, l, r, pre_rhs_inst, last_rhs_inst)) 555 return; 556 557 if (ir->condition) { 558 emit_bool_to_cond_code(ir->condition); 559 } 560 561 if (ir->lhs->type->is_scalar() || 562 ir->lhs->type->is_vector()) { 563 for (int i = 0; i < ir->lhs->type->vector_elements; i++) { 564 if (ir->write_mask & (1 << i)) { 565 inst = emit(BRW_OPCODE_MOV, l, r); 566 if (ir->condition) 567 inst->predicated = true; 568 r.reg_offset++; 569 } 570 l.reg_offset++; 571 } 572 } else { 573 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL); 574 } 575} 576 577fs_inst * 578fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate, 579 int sampler) 580{ 581 int mlen; 582 int base_mrf = 1; 583 bool simd16 = false; 584 fs_reg orig_dst; 585 586 /* g0 header. */ 587 mlen = 1; 588 589 if (ir->shadow_comparitor && ir->op != ir_txd) { 590 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 591 fs_inst *inst = emit(BRW_OPCODE_MOV, 592 fs_reg(MRF, base_mrf + mlen + i), coordinate); 593 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 594 inst->saturate = true; 595 596 coordinate.reg_offset++; 597 } 598 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 599 mlen += 3; 600 601 if (ir->op == ir_tex) { 602 /* There's no plain shadow compare message, so we use shadow 603 * compare with a bias of 0.0. 604 */ 605 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)); 606 mlen++; 607 } else if (ir->op == ir_txb) { 608 ir->lod_info.bias->accept(this); 609 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 610 mlen++; 611 } else { 612 assert(ir->op == ir_txl); 613 ir->lod_info.lod->accept(this); 614 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 615 mlen++; 616 } 617 618 ir->shadow_comparitor->accept(this); 619 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 620 mlen++; 621 } else if (ir->op == ir_tex) { 622 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 623 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), 624 coordinate); 625 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 626 inst->saturate = true; 627 coordinate.reg_offset++; 628 } 629 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 630 mlen += 3; 631 } else if (ir->op == ir_txd) { 632 ir->lod_info.grad.dPdx->accept(this); 633 fs_reg dPdx = this->result; 634 635 ir->lod_info.grad.dPdy->accept(this); 636 fs_reg dPdy = this->result; 637 638 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 639 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); 640 coordinate.reg_offset++; 641 } 642 /* the slots for u and v are always present, but r is optional */ 643 mlen += MAX2(ir->coordinate->type->vector_elements, 2); 644 645 /* P = u, v, r 646 * dPdx = dudx, dvdx, drdx 647 * dPdy = dudy, dvdy, drdy 648 * 649 * 1-arg: Does not exist. 650 * 651 * 2-arg: dudx dvdx dudy dvdy 652 * dPdx.x dPdx.y dPdy.x dPdy.y 653 * m4 m5 m6 m7 654 * 655 * 3-arg: dudx dvdx drdx dudy dvdy drdy 656 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z 657 * m5 m6 m7 m8 m9 m10 658 */ 659 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 660 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 661 dPdx.reg_offset++; 662 } 663 mlen += MAX2(ir->lod_info.grad.dPdx->type->vector_elements, 2); 664 665 for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) { 666 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 667 dPdy.reg_offset++; 668 } 669 mlen += MAX2(ir->lod_info.grad.dPdy->type->vector_elements, 2); 670 } else if (ir->op == ir_txs) { 671 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */ 672 simd16 = true; 673 ir->lod_info.lod->accept(this); 674 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 675 mlen += 2; 676 } else { 677 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod 678 * instructions. We'll need to do SIMD16 here. 679 */ 680 simd16 = true; 681 assert(ir->op == ir_txb || ir->op == ir_txl || ir->op == ir_txf); 682 683 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 684 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, 685 base_mrf + mlen + i * 2, 686 coordinate.type), 687 coordinate); 688 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 689 inst->saturate = true; 690 coordinate.reg_offset++; 691 } 692 693 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to 694 * be necessary for TXF (ld), but seems wise to do for all messages. 695 */ 696 for (int i = ir->coordinate->type->vector_elements; i < 3; i++) { 697 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i * 2), fs_reg(0.0f)); 698 } 699 700 /* lod/bias appears after u/v/r. */ 701 mlen += 6; 702 703 if (ir->op == ir_txb) { 704 ir->lod_info.bias->accept(this); 705 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 706 mlen++; 707 } else { 708 ir->lod_info.lod->accept(this); 709 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, this->result.type), 710 this->result); 711 mlen++; 712 } 713 714 /* The unused upper half. */ 715 mlen++; 716 } 717 718 if (simd16) { 719 /* Now, since we're doing simd16, the return is 2 interleaved 720 * vec4s where the odd-indexed ones are junk. We'll need to move 721 * this weirdness around to the expected layout. 722 */ 723 orig_dst = dst; 724 const glsl_type *vec_type = 725 glsl_type::get_instance(ir->type->base_type, 4, 1); 726 dst = fs_reg(this, glsl_type::get_array_instance(vec_type, 2)); 727 dst.type = intel->is_g4x ? brw_type_for_base_type(ir->type) 728 : BRW_REGISTER_TYPE_F; 729 } 730 731 fs_inst *inst = NULL; 732 switch (ir->op) { 733 case ir_tex: 734 inst = emit(FS_OPCODE_TEX, dst); 735 break; 736 case ir_txb: 737 inst = emit(FS_OPCODE_TXB, dst); 738 break; 739 case ir_txl: 740 inst = emit(FS_OPCODE_TXL, dst); 741 break; 742 case ir_txd: 743 inst = emit(FS_OPCODE_TXD, dst); 744 break; 745 case ir_txs: 746 inst = emit(FS_OPCODE_TXS, dst); 747 break; 748 case ir_txf: 749 inst = emit(FS_OPCODE_TXF, dst); 750 break; 751 } 752 inst->base_mrf = base_mrf; 753 inst->mlen = mlen; 754 inst->header_present = true; 755 756 if (simd16) { 757 for (int i = 0; i < 4; i++) { 758 emit(BRW_OPCODE_MOV, orig_dst, dst); 759 orig_dst.reg_offset++; 760 dst.reg_offset += 2; 761 } 762 } 763 764 return inst; 765} 766 767/* gen5's sampler has slots for u, v, r, array index, then optional 768 * parameters like shadow comparitor or LOD bias. If optional 769 * parameters aren't present, those base slots are optional and don't 770 * need to be included in the message. 771 * 772 * We don't fill in the unnecessary slots regardless, which may look 773 * surprising in the disassembly. 774 */ 775fs_inst * 776fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate, 777 int sampler) 778{ 779 int mlen = 0; 780 int base_mrf = 2; 781 int reg_width = c->dispatch_width / 8; 782 bool header_present = false; 783 const int vector_elements = 784 ir->coordinate ? ir->coordinate->type->vector_elements : 0; 785 786 if (ir->offset) { 787 /* The offsets set up by the ir_texture visitor are in the 788 * m1 header, so we can't go headerless. 789 */ 790 header_present = true; 791 mlen++; 792 base_mrf--; 793 } 794 795 for (int i = 0; i < vector_elements; i++) { 796 fs_inst *inst = emit(BRW_OPCODE_MOV, 797 fs_reg(MRF, base_mrf + mlen + i * reg_width, 798 coordinate.type), 799 coordinate); 800 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 801 inst->saturate = true; 802 coordinate.reg_offset++; 803 } 804 mlen += vector_elements * reg_width; 805 806 if (ir->shadow_comparitor && ir->op != ir_txd) { 807 mlen = MAX2(mlen, header_present + 4 * reg_width); 808 809 ir->shadow_comparitor->accept(this); 810 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 811 mlen += reg_width; 812 } 813 814 fs_inst *inst = NULL; 815 switch (ir->op) { 816 case ir_tex: 817 inst = emit(FS_OPCODE_TEX, dst); 818 break; 819 case ir_txb: 820 ir->lod_info.bias->accept(this); 821 mlen = MAX2(mlen, header_present + 4 * reg_width); 822 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 823 mlen += reg_width; 824 825 inst = emit(FS_OPCODE_TXB, dst); 826 827 break; 828 case ir_txl: 829 ir->lod_info.lod->accept(this); 830 mlen = MAX2(mlen, header_present + 4 * reg_width); 831 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 832 mlen += reg_width; 833 834 inst = emit(FS_OPCODE_TXL, dst); 835 break; 836 case ir_txd: { 837 ir->lod_info.grad.dPdx->accept(this); 838 fs_reg dPdx = this->result; 839 840 ir->lod_info.grad.dPdy->accept(this); 841 fs_reg dPdy = this->result; 842 843 mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */ 844 845 /** 846 * P = u, v, r 847 * dPdx = dudx, dvdx, drdx 848 * dPdy = dudy, dvdy, drdy 849 * 850 * Load up these values: 851 * - dudx dudy dvdx dvdy drdx drdy 852 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z 853 */ 854 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 855 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 856 dPdx.reg_offset++; 857 mlen += reg_width; 858 859 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 860 dPdy.reg_offset++; 861 mlen += reg_width; 862 } 863 864 inst = emit(FS_OPCODE_TXD, dst); 865 break; 866 } 867 case ir_txs: 868 ir->lod_info.lod->accept(this); 869 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 870 mlen += reg_width; 871 inst = emit(FS_OPCODE_TXS, dst); 872 break; 873 case ir_txf: 874 mlen = header_present + 4 * reg_width; 875 876 ir->lod_info.lod->accept(this); 877 emit(BRW_OPCODE_MOV, 878 fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), 879 this->result); 880 inst = emit(FS_OPCODE_TXF, dst); 881 break; 882 } 883 inst->base_mrf = base_mrf; 884 inst->mlen = mlen; 885 inst->header_present = header_present; 886 887 if (mlen > 11) { 888 fail("Message length >11 disallowed by hardware\n"); 889 } 890 891 return inst; 892} 893 894fs_inst * 895fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate, 896 int sampler) 897{ 898 int mlen = 0; 899 int base_mrf = 2; 900 int reg_width = c->dispatch_width / 8; 901 bool header_present = false; 902 903 if (ir->offset) { 904 /* The offsets set up by the ir_texture visitor are in the 905 * m1 header, so we can't go headerless. 906 */ 907 header_present = true; 908 mlen++; 909 base_mrf--; 910 } 911 912 if (ir->shadow_comparitor && ir->op != ir_txd) { 913 ir->shadow_comparitor->accept(this); 914 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 915 mlen += reg_width; 916 } 917 918 /* Set up the LOD info */ 919 switch (ir->op) { 920 case ir_tex: 921 break; 922 case ir_txb: 923 ir->lod_info.bias->accept(this); 924 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 925 mlen += reg_width; 926 break; 927 case ir_txl: 928 ir->lod_info.lod->accept(this); 929 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 930 mlen += reg_width; 931 break; 932 case ir_txd: { 933 if (c->dispatch_width == 16) 934 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode."); 935 936 ir->lod_info.grad.dPdx->accept(this); 937 fs_reg dPdx = this->result; 938 939 ir->lod_info.grad.dPdy->accept(this); 940 fs_reg dPdy = this->result; 941 942 /* Load dPdx and the coordinate together: 943 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z 944 */ 945 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 946 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 947 coordinate); 948 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 949 inst->saturate = true; 950 coordinate.reg_offset++; 951 mlen += reg_width; 952 953 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 954 dPdx.reg_offset++; 955 mlen += reg_width; 956 957 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 958 dPdy.reg_offset++; 959 mlen += reg_width; 960 } 961 break; 962 } 963 case ir_txs: 964 ir->lod_info.lod->accept(this); 965 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 966 mlen += reg_width; 967 break; 968 case ir_txf: 969 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */ 970 emit(BRW_OPCODE_MOV, 971 fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), coordinate); 972 coordinate.reg_offset++; 973 mlen += reg_width; 974 975 ir->lod_info.lod->accept(this); 976 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), this->result); 977 mlen += reg_width; 978 979 for (int i = 1; i < ir->coordinate->type->vector_elements; i++) { 980 emit(BRW_OPCODE_MOV, 981 fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), coordinate); 982 coordinate.reg_offset++; 983 mlen += reg_width; 984 } 985 break; 986 } 987 988 /* Set up the coordinate (except for cases where it was done above) */ 989 if (ir->op != ir_txd && ir->op != ir_txs && ir->op != ir_txf) { 990 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 991 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 992 coordinate); 993 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 994 inst->saturate = true; 995 coordinate.reg_offset++; 996 mlen += reg_width; 997 } 998 } 999 1000 /* Generate the SEND */ 1001 fs_inst *inst = NULL; 1002 switch (ir->op) { 1003 case ir_tex: inst = emit(FS_OPCODE_TEX, dst); break; 1004 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break; 1005 case ir_txl: inst = emit(FS_OPCODE_TXL, dst); break; 1006 case ir_txd: inst = emit(FS_OPCODE_TXD, dst); break; 1007 case ir_txf: inst = emit(FS_OPCODE_TXF, dst); break; 1008 case ir_txs: inst = emit(FS_OPCODE_TXS, dst); break; 1009 } 1010 inst->base_mrf = base_mrf; 1011 inst->mlen = mlen; 1012 inst->header_present = header_present; 1013 1014 if (mlen > 11) { 1015 fail("Message length >11 disallowed by hardware\n"); 1016 } 1017 1018 return inst; 1019} 1020 1021void 1022fs_visitor::visit(ir_texture *ir) 1023{ 1024 fs_inst *inst = NULL; 1025 1026 int sampler = _mesa_get_sampler_uniform_value(ir->sampler, prog, &fp->Base); 1027 sampler = fp->Base.SamplerUnits[sampler]; 1028 1029 /* Our hardware doesn't have a sample_d_c message, so shadow compares 1030 * for textureGrad/TXD need to be emulated with instructions. 1031 */ 1032 bool hw_compare_supported = ir->op != ir_txd; 1033 if (ir->shadow_comparitor && !hw_compare_supported) { 1034 assert(c->key.compare_funcs[sampler] != GL_NONE); 1035 /* No need to even sample for GL_ALWAYS or GL_NEVER...bail early */ 1036 if (c->key.compare_funcs[sampler] == GL_ALWAYS) 1037 return swizzle_result(ir, fs_reg(1.0f), sampler); 1038 else if (c->key.compare_funcs[sampler] == GL_NEVER) 1039 return swizzle_result(ir, fs_reg(0.0f), sampler); 1040 } 1041 1042 if (ir->coordinate) 1043 ir->coordinate->accept(this); 1044 fs_reg coordinate = this->result; 1045 1046 if (ir->offset != NULL) { 1047 ir_constant *offset = ir->offset->as_constant(); 1048 assert(offset != NULL); 1049 1050 signed char offsets[3]; 1051 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) 1052 offsets[i] = (signed char) offset->value.i[i]; 1053 1054 /* Combine all three offsets into a single unsigned dword: 1055 * 1056 * bits 11:8 - U Offset (X component) 1057 * bits 7:4 - V Offset (Y component) 1058 * bits 3:0 - R Offset (Z component) 1059 */ 1060 unsigned offset_bits = 0; 1061 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) { 1062 const unsigned shift = 4 * (2 - i); 1063 offset_bits |= (offsets[i] << shift) & (0xF << shift); 1064 } 1065 1066 /* Explicitly set up the message header by copying g0 to msg reg m1. */ 1067 emit(BRW_OPCODE_MOV, fs_reg(MRF, 1, BRW_REGISTER_TYPE_UD), 1068 fs_reg(GRF, 0, BRW_REGISTER_TYPE_UD)); 1069 1070 /* Then set the offset bits in DWord 2 of the message header. */ 1071 emit(BRW_OPCODE_MOV, 1072 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 1, 2), 1073 BRW_REGISTER_TYPE_UD)), 1074 fs_reg(brw_imm_uw(offset_bits))); 1075 } 1076 1077 /* Should be lowered by do_lower_texture_projection */ 1078 assert(!ir->projector); 1079 1080 /* The 965 requires the EU to do the normalization of GL rectangle 1081 * texture coordinates. We use the program parameter state 1082 * tracking to get the scaling factor. 1083 */ 1084 if (intel->gen < 6 && 1085 ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) { 1086 struct gl_program_parameter_list *params = c->fp->program.Base.Parameters; 1087 int tokens[STATE_LENGTH] = { 1088 STATE_INTERNAL, 1089 STATE_TEXRECT_SCALE, 1090 sampler, 1091 0, 1092 0 1093 }; 1094 1095 if (c->dispatch_width == 16) { 1096 fail("rectangle scale uniform setup not supported on 16-wide\n"); 1097 this->result = fs_reg(this, ir->type); 1098 return; 1099 } 1100 1101 c->prog_data.param_convert[c->prog_data.nr_params] = 1102 PARAM_NO_CONVERT; 1103 c->prog_data.param_convert[c->prog_data.nr_params + 1] = 1104 PARAM_NO_CONVERT; 1105 1106 fs_reg scale_x = fs_reg(UNIFORM, c->prog_data.nr_params); 1107 fs_reg scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1); 1108 GLuint index = _mesa_add_state_reference(params, 1109 (gl_state_index *)tokens); 1110 1111 this->param_index[c->prog_data.nr_params] = index; 1112 this->param_offset[c->prog_data.nr_params] = 0; 1113 c->prog_data.nr_params++; 1114 this->param_index[c->prog_data.nr_params] = index; 1115 this->param_offset[c->prog_data.nr_params] = 1; 1116 c->prog_data.nr_params++; 1117 1118 fs_reg dst = fs_reg(this, ir->coordinate->type); 1119 fs_reg src = coordinate; 1120 coordinate = dst; 1121 1122 emit(BRW_OPCODE_MUL, dst, src, scale_x); 1123 dst.reg_offset++; 1124 src.reg_offset++; 1125 emit(BRW_OPCODE_MUL, dst, src, scale_y); 1126 } 1127 1128 /* Writemasking doesn't eliminate channels on SIMD8 texture 1129 * samples, so don't worry about them. 1130 */ 1131 fs_reg dst = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 4, 1)); 1132 1133 if (intel->gen >= 7) { 1134 inst = emit_texture_gen7(ir, dst, coordinate, sampler); 1135 } else if (intel->gen >= 5) { 1136 inst = emit_texture_gen5(ir, dst, coordinate, sampler); 1137 } else { 1138 inst = emit_texture_gen4(ir, dst, coordinate, sampler); 1139 } 1140 1141 /* If there's an offset, we already set up m1. To avoid the implied move, 1142 * use the null register. Otherwise, we want an implied move from g0. 1143 */ 1144 if (ir->offset != NULL || !inst->header_present) 1145 inst->src[0] = reg_undef; 1146 else 1147 inst->src[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW)); 1148 1149 inst->sampler = sampler; 1150 1151 if (ir->shadow_comparitor) { 1152 if (hw_compare_supported) { 1153 inst->shadow_compare = true; 1154 } else { 1155 ir->shadow_comparitor->accept(this); 1156 fs_reg ref = this->result; 1157 1158 fs_reg value = dst; 1159 dst = fs_reg(this, glsl_type::vec4_type); 1160 1161 /* FINISHME: This needs to be done pre-filtering. */ 1162 1163 uint32_t conditional = 0; 1164 switch (c->key.compare_funcs[sampler]) { 1165 /* GL_ALWAYS and GL_NEVER were handled at the top of the function */ 1166 case GL_LESS: conditional = BRW_CONDITIONAL_L; break; 1167 case GL_GREATER: conditional = BRW_CONDITIONAL_G; break; 1168 case GL_LEQUAL: conditional = BRW_CONDITIONAL_LE; break; 1169 case GL_GEQUAL: conditional = BRW_CONDITIONAL_GE; break; 1170 case GL_EQUAL: conditional = BRW_CONDITIONAL_EQ; break; 1171 case GL_NOTEQUAL: conditional = BRW_CONDITIONAL_NEQ; break; 1172 default: assert(!"Should not get here: bad shadow compare function"); 1173 } 1174 1175 /* Use conditional moves to load 0 or 1 as the result */ 1176 this->current_annotation = "manual shadow comparison"; 1177 for (int i = 0; i < 4; i++) { 1178 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(0.0f)); 1179 1180 inst = emit(BRW_OPCODE_CMP, reg_null_f, ref, value); 1181 inst->conditional_mod = conditional; 1182 1183 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(1.0f)); 1184 inst->predicated = true; 1185 1186 dst.reg_offset++; 1187 value.reg_offset++; 1188 } 1189 dst.reg_offset = 0; 1190 } 1191 } 1192 1193 swizzle_result(ir, dst, sampler); 1194} 1195 1196/** 1197 * Swizzle the result of a texture result. This is necessary for 1198 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons. 1199 */ 1200void 1201fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler) 1202{ 1203 this->result = orig_val; 1204 1205 if (ir->type == glsl_type::float_type) { 1206 /* Ignore DEPTH_TEXTURE_MODE swizzling. */ 1207 assert(ir->sampler->type->sampler_shadow); 1208 } else if (c->key.tex_swizzles[sampler] != SWIZZLE_NOOP) { 1209 fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type); 1210 1211 for (int i = 0; i < 4; i++) { 1212 int swiz = GET_SWZ(c->key.tex_swizzles[sampler], i); 1213 fs_reg l = swizzled_result; 1214 l.reg_offset += i; 1215 1216 if (swiz == SWIZZLE_ZERO) { 1217 emit(BRW_OPCODE_MOV, l, fs_reg(0.0f)); 1218 } else if (swiz == SWIZZLE_ONE) { 1219 emit(BRW_OPCODE_MOV, l, fs_reg(1.0f)); 1220 } else { 1221 fs_reg r = orig_val; 1222 r.reg_offset += GET_SWZ(c->key.tex_swizzles[sampler], i); 1223 emit(BRW_OPCODE_MOV, l, r); 1224 } 1225 } 1226 this->result = swizzled_result; 1227 } 1228} 1229 1230void 1231fs_visitor::visit(ir_swizzle *ir) 1232{ 1233 ir->val->accept(this); 1234 fs_reg val = this->result; 1235 1236 if (ir->type->vector_elements == 1) { 1237 this->result.reg_offset += ir->mask.x; 1238 return; 1239 } 1240 1241 fs_reg result = fs_reg(this, ir->type); 1242 this->result = result; 1243 1244 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 1245 fs_reg channel = val; 1246 int swiz = 0; 1247 1248 switch (i) { 1249 case 0: 1250 swiz = ir->mask.x; 1251 break; 1252 case 1: 1253 swiz = ir->mask.y; 1254 break; 1255 case 2: 1256 swiz = ir->mask.z; 1257 break; 1258 case 3: 1259 swiz = ir->mask.w; 1260 break; 1261 } 1262 1263 channel.reg_offset += swiz; 1264 emit(BRW_OPCODE_MOV, result, channel); 1265 result.reg_offset++; 1266 } 1267} 1268 1269void 1270fs_visitor::visit(ir_discard *ir) 1271{ 1272 assert(ir->condition == NULL); /* FINISHME */ 1273 1274 emit(FS_OPCODE_DISCARD); 1275 kill_emitted = true; 1276} 1277 1278void 1279fs_visitor::visit(ir_constant *ir) 1280{ 1281 /* Set this->result to reg at the bottom of the function because some code 1282 * paths will cause this visitor to be applied to other fields. This will 1283 * cause the value stored in this->result to be modified. 1284 * 1285 * Make reg constant so that it doesn't get accidentally modified along the 1286 * way. Yes, I actually had this problem. :( 1287 */ 1288 const fs_reg reg(this, ir->type); 1289 fs_reg dst_reg = reg; 1290 1291 if (ir->type->is_array()) { 1292 const unsigned size = type_size(ir->type->fields.array); 1293 1294 for (unsigned i = 0; i < ir->type->length; i++) { 1295 ir->array_elements[i]->accept(this); 1296 fs_reg src_reg = this->result; 1297 1298 dst_reg.type = src_reg.type; 1299 for (unsigned j = 0; j < size; j++) { 1300 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1301 src_reg.reg_offset++; 1302 dst_reg.reg_offset++; 1303 } 1304 } 1305 } else if (ir->type->is_record()) { 1306 foreach_list(node, &ir->components) { 1307 ir_instruction *const field = (ir_instruction *) node; 1308 const unsigned size = type_size(field->type); 1309 1310 field->accept(this); 1311 fs_reg src_reg = this->result; 1312 1313 dst_reg.type = src_reg.type; 1314 for (unsigned j = 0; j < size; j++) { 1315 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1316 src_reg.reg_offset++; 1317 dst_reg.reg_offset++; 1318 } 1319 } 1320 } else { 1321 const unsigned size = type_size(ir->type); 1322 1323 for (unsigned i = 0; i < size; i++) { 1324 switch (ir->type->base_type) { 1325 case GLSL_TYPE_FLOAT: 1326 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i])); 1327 break; 1328 case GLSL_TYPE_UINT: 1329 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i])); 1330 break; 1331 case GLSL_TYPE_INT: 1332 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.i[i])); 1333 break; 1334 case GLSL_TYPE_BOOL: 1335 emit(BRW_OPCODE_MOV, dst_reg, fs_reg((int)ir->value.b[i])); 1336 break; 1337 default: 1338 assert(!"Non-float/uint/int/bool constant"); 1339 } 1340 dst_reg.reg_offset++; 1341 } 1342 } 1343 1344 this->result = reg; 1345} 1346 1347void 1348fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir) 1349{ 1350 ir_expression *expr = ir->as_expression(); 1351 1352 if (expr) { 1353 fs_reg op[2]; 1354 fs_inst *inst; 1355 1356 assert(expr->get_num_operands() <= 2); 1357 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1358 assert(expr->operands[i]->type->is_scalar()); 1359 1360 expr->operands[i]->accept(this); 1361 op[i] = this->result; 1362 } 1363 1364 switch (expr->operation) { 1365 case ir_unop_logic_not: 1366 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1)); 1367 inst->conditional_mod = BRW_CONDITIONAL_Z; 1368 break; 1369 1370 case ir_binop_logic_xor: 1371 inst = emit(BRW_OPCODE_XOR, reg_null_d, op[0], op[1]); 1372 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1373 break; 1374 1375 case ir_binop_logic_or: 1376 inst = emit(BRW_OPCODE_OR, reg_null_d, op[0], op[1]); 1377 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1378 break; 1379 1380 case ir_binop_logic_and: 1381 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], op[1]); 1382 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1383 break; 1384 1385 case ir_unop_f2b: 1386 if (intel->gen >= 6) { 1387 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0.0f)); 1388 } else { 1389 inst = emit(BRW_OPCODE_MOV, reg_null_f, op[0]); 1390 } 1391 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1392 break; 1393 1394 case ir_unop_i2b: 1395 if (intel->gen >= 6) { 1396 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0)); 1397 } else { 1398 inst = emit(BRW_OPCODE_MOV, reg_null_d, op[0]); 1399 } 1400 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1401 break; 1402 1403 case ir_binop_greater: 1404 case ir_binop_gequal: 1405 case ir_binop_less: 1406 case ir_binop_lequal: 1407 case ir_binop_equal: 1408 case ir_binop_all_equal: 1409 case ir_binop_nequal: 1410 case ir_binop_any_nequal: 1411 inst = emit(BRW_OPCODE_CMP, reg_null_cmp, op[0], op[1]); 1412 inst->conditional_mod = 1413 brw_conditional_for_comparison(expr->operation); 1414 break; 1415 1416 default: 1417 assert(!"not reached"); 1418 fail("bad cond code\n"); 1419 break; 1420 } 1421 return; 1422 } 1423 1424 ir->accept(this); 1425 1426 if (intel->gen >= 6) { 1427 fs_inst *inst = emit(BRW_OPCODE_AND, reg_null_d, this->result, fs_reg(1)); 1428 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1429 } else { 1430 fs_inst *inst = emit(BRW_OPCODE_MOV, reg_null_d, this->result); 1431 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1432 } 1433} 1434 1435/** 1436 * Emit a gen6 IF statement with the comparison folded into the IF 1437 * instruction. 1438 */ 1439void 1440fs_visitor::emit_if_gen6(ir_if *ir) 1441{ 1442 ir_expression *expr = ir->condition->as_expression(); 1443 1444 if (expr) { 1445 fs_reg op[2]; 1446 fs_inst *inst; 1447 fs_reg temp; 1448 1449 assert(expr->get_num_operands() <= 2); 1450 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1451 assert(expr->operands[i]->type->is_scalar()); 1452 1453 expr->operands[i]->accept(this); 1454 op[i] = this->result; 1455 } 1456 1457 switch (expr->operation) { 1458 case ir_unop_logic_not: 1459 inst = emit(BRW_OPCODE_IF, temp, op[0], fs_reg(0)); 1460 inst->conditional_mod = BRW_CONDITIONAL_Z; 1461 return; 1462 1463 case ir_binop_logic_xor: 1464 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1465 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1466 return; 1467 1468 case ir_binop_logic_or: 1469 temp = fs_reg(this, glsl_type::bool_type); 1470 emit(BRW_OPCODE_OR, temp, op[0], op[1]); 1471 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1472 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1473 return; 1474 1475 case ir_binop_logic_and: 1476 temp = fs_reg(this, glsl_type::bool_type); 1477 emit(BRW_OPCODE_AND, temp, op[0], op[1]); 1478 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1479 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1480 return; 1481 1482 case ir_unop_f2b: 1483 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0)); 1484 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1485 return; 1486 1487 case ir_unop_i2b: 1488 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1489 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1490 return; 1491 1492 case ir_binop_greater: 1493 case ir_binop_gequal: 1494 case ir_binop_less: 1495 case ir_binop_lequal: 1496 case ir_binop_equal: 1497 case ir_binop_all_equal: 1498 case ir_binop_nequal: 1499 case ir_binop_any_nequal: 1500 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1501 inst->conditional_mod = 1502 brw_conditional_for_comparison(expr->operation); 1503 return; 1504 default: 1505 assert(!"not reached"); 1506 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1507 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1508 fail("bad condition\n"); 1509 return; 1510 } 1511 return; 1512 } 1513 1514 ir->condition->accept(this); 1515 1516 fs_inst *inst = emit(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0)); 1517 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1518} 1519 1520void 1521fs_visitor::visit(ir_if *ir) 1522{ 1523 fs_inst *inst; 1524 1525 if (intel->gen < 6 && c->dispatch_width == 16) { 1526 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1527 } 1528 1529 /* Don't point the annotation at the if statement, because then it plus 1530 * the then and else blocks get printed. 1531 */ 1532 this->base_ir = ir->condition; 1533 1534 if (intel->gen == 6) { 1535 emit_if_gen6(ir); 1536 } else { 1537 emit_bool_to_cond_code(ir->condition); 1538 1539 inst = emit(BRW_OPCODE_IF); 1540 inst->predicated = true; 1541 } 1542 1543 foreach_list(node, &ir->then_instructions) { 1544 ir_instruction *ir = (ir_instruction *)node; 1545 this->base_ir = ir; 1546 1547 ir->accept(this); 1548 } 1549 1550 if (!ir->else_instructions.is_empty()) { 1551 emit(BRW_OPCODE_ELSE); 1552 1553 foreach_list(node, &ir->else_instructions) { 1554 ir_instruction *ir = (ir_instruction *)node; 1555 this->base_ir = ir; 1556 1557 ir->accept(this); 1558 } 1559 } 1560 1561 emit(BRW_OPCODE_ENDIF); 1562} 1563 1564void 1565fs_visitor::visit(ir_loop *ir) 1566{ 1567 fs_reg counter = reg_undef; 1568 1569 if (c->dispatch_width == 16) { 1570 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1571 } 1572 1573 if (ir->counter) { 1574 this->base_ir = ir->counter; 1575 ir->counter->accept(this); 1576 counter = *(variable_storage(ir->counter)); 1577 1578 if (ir->from) { 1579 this->base_ir = ir->from; 1580 ir->from->accept(this); 1581 1582 emit(BRW_OPCODE_MOV, counter, this->result); 1583 } 1584 } 1585 1586 emit(BRW_OPCODE_DO); 1587 1588 if (ir->to) { 1589 this->base_ir = ir->to; 1590 ir->to->accept(this); 1591 1592 fs_inst *inst = emit(BRW_OPCODE_CMP, reg_null_cmp, counter, this->result); 1593 inst->conditional_mod = brw_conditional_for_comparison(ir->cmp); 1594 1595 inst = emit(BRW_OPCODE_BREAK); 1596 inst->predicated = true; 1597 } 1598 1599 foreach_list(node, &ir->body_instructions) { 1600 ir_instruction *ir = (ir_instruction *)node; 1601 1602 this->base_ir = ir; 1603 ir->accept(this); 1604 } 1605 1606 if (ir->increment) { 1607 this->base_ir = ir->increment; 1608 ir->increment->accept(this); 1609 emit(BRW_OPCODE_ADD, counter, counter, this->result); 1610 } 1611 1612 emit(BRW_OPCODE_WHILE); 1613} 1614 1615void 1616fs_visitor::visit(ir_loop_jump *ir) 1617{ 1618 switch (ir->mode) { 1619 case ir_loop_jump::jump_break: 1620 emit(BRW_OPCODE_BREAK); 1621 break; 1622 case ir_loop_jump::jump_continue: 1623 emit(BRW_OPCODE_CONTINUE); 1624 break; 1625 } 1626} 1627 1628void 1629fs_visitor::visit(ir_call *ir) 1630{ 1631 assert(!"FINISHME"); 1632} 1633 1634void 1635fs_visitor::visit(ir_return *ir) 1636{ 1637 assert(!"FINISHME"); 1638} 1639 1640void 1641fs_visitor::visit(ir_function *ir) 1642{ 1643 /* Ignore function bodies other than main() -- we shouldn't see calls to 1644 * them since they should all be inlined before we get to ir_to_mesa. 1645 */ 1646 if (strcmp(ir->name, "main") == 0) { 1647 const ir_function_signature *sig; 1648 exec_list empty; 1649 1650 sig = ir->matching_signature(&empty); 1651 1652 assert(sig); 1653 1654 foreach_list(node, &sig->body) { 1655 ir_instruction *ir = (ir_instruction *)node; 1656 this->base_ir = ir; 1657 1658 ir->accept(this); 1659 } 1660 } 1661} 1662 1663void 1664fs_visitor::visit(ir_function_signature *ir) 1665{ 1666 assert(!"not reached"); 1667 (void)ir; 1668} 1669 1670fs_inst * 1671fs_visitor::emit(fs_inst inst) 1672{ 1673 fs_inst *list_inst = new(mem_ctx) fs_inst; 1674 *list_inst = inst; 1675 1676 if (force_uncompressed_stack > 0) 1677 list_inst->force_uncompressed = true; 1678 else if (force_sechalf_stack > 0) 1679 list_inst->force_sechalf = true; 1680 1681 list_inst->annotation = this->current_annotation; 1682 list_inst->ir = this->base_ir; 1683 1684 this->instructions.push_tail(list_inst); 1685 1686 return list_inst; 1687} 1688 1689/** Emits a dummy fragment shader consisting of magenta for bringup purposes. */ 1690void 1691fs_visitor::emit_dummy_fs() 1692{ 1693 /* Everyone's favorite color. */ 1694 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2), fs_reg(1.0f)); 1695 emit(BRW_OPCODE_MOV, fs_reg(MRF, 3), fs_reg(0.0f)); 1696 emit(BRW_OPCODE_MOV, fs_reg(MRF, 4), fs_reg(1.0f)); 1697 emit(BRW_OPCODE_MOV, fs_reg(MRF, 5), fs_reg(0.0f)); 1698 1699 fs_inst *write; 1700 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0)); 1701 write->base_mrf = 2; 1702} 1703 1704/* The register location here is relative to the start of the URB 1705 * data. It will get adjusted to be a real location before 1706 * generate_code() time. 1707 */ 1708struct brw_reg 1709fs_visitor::interp_reg(int location, int channel) 1710{ 1711 int regnr = urb_setup[location] * 2 + channel / 2; 1712 int stride = (channel & 1) * 4; 1713 1714 assert(urb_setup[location] != -1); 1715 1716 return brw_vec1_grf(regnr, stride); 1717} 1718 1719/** Emits the interpolation for the varying inputs. */ 1720void 1721fs_visitor::emit_interpolation_setup_gen4() 1722{ 1723 this->current_annotation = "compute pixel centers"; 1724 this->pixel_x = fs_reg(this, glsl_type::uint_type); 1725 this->pixel_y = fs_reg(this, glsl_type::uint_type); 1726 this->pixel_x.type = BRW_REGISTER_TYPE_UW; 1727 this->pixel_y.type = BRW_REGISTER_TYPE_UW; 1728 1729 emit(FS_OPCODE_PIXEL_X, this->pixel_x); 1730 emit(FS_OPCODE_PIXEL_Y, this->pixel_y); 1731 1732 this->current_annotation = "compute pixel deltas from v0"; 1733 if (brw->has_pln) { 1734 this->delta_x = fs_reg(this, glsl_type::vec2_type); 1735 this->delta_y = this->delta_x; 1736 this->delta_y.reg_offset++; 1737 } else { 1738 this->delta_x = fs_reg(this, glsl_type::float_type); 1739 this->delta_y = fs_reg(this, glsl_type::float_type); 1740 } 1741 emit(BRW_OPCODE_ADD, this->delta_x, 1742 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))); 1743 emit(BRW_OPCODE_ADD, this->delta_y, 1744 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))); 1745 1746 this->current_annotation = "compute pos.w and 1/pos.w"; 1747 /* Compute wpos.w. It's always in our setup, since it's needed to 1748 * interpolate the other attributes. 1749 */ 1750 this->wpos_w = fs_reg(this, glsl_type::float_type); 1751 emit(FS_OPCODE_LINTERP, wpos_w, this->delta_x, this->delta_y, 1752 interp_reg(FRAG_ATTRIB_WPOS, 3)); 1753 /* Compute the pixel 1/W value from wpos.w. */ 1754 this->pixel_w = fs_reg(this, glsl_type::float_type); 1755 emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w); 1756 this->current_annotation = NULL; 1757} 1758 1759/** Emits the interpolation for the varying inputs. */ 1760void 1761fs_visitor::emit_interpolation_setup_gen6() 1762{ 1763 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); 1764 1765 /* If the pixel centers end up used, the setup is the same as for gen4. */ 1766 this->current_annotation = "compute pixel centers"; 1767 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type); 1768 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type); 1769 int_pixel_x.type = BRW_REGISTER_TYPE_UW; 1770 int_pixel_y.type = BRW_REGISTER_TYPE_UW; 1771 emit(BRW_OPCODE_ADD, 1772 int_pixel_x, 1773 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), 1774 fs_reg(brw_imm_v(0x10101010))); 1775 emit(BRW_OPCODE_ADD, 1776 int_pixel_y, 1777 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), 1778 fs_reg(brw_imm_v(0x11001100))); 1779 1780 /* As of gen6, we can no longer mix float and int sources. We have 1781 * to turn the integer pixel centers into floats for their actual 1782 * use. 1783 */ 1784 this->pixel_x = fs_reg(this, glsl_type::float_type); 1785 this->pixel_y = fs_reg(this, glsl_type::float_type); 1786 emit(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x); 1787 emit(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y); 1788 1789 this->current_annotation = "compute pos.w"; 1790 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0)); 1791 this->wpos_w = fs_reg(this, glsl_type::float_type); 1792 emit_math(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w); 1793 1794 this->delta_x = fs_reg(brw_vec8_grf(2, 0)); 1795 this->delta_y = fs_reg(brw_vec8_grf(3, 0)); 1796 1797 this->current_annotation = NULL; 1798} 1799 1800void 1801fs_visitor::emit_color_write(int index, int first_color_mrf, fs_reg color) 1802{ 1803 int reg_width = c->dispatch_width / 8; 1804 fs_inst *inst; 1805 1806 if (c->dispatch_width == 8 || intel->gen >= 6) { 1807 /* SIMD8 write looks like: 1808 * m + 0: r0 1809 * m + 1: r1 1810 * m + 2: g0 1811 * m + 3: g1 1812 * 1813 * gen6 SIMD16 DP write looks like: 1814 * m + 0: r0 1815 * m + 1: r1 1816 * m + 2: g0 1817 * m + 3: g1 1818 * m + 4: b0 1819 * m + 5: b1 1820 * m + 6: a0 1821 * m + 7: a1 1822 */ 1823 inst = emit(BRW_OPCODE_MOV, 1824 fs_reg(MRF, first_color_mrf + index * reg_width), 1825 color); 1826 inst->saturate = c->key.clamp_fragment_color; 1827 } else { 1828 /* pre-gen6 SIMD16 single source DP write looks like: 1829 * m + 0: r0 1830 * m + 1: g0 1831 * m + 2: b0 1832 * m + 3: a0 1833 * m + 4: r1 1834 * m + 5: g1 1835 * m + 6: b1 1836 * m + 7: a1 1837 */ 1838 if (brw->has_compr4) { 1839 /* By setting the high bit of the MRF register number, we 1840 * indicate that we want COMPR4 mode - instead of doing the 1841 * usual destination + 1 for the second half we get 1842 * destination + 4. 1843 */ 1844 inst = emit(BRW_OPCODE_MOV, 1845 fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index), 1846 color); 1847 inst->saturate = c->key.clamp_fragment_color; 1848 } else { 1849 push_force_uncompressed(); 1850 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index), 1851 color); 1852 inst->saturate = c->key.clamp_fragment_color; 1853 pop_force_uncompressed(); 1854 1855 push_force_sechalf(); 1856 color.sechalf = true; 1857 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index + 4), 1858 color); 1859 inst->saturate = c->key.clamp_fragment_color; 1860 pop_force_sechalf(); 1861 color.sechalf = false; 1862 } 1863 } 1864} 1865 1866void 1867fs_visitor::emit_fb_writes() 1868{ 1869 this->current_annotation = "FB write header"; 1870 GLboolean header_present = GL_TRUE; 1871 int base_mrf = 2; 1872 int nr = base_mrf; 1873 int reg_width = c->dispatch_width / 8; 1874 1875 if (intel->gen >= 6 && 1876 !this->kill_emitted && 1877 c->key.nr_color_regions == 1) { 1878 header_present = false; 1879 } 1880 1881 if (header_present) { 1882 /* m2, m3 header */ 1883 nr += 2; 1884 } 1885 1886 if (c->aa_dest_stencil_reg) { 1887 push_force_uncompressed(); 1888 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++), 1889 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))); 1890 pop_force_uncompressed(); 1891 } 1892 1893 /* Reserve space for color. It'll be filled in per MRT below. */ 1894 int color_mrf = nr; 1895 nr += 4 * reg_width; 1896 1897 if (c->source_depth_to_render_target) { 1898 if (intel->gen == 6 && c->dispatch_width == 16) { 1899 /* For outputting oDepth on gen6, SIMD8 writes have to be 1900 * used. This would require 8-wide moves of each half to 1901 * message regs, kind of like pre-gen5 SIMD16 FB writes. 1902 * Just bail on doing so for now. 1903 */ 1904 fail("Missing support for simd16 depth writes on gen6\n"); 1905 } 1906 1907 if (c->computes_depth) { 1908 /* Hand over gl_FragDepth. */ 1909 assert(this->frag_depth); 1910 fs_reg depth = *(variable_storage(this->frag_depth)); 1911 1912 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), depth); 1913 } else { 1914 /* Pass through the payload depth. */ 1915 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1916 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))); 1917 } 1918 nr += reg_width; 1919 } 1920 1921 if (c->dest_depth_reg) { 1922 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1923 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))); 1924 nr += reg_width; 1925 } 1926 1927 fs_reg color = reg_undef; 1928 if (this->frag_color) 1929 color = *(variable_storage(this->frag_color)); 1930 else if (this->frag_data) { 1931 color = *(variable_storage(this->frag_data)); 1932 color.type = BRW_REGISTER_TYPE_F; 1933 } 1934 1935 for (int target = 0; target < c->key.nr_color_regions; target++) { 1936 this->current_annotation = ralloc_asprintf(this->mem_ctx, 1937 "FB write target %d", 1938 target); 1939 if (this->frag_color || this->frag_data) { 1940 for (int i = 0; i < 4; i++) { 1941 emit_color_write(i, color_mrf, color); 1942 color.reg_offset++; 1943 } 1944 } 1945 1946 if (this->frag_color) 1947 color.reg_offset -= 4; 1948 1949 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1950 inst->target = target; 1951 inst->base_mrf = base_mrf; 1952 inst->mlen = nr - base_mrf; 1953 if (target == c->key.nr_color_regions - 1) 1954 inst->eot = true; 1955 inst->header_present = header_present; 1956 } 1957 1958 if (c->key.nr_color_regions == 0) { 1959 if (c->key.alpha_test && (this->frag_color || this->frag_data)) { 1960 /* If the alpha test is enabled but there's no color buffer, 1961 * we still need to send alpha out the pipeline to our null 1962 * renderbuffer. 1963 */ 1964 color.reg_offset += 3; 1965 emit_color_write(3, color_mrf, color); 1966 } 1967 1968 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1969 inst->base_mrf = base_mrf; 1970 inst->mlen = nr - base_mrf; 1971 inst->eot = true; 1972 inst->header_present = header_present; 1973 } 1974 1975 this->current_annotation = NULL; 1976} 1977