brw_fs_visitor.cpp revision b633ddeb9fd951ddc49e8a3fd25a946e5a16361f
1/* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24/** @file brw_fs_visitor.cpp 25 * 26 * This file supports generating the FS LIR from the GLSL IR. The LIR 27 * makes it easier to do backend-specific optimizations than doing so 28 * in the GLSL IR or in the native code. 29 */ 30extern "C" { 31 32#include <sys/types.h> 33 34#include "main/macros.h" 35#include "main/shaderobj.h" 36#include "main/uniforms.h" 37#include "program/prog_parameter.h" 38#include "program/prog_print.h" 39#include "program/prog_optimize.h" 40#include "program/register_allocate.h" 41#include "program/sampler.h" 42#include "program/hash_table.h" 43#include "brw_context.h" 44#include "brw_eu.h" 45#include "brw_wm.h" 46} 47#include "brw_shader.h" 48#include "brw_fs.h" 49#include "../glsl/glsl_types.h" 50#include "../glsl/ir_optimization.h" 51#include "../glsl/ir_print_visitor.h" 52 53void 54fs_visitor::visit(ir_variable *ir) 55{ 56 fs_reg *reg = NULL; 57 58 if (variable_storage(ir)) 59 return; 60 61 if (strcmp(ir->name, "gl_FragColor") == 0) { 62 this->frag_color = ir; 63 } else if (strcmp(ir->name, "gl_FragData") == 0) { 64 this->frag_data = ir; 65 } else if (strcmp(ir->name, "gl_FragDepth") == 0) { 66 this->frag_depth = ir; 67 } 68 69 if (ir->mode == ir_var_in) { 70 if (!strcmp(ir->name, "gl_FragCoord")) { 71 reg = emit_fragcoord_interpolation(ir); 72 } else if (!strcmp(ir->name, "gl_FrontFacing")) { 73 reg = emit_frontfacing_interpolation(ir); 74 } else { 75 reg = emit_general_interpolation(ir); 76 } 77 assert(reg); 78 hash_table_insert(this->variable_ht, reg, ir); 79 return; 80 } 81 82 if (ir->mode == ir_var_uniform) { 83 int param_index = c->prog_data.nr_params; 84 85 if (c->dispatch_width == 16) { 86 if (!variable_storage(ir)) { 87 fail("Failed to find uniform '%s' in 16-wide\n", ir->name); 88 } 89 return; 90 } 91 92 if (!strncmp(ir->name, "gl_", 3)) { 93 setup_builtin_uniform_values(ir); 94 } else { 95 setup_uniform_values(ir->location, ir->type); 96 } 97 98 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index); 99 reg->type = brw_type_for_base_type(ir->type); 100 } 101 102 if (!reg) 103 reg = new(this->mem_ctx) fs_reg(this, ir->type); 104 105 hash_table_insert(this->variable_ht, reg, ir); 106} 107 108void 109fs_visitor::visit(ir_dereference_variable *ir) 110{ 111 fs_reg *reg = variable_storage(ir->var); 112 this->result = *reg; 113} 114 115void 116fs_visitor::visit(ir_dereference_record *ir) 117{ 118 const glsl_type *struct_type = ir->record->type; 119 120 ir->record->accept(this); 121 122 unsigned int offset = 0; 123 for (unsigned int i = 0; i < struct_type->length; i++) { 124 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0) 125 break; 126 offset += type_size(struct_type->fields.structure[i].type); 127 } 128 this->result.reg_offset += offset; 129 this->result.type = brw_type_for_base_type(ir->type); 130} 131 132void 133fs_visitor::visit(ir_dereference_array *ir) 134{ 135 ir_constant *index; 136 int element_size; 137 138 ir->array->accept(this); 139 index = ir->array_index->as_constant(); 140 141 element_size = type_size(ir->type); 142 this->result.type = brw_type_for_base_type(ir->type); 143 144 if (index) { 145 assert(this->result.file == UNIFORM || 146 (this->result.file == GRF && 147 this->result.reg != 0)); 148 this->result.reg_offset += index->value.i[0] * element_size; 149 } else { 150 assert(!"FINISHME: non-constant array element"); 151 } 152} 153 154/* Instruction selection: Produce a MOV.sat instead of 155 * MIN(MAX(val, 0), 1) when possible. 156 */ 157bool 158fs_visitor::try_emit_saturate(ir_expression *ir) 159{ 160 ir_rvalue *sat_val = ir->as_rvalue_to_saturate(); 161 162 if (!sat_val) 163 return false; 164 165 this->result = reg_undef; 166 sat_val->accept(this); 167 fs_reg src = this->result; 168 169 this->result = fs_reg(this, ir->type); 170 fs_inst *inst = emit(BRW_OPCODE_MOV, this->result, src); 171 inst->saturate = true; 172 173 return true; 174} 175 176void 177fs_visitor::visit(ir_expression *ir) 178{ 179 unsigned int operand; 180 fs_reg op[2], temp; 181 fs_inst *inst; 182 183 assert(ir->get_num_operands() <= 2); 184 185 if (try_emit_saturate(ir)) 186 return; 187 188 /* This is where our caller would like us to put the result, if possible. */ 189 fs_reg saved_result_storage = this->result; 190 191 for (operand = 0; operand < ir->get_num_operands(); operand++) { 192 this->result = reg_undef; 193 ir->operands[operand]->accept(this); 194 if (this->result.file == BAD_FILE) { 195 ir_print_visitor v; 196 fail("Failed to get tree for expression operand:\n"); 197 ir->operands[operand]->accept(&v); 198 } 199 op[operand] = this->result; 200 201 /* Matrix expression operands should have been broken down to vector 202 * operations already. 203 */ 204 assert(!ir->operands[operand]->type->is_matrix()); 205 /* And then those vector operands should have been broken down to scalar. 206 */ 207 assert(!ir->operands[operand]->type->is_vector()); 208 } 209 210 /* Inherit storage from our parent if possible, and otherwise we 211 * alloc a temporary. 212 */ 213 if (saved_result_storage.file == BAD_FILE) { 214 this->result = fs_reg(this, ir->type); 215 } else { 216 this->result = saved_result_storage; 217 } 218 219 switch (ir->operation) { 220 case ir_unop_logic_not: 221 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is 222 * ones complement of the whole register, not just bit 0. 223 */ 224 emit(BRW_OPCODE_XOR, this->result, op[0], fs_reg(1)); 225 break; 226 case ir_unop_neg: 227 op[0].negate = !op[0].negate; 228 this->result = op[0]; 229 break; 230 case ir_unop_abs: 231 op[0].abs = true; 232 op[0].negate = false; 233 this->result = op[0]; 234 break; 235 case ir_unop_sign: 236 temp = fs_reg(this, ir->type); 237 238 /* Unalias the destination. (imagine a = sign(a)) */ 239 this->result = fs_reg(this, ir->type); 240 241 emit(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)); 242 243 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 244 inst->conditional_mod = BRW_CONDITIONAL_G; 245 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)); 246 inst->predicated = true; 247 248 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 249 inst->conditional_mod = BRW_CONDITIONAL_L; 250 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)); 251 inst->predicated = true; 252 253 break; 254 case ir_unop_rcp: 255 emit_math(FS_OPCODE_RCP, this->result, op[0]); 256 break; 257 258 case ir_unop_exp2: 259 emit_math(FS_OPCODE_EXP2, this->result, op[0]); 260 break; 261 case ir_unop_log2: 262 emit_math(FS_OPCODE_LOG2, this->result, op[0]); 263 break; 264 case ir_unop_exp: 265 case ir_unop_log: 266 assert(!"not reached: should be handled by ir_explog_to_explog2"); 267 break; 268 case ir_unop_sin: 269 case ir_unop_sin_reduced: 270 emit_math(FS_OPCODE_SIN, this->result, op[0]); 271 break; 272 case ir_unop_cos: 273 case ir_unop_cos_reduced: 274 emit_math(FS_OPCODE_COS, this->result, op[0]); 275 break; 276 277 case ir_unop_dFdx: 278 emit(FS_OPCODE_DDX, this->result, op[0]); 279 break; 280 case ir_unop_dFdy: 281 emit(FS_OPCODE_DDY, this->result, op[0]); 282 break; 283 284 case ir_binop_add: 285 emit(BRW_OPCODE_ADD, this->result, op[0], op[1]); 286 break; 287 case ir_binop_sub: 288 assert(!"not reached: should be handled by ir_sub_to_add_neg"); 289 break; 290 291 case ir_binop_mul: 292 emit(BRW_OPCODE_MUL, this->result, op[0], op[1]); 293 break; 294 case ir_binop_div: 295 assert(!"not reached: should be handled by ir_div_to_mul_rcp"); 296 break; 297 case ir_binop_mod: 298 assert(!"ir_binop_mod should have been converted to b * fract(a/b)"); 299 break; 300 301 case ir_binop_less: 302 case ir_binop_greater: 303 case ir_binop_lequal: 304 case ir_binop_gequal: 305 case ir_binop_equal: 306 case ir_binop_all_equal: 307 case ir_binop_nequal: 308 case ir_binop_any_nequal: 309 temp = this->result; 310 /* original gen4 does implicit conversion before comparison. */ 311 if (intel->gen < 5) 312 temp.type = op[0].type; 313 314 inst = emit(BRW_OPCODE_CMP, temp, op[0], op[1]); 315 inst->conditional_mod = brw_conditional_for_comparison(ir->operation); 316 emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)); 317 break; 318 319 case ir_binop_logic_xor: 320 emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 321 break; 322 323 case ir_binop_logic_or: 324 emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 325 break; 326 327 case ir_binop_logic_and: 328 emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 329 break; 330 331 case ir_binop_dot: 332 case ir_unop_any: 333 assert(!"not reached: should be handled by brw_fs_channel_expressions"); 334 break; 335 336 case ir_unop_noise: 337 assert(!"not reached: should be handled by lower_noise"); 338 break; 339 340 case ir_quadop_vector: 341 assert(!"not reached: should be handled by lower_quadop_vector"); 342 break; 343 344 case ir_unop_sqrt: 345 emit_math(FS_OPCODE_SQRT, this->result, op[0]); 346 break; 347 348 case ir_unop_rsq: 349 emit_math(FS_OPCODE_RSQ, this->result, op[0]); 350 break; 351 352 case ir_unop_i2u: 353 op[0].type = BRW_REGISTER_TYPE_UD; 354 this->result = op[0]; 355 break; 356 case ir_unop_u2i: 357 op[0].type = BRW_REGISTER_TYPE_D; 358 this->result = op[0]; 359 break; 360 case ir_unop_i2f: 361 case ir_unop_b2f: 362 case ir_unop_b2i: 363 case ir_unop_f2i: 364 emit(BRW_OPCODE_MOV, this->result, op[0]); 365 break; 366 case ir_unop_f2b: 367 case ir_unop_i2b: 368 temp = this->result; 369 /* original gen4 does implicit conversion before comparison. */ 370 if (intel->gen < 5) 371 temp.type = op[0].type; 372 373 inst = emit(BRW_OPCODE_CMP, temp, op[0], fs_reg(0.0f)); 374 inst->conditional_mod = BRW_CONDITIONAL_NZ; 375 inst = emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(1)); 376 break; 377 378 case ir_unop_trunc: 379 emit(BRW_OPCODE_RNDZ, this->result, op[0]); 380 break; 381 case ir_unop_ceil: 382 op[0].negate = !op[0].negate; 383 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 384 this->result.negate = true; 385 break; 386 case ir_unop_floor: 387 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 388 break; 389 case ir_unop_fract: 390 inst = emit(BRW_OPCODE_FRC, this->result, op[0]); 391 break; 392 case ir_unop_round_even: 393 emit(BRW_OPCODE_RNDE, this->result, op[0]); 394 break; 395 396 case ir_binop_min: 397 if (intel->gen >= 6) { 398 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 399 inst->conditional_mod = BRW_CONDITIONAL_L; 400 } else { 401 /* Unalias the destination */ 402 this->result = fs_reg(this, ir->type); 403 404 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 405 inst->conditional_mod = BRW_CONDITIONAL_L; 406 407 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 408 inst->predicated = true; 409 } 410 break; 411 case ir_binop_max: 412 if (intel->gen >= 6) { 413 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 414 inst->conditional_mod = BRW_CONDITIONAL_GE; 415 } else { 416 /* Unalias the destination */ 417 this->result = fs_reg(this, ir->type); 418 419 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 420 inst->conditional_mod = BRW_CONDITIONAL_G; 421 422 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 423 inst->predicated = true; 424 } 425 break; 426 427 case ir_binop_pow: 428 emit_math(FS_OPCODE_POW, this->result, op[0], op[1]); 429 break; 430 431 case ir_unop_bit_not: 432 inst = emit(BRW_OPCODE_NOT, this->result, op[0]); 433 break; 434 case ir_binop_bit_and: 435 inst = emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 436 break; 437 case ir_binop_bit_xor: 438 inst = emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 439 break; 440 case ir_binop_bit_or: 441 inst = emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 442 break; 443 444 case ir_unop_u2f: 445 case ir_binop_lshift: 446 case ir_binop_rshift: 447 assert(!"GLSL 1.30 features unsupported"); 448 break; 449 } 450} 451 452void 453fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r, 454 const glsl_type *type, bool predicated) 455{ 456 switch (type->base_type) { 457 case GLSL_TYPE_FLOAT: 458 case GLSL_TYPE_UINT: 459 case GLSL_TYPE_INT: 460 case GLSL_TYPE_BOOL: 461 for (unsigned int i = 0; i < type->components(); i++) { 462 l.type = brw_type_for_base_type(type); 463 r.type = brw_type_for_base_type(type); 464 465 if (predicated || !l.equals(&r)) { 466 fs_inst *inst = emit(BRW_OPCODE_MOV, l, r); 467 inst->predicated = predicated; 468 } 469 470 l.reg_offset++; 471 r.reg_offset++; 472 } 473 break; 474 case GLSL_TYPE_ARRAY: 475 for (unsigned int i = 0; i < type->length; i++) { 476 emit_assignment_writes(l, r, type->fields.array, predicated); 477 } 478 break; 479 480 case GLSL_TYPE_STRUCT: 481 for (unsigned int i = 0; i < type->length; i++) { 482 emit_assignment_writes(l, r, type->fields.structure[i].type, 483 predicated); 484 } 485 break; 486 487 case GLSL_TYPE_SAMPLER: 488 break; 489 490 default: 491 assert(!"not reached"); 492 break; 493 } 494} 495 496void 497fs_visitor::visit(ir_assignment *ir) 498{ 499 struct fs_reg l, r; 500 fs_inst *inst; 501 502 /* FINISHME: arrays on the lhs */ 503 this->result = reg_undef; 504 ir->lhs->accept(this); 505 l = this->result; 506 507 /* If we're doing a direct assignment, an RHS expression could 508 * drop its result right into our destination. Otherwise, tell it 509 * not to. 510 */ 511 if (ir->condition || 512 !(ir->lhs->type->is_scalar() || 513 (ir->lhs->type->is_vector() && 514 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1))) { 515 this->result = reg_undef; 516 } 517 518 ir->rhs->accept(this); 519 r = this->result; 520 521 assert(l.file != BAD_FILE); 522 assert(r.file != BAD_FILE); 523 524 if (ir->condition) { 525 emit_bool_to_cond_code(ir->condition); 526 } 527 528 if (ir->lhs->type->is_scalar() || 529 ir->lhs->type->is_vector()) { 530 for (int i = 0; i < ir->lhs->type->vector_elements; i++) { 531 if (ir->write_mask & (1 << i)) { 532 if (ir->condition) { 533 inst = emit(BRW_OPCODE_MOV, l, r); 534 inst->predicated = true; 535 } else if (!l.equals(&r)) { 536 inst = emit(BRW_OPCODE_MOV, l, r); 537 } 538 539 r.reg_offset++; 540 } 541 l.reg_offset++; 542 } 543 } else { 544 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL); 545 } 546} 547 548fs_inst * 549fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate, 550 int sampler) 551{ 552 int mlen; 553 int base_mrf = 1; 554 bool simd16 = false; 555 fs_reg orig_dst; 556 557 /* g0 header. */ 558 mlen = 1; 559 560 if (ir->shadow_comparitor && ir->op != ir_txd) { 561 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 562 fs_inst *inst = emit(BRW_OPCODE_MOV, 563 fs_reg(MRF, base_mrf + mlen + i), coordinate); 564 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 565 inst->saturate = true; 566 567 coordinate.reg_offset++; 568 } 569 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 570 mlen += 3; 571 572 if (ir->op == ir_tex) { 573 /* There's no plain shadow compare message, so we use shadow 574 * compare with a bias of 0.0. 575 */ 576 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)); 577 mlen++; 578 } else if (ir->op == ir_txb) { 579 this->result = reg_undef; 580 ir->lod_info.bias->accept(this); 581 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 582 mlen++; 583 } else { 584 assert(ir->op == ir_txl); 585 this->result = reg_undef; 586 ir->lod_info.lod->accept(this); 587 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 588 mlen++; 589 } 590 591 this->result = reg_undef; 592 ir->shadow_comparitor->accept(this); 593 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 594 mlen++; 595 } else if (ir->op == ir_tex) { 596 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 597 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), 598 coordinate); 599 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 600 inst->saturate = true; 601 coordinate.reg_offset++; 602 } 603 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 604 mlen += 3; 605 } else if (ir->op == ir_txd) { 606 ir->lod_info.grad.dPdx->accept(this); 607 fs_reg dPdx = this->result; 608 609 ir->lod_info.grad.dPdy->accept(this); 610 fs_reg dPdy = this->result; 611 612 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 613 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); 614 coordinate.reg_offset++; 615 } 616 /* the slots for u and v are always present, but r is optional */ 617 mlen += MAX2(ir->coordinate->type->vector_elements, 2); 618 619 /* P = u, v, r 620 * dPdx = dudx, dvdx, drdx 621 * dPdy = dudy, dvdy, drdy 622 * 623 * 2-arg: dudx dvdx dudy dvdy 624 * dPdx.x dPdx.y dPdy.x dPdy.y 625 * m4 m5 m6 m7 626 * 627 * 3-arg: dudx dvdx drdx dudy dvdy drdy 628 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z 629 * m5 m6 m7 m8 m9 m10 630 */ 631 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 632 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 633 dPdx.reg_offset++; 634 mlen++; 635 } 636 637 for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) { 638 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 639 dPdy.reg_offset++; 640 mlen++; 641 } 642 } else { 643 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod 644 * instructions. We'll need to do SIMD16 here. 645 */ 646 assert(ir->op == ir_txb || ir->op == ir_txl); 647 648 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 649 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, 650 base_mrf + mlen + i * 2), 651 coordinate); 652 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 653 inst->saturate = true; 654 coordinate.reg_offset++; 655 } 656 657 /* lod/bias appears after u/v/r. */ 658 mlen += 6; 659 660 if (ir->op == ir_txb) { 661 this->result = reg_undef; 662 ir->lod_info.bias->accept(this); 663 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 664 mlen++; 665 } else { 666 this->result = reg_undef; 667 ir->lod_info.lod->accept(this); 668 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 669 mlen++; 670 } 671 672 /* The unused upper half. */ 673 mlen++; 674 675 /* Now, since we're doing simd16, the return is 2 interleaved 676 * vec4s where the odd-indexed ones are junk. We'll need to move 677 * this weirdness around to the expected layout. 678 */ 679 simd16 = true; 680 orig_dst = dst; 681 dst = fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type, 682 2)); 683 dst.type = BRW_REGISTER_TYPE_F; 684 } 685 686 fs_inst *inst = NULL; 687 switch (ir->op) { 688 case ir_tex: 689 inst = emit(FS_OPCODE_TEX, dst); 690 break; 691 case ir_txb: 692 inst = emit(FS_OPCODE_TXB, dst); 693 break; 694 case ir_txl: 695 inst = emit(FS_OPCODE_TXL, dst); 696 break; 697 case ir_txd: 698 inst = emit(FS_OPCODE_TXD, dst); 699 break; 700 case ir_txf: 701 assert(!"GLSL 1.30 features unsupported"); 702 break; 703 } 704 inst->base_mrf = base_mrf; 705 inst->mlen = mlen; 706 inst->header_present = true; 707 708 if (simd16) { 709 for (int i = 0; i < 4; i++) { 710 emit(BRW_OPCODE_MOV, orig_dst, dst); 711 orig_dst.reg_offset++; 712 dst.reg_offset += 2; 713 } 714 } 715 716 return inst; 717} 718 719/* gen5's sampler has slots for u, v, r, array index, then optional 720 * parameters like shadow comparitor or LOD bias. If optional 721 * parameters aren't present, those base slots are optional and don't 722 * need to be included in the message. 723 * 724 * We don't fill in the unnecessary slots regardless, which may look 725 * surprising in the disassembly. 726 */ 727fs_inst * 728fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate, 729 int sampler) 730{ 731 int mlen = 0; 732 int base_mrf = 2; 733 int reg_width = c->dispatch_width / 8; 734 bool header_present = false; 735 736 if (ir->offset) { 737 /* The offsets set up by the ir_texture visitor are in the 738 * m1 header, so we can't go headerless. 739 */ 740 header_present = true; 741 mlen++; 742 base_mrf--; 743 } 744 745 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 746 fs_inst *inst = emit(BRW_OPCODE_MOV, 747 fs_reg(MRF, base_mrf + mlen + i * reg_width), 748 coordinate); 749 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 750 inst->saturate = true; 751 coordinate.reg_offset++; 752 } 753 mlen += ir->coordinate->type->vector_elements * reg_width; 754 755 if (ir->shadow_comparitor && ir->op != ir_txd) { 756 mlen = MAX2(mlen, header_present + 4 * reg_width); 757 758 this->result = reg_undef; 759 ir->shadow_comparitor->accept(this); 760 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 761 mlen += reg_width; 762 } 763 764 fs_inst *inst = NULL; 765 switch (ir->op) { 766 case ir_tex: 767 inst = emit(FS_OPCODE_TEX, dst); 768 break; 769 case ir_txb: 770 this->result = reg_undef; 771 ir->lod_info.bias->accept(this); 772 mlen = MAX2(mlen, header_present + 4 * reg_width); 773 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 774 mlen += reg_width; 775 776 inst = emit(FS_OPCODE_TXB, dst); 777 778 break; 779 case ir_txl: 780 this->result = reg_undef; 781 ir->lod_info.lod->accept(this); 782 mlen = MAX2(mlen, header_present + 4 * reg_width); 783 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 784 mlen += reg_width; 785 786 inst = emit(FS_OPCODE_TXL, dst); 787 break; 788 case ir_txd: { 789 ir->lod_info.grad.dPdx->accept(this); 790 fs_reg dPdx = this->result; 791 792 ir->lod_info.grad.dPdy->accept(this); 793 fs_reg dPdy = this->result; 794 795 mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */ 796 797 /** 798 * P = u, v, r 799 * dPdx = dudx, dvdx, drdx 800 * dPdy = dudy, dvdy, drdy 801 * 802 * Load up these values: 803 * - dudx dudy dvdx dvdy drdx drdy 804 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z 805 */ 806 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 807 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 808 dPdx.reg_offset++; 809 mlen += reg_width; 810 811 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 812 dPdy.reg_offset++; 813 mlen += reg_width; 814 } 815 816 inst = emit(FS_OPCODE_TXD, dst); 817 break; 818 } 819 case ir_txf: 820 assert(!"GLSL 1.30 features unsupported"); 821 break; 822 } 823 inst->base_mrf = base_mrf; 824 inst->mlen = mlen; 825 inst->header_present = header_present; 826 827 if (mlen > 11) { 828 fail("Message length >11 disallowed by hardware\n"); 829 } 830 831 return inst; 832} 833 834fs_inst * 835fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate, 836 int sampler) 837{ 838 int mlen = 0; 839 int base_mrf = 2; 840 int reg_width = c->dispatch_width / 8; 841 bool header_present = false; 842 843 if (ir->offset) { 844 /* The offsets set up by the ir_texture visitor are in the 845 * m1 header, so we can't go headerless. 846 */ 847 header_present = true; 848 mlen++; 849 base_mrf--; 850 } 851 852 if (ir->shadow_comparitor && ir->op != ir_txd) { 853 ir->shadow_comparitor->accept(this); 854 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 855 mlen += reg_width; 856 } 857 858 /* Set up the LOD info */ 859 switch (ir->op) { 860 case ir_tex: 861 break; 862 case ir_txb: 863 ir->lod_info.bias->accept(this); 864 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 865 mlen += reg_width; 866 break; 867 case ir_txl: 868 ir->lod_info.lod->accept(this); 869 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 870 mlen += reg_width; 871 break; 872 case ir_txd: { 873 if (c->dispatch_width == 16) 874 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode."); 875 876 ir->lod_info.grad.dPdx->accept(this); 877 fs_reg dPdx = this->result; 878 879 ir->lod_info.grad.dPdy->accept(this); 880 fs_reg dPdy = this->result; 881 882 /* Load dPdx and the coordinate together: 883 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z 884 */ 885 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 886 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 887 coordinate); 888 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 889 inst->saturate = true; 890 coordinate.reg_offset++; 891 mlen += reg_width; 892 893 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 894 dPdx.reg_offset++; 895 mlen += reg_width; 896 897 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 898 dPdy.reg_offset++; 899 mlen += reg_width; 900 } 901 break; 902 } 903 case ir_txf: 904 assert(!"GLSL 1.30 features unsupported"); 905 break; 906 } 907 908 /* Set up the coordinate (except for TXD where it was done earlier) */ 909 if (ir->op != ir_txd) { 910 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 911 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 912 coordinate); 913 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 914 inst->saturate = true; 915 coordinate.reg_offset++; 916 mlen += reg_width; 917 } 918 } 919 920 /* Generate the SEND */ 921 fs_inst *inst = NULL; 922 switch (ir->op) { 923 case ir_tex: inst = emit(FS_OPCODE_TEX, dst); break; 924 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break; 925 case ir_txl: inst = emit(FS_OPCODE_TXL, dst); break; 926 case ir_txd: inst = emit(FS_OPCODE_TXD, dst); break; 927 case ir_txf: assert(!"TXF unsupported."); 928 } 929 inst->base_mrf = base_mrf; 930 inst->mlen = mlen; 931 inst->header_present = header_present; 932 933 if (mlen > 11) { 934 fail("Message length >11 disallowed by hardware\n"); 935 } 936 937 return inst; 938} 939 940void 941fs_visitor::visit(ir_texture *ir) 942{ 943 fs_inst *inst = NULL; 944 945 int sampler = _mesa_get_sampler_uniform_value(ir->sampler, prog, &fp->Base); 946 sampler = fp->Base.SamplerUnits[sampler]; 947 948 /* Our hardware doesn't have a sample_d_c message, so shadow compares 949 * for textureGrad/TXD need to be emulated with instructions. 950 */ 951 bool hw_compare_supported = ir->op != ir_txd; 952 if (ir->shadow_comparitor && !hw_compare_supported) { 953 assert(c->key.compare_funcs[sampler] != GL_NONE); 954 /* No need to even sample for GL_ALWAYS or GL_NEVER...bail early */ 955 if (c->key.compare_funcs[sampler] == GL_ALWAYS) 956 return swizzle_result(ir, fs_reg(1.0f), sampler); 957 else if (c->key.compare_funcs[sampler] == GL_NEVER) 958 return swizzle_result(ir, fs_reg(0.0f), sampler); 959 } 960 961 this->result = reg_undef; 962 ir->coordinate->accept(this); 963 fs_reg coordinate = this->result; 964 965 if (ir->offset != NULL) { 966 ir_constant *offset = ir->offset->as_constant(); 967 assert(offset != NULL); 968 969 signed char offsets[3]; 970 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) 971 offsets[i] = (signed char) offset->value.i[i]; 972 973 /* Combine all three offsets into a single unsigned dword: 974 * 975 * bits 11:8 - U Offset (X component) 976 * bits 7:4 - V Offset (Y component) 977 * bits 3:0 - R Offset (Z component) 978 */ 979 unsigned offset_bits = 0; 980 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) { 981 const unsigned shift = 4 * (2 - i); 982 offset_bits |= (offsets[i] << shift) & (0xF << shift); 983 } 984 985 /* Explicitly set up the message header by copying g0 to msg reg m1. */ 986 emit(BRW_OPCODE_MOV, fs_reg(MRF, 1, BRW_REGISTER_TYPE_UD), 987 fs_reg(GRF, 0, BRW_REGISTER_TYPE_UD)); 988 989 /* Then set the offset bits in DWord 2 of the message header. */ 990 emit(BRW_OPCODE_MOV, 991 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 1, 2), 992 BRW_REGISTER_TYPE_UD)), 993 fs_reg(brw_imm_uw(offset_bits))); 994 } 995 996 /* Should be lowered by do_lower_texture_projection */ 997 assert(!ir->projector); 998 999 /* The 965 requires the EU to do the normalization of GL rectangle 1000 * texture coordinates. We use the program parameter state 1001 * tracking to get the scaling factor. 1002 */ 1003 if (ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) { 1004 struct gl_program_parameter_list *params = c->fp->program.Base.Parameters; 1005 int tokens[STATE_LENGTH] = { 1006 STATE_INTERNAL, 1007 STATE_TEXRECT_SCALE, 1008 sampler, 1009 0, 1010 0 1011 }; 1012 1013 if (c->dispatch_width == 16) { 1014 fail("rectangle scale uniform setup not supported on 16-wide\n"); 1015 this->result = fs_reg(this, ir->type); 1016 return; 1017 } 1018 1019 c->prog_data.param_convert[c->prog_data.nr_params] = 1020 PARAM_NO_CONVERT; 1021 c->prog_data.param_convert[c->prog_data.nr_params + 1] = 1022 PARAM_NO_CONVERT; 1023 1024 fs_reg scale_x = fs_reg(UNIFORM, c->prog_data.nr_params); 1025 fs_reg scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1); 1026 GLuint index = _mesa_add_state_reference(params, 1027 (gl_state_index *)tokens); 1028 1029 this->param_index[c->prog_data.nr_params] = index; 1030 this->param_offset[c->prog_data.nr_params] = 0; 1031 c->prog_data.nr_params++; 1032 this->param_index[c->prog_data.nr_params] = index; 1033 this->param_offset[c->prog_data.nr_params] = 1; 1034 c->prog_data.nr_params++; 1035 1036 fs_reg dst = fs_reg(this, ir->coordinate->type); 1037 fs_reg src = coordinate; 1038 coordinate = dst; 1039 1040 emit(BRW_OPCODE_MUL, dst, src, scale_x); 1041 dst.reg_offset++; 1042 src.reg_offset++; 1043 emit(BRW_OPCODE_MUL, dst, src, scale_y); 1044 } 1045 1046 /* Writemasking doesn't eliminate channels on SIMD8 texture 1047 * samples, so don't worry about them. 1048 */ 1049 fs_reg dst = fs_reg(this, glsl_type::vec4_type); 1050 1051 if (intel->gen >= 7) { 1052 inst = emit_texture_gen7(ir, dst, coordinate, sampler); 1053 } else if (intel->gen >= 5) { 1054 inst = emit_texture_gen5(ir, dst, coordinate, sampler); 1055 } else { 1056 inst = emit_texture_gen4(ir, dst, coordinate, sampler); 1057 } 1058 1059 /* If there's an offset, we already set up m1. To avoid the implied move, 1060 * use the null register. Otherwise, we want an implied move from g0. 1061 */ 1062 if (ir->offset != NULL || !inst->header_present) 1063 inst->src[0] = reg_undef; 1064 else 1065 inst->src[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW)); 1066 1067 inst->sampler = sampler; 1068 1069 if (ir->shadow_comparitor) { 1070 if (hw_compare_supported) { 1071 inst->shadow_compare = true; 1072 } else { 1073 ir->shadow_comparitor->accept(this); 1074 fs_reg ref = this->result; 1075 1076 fs_reg value = dst; 1077 dst = fs_reg(this, glsl_type::vec4_type); 1078 1079 /* FINISHME: This needs to be done pre-filtering. */ 1080 1081 uint32_t conditional = 0; 1082 switch (c->key.compare_funcs[sampler]) { 1083 /* GL_ALWAYS and GL_NEVER were handled at the top of the function */ 1084 case GL_LESS: conditional = BRW_CONDITIONAL_L; break; 1085 case GL_GREATER: conditional = BRW_CONDITIONAL_G; break; 1086 case GL_LEQUAL: conditional = BRW_CONDITIONAL_LE; break; 1087 case GL_GEQUAL: conditional = BRW_CONDITIONAL_GE; break; 1088 case GL_EQUAL: conditional = BRW_CONDITIONAL_EQ; break; 1089 case GL_NOTEQUAL: conditional = BRW_CONDITIONAL_NEQ; break; 1090 default: assert(!"Should not get here: bad shadow compare function"); 1091 } 1092 1093 /* Use conditional moves to load 0 or 1 as the result */ 1094 this->current_annotation = "manual shadow comparison"; 1095 for (int i = 0; i < 4; i++) { 1096 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(0.0f)); 1097 1098 inst = emit(BRW_OPCODE_CMP, reg_null_f, ref, value); 1099 inst->conditional_mod = conditional; 1100 1101 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(1.0f)); 1102 inst->predicated = true; 1103 1104 dst.reg_offset++; 1105 value.reg_offset++; 1106 } 1107 dst.reg_offset = 0; 1108 } 1109 } 1110 1111 swizzle_result(ir, dst, sampler); 1112} 1113 1114/** 1115 * Swizzle the result of a texture result. This is necessary for 1116 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons. 1117 */ 1118void 1119fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler) 1120{ 1121 this->result = orig_val; 1122 1123 if (ir->type == glsl_type::float_type) { 1124 /* Ignore DEPTH_TEXTURE_MODE swizzling. */ 1125 assert(ir->sampler->type->sampler_shadow); 1126 } else if (c->key.tex_swizzles[sampler] != SWIZZLE_NOOP) { 1127 fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type); 1128 1129 for (int i = 0; i < 4; i++) { 1130 int swiz = GET_SWZ(c->key.tex_swizzles[sampler], i); 1131 fs_reg l = swizzled_result; 1132 l.reg_offset += i; 1133 1134 if (swiz == SWIZZLE_ZERO) { 1135 emit(BRW_OPCODE_MOV, l, fs_reg(0.0f)); 1136 } else if (swiz == SWIZZLE_ONE) { 1137 emit(BRW_OPCODE_MOV, l, fs_reg(1.0f)); 1138 } else { 1139 fs_reg r = orig_val; 1140 r.reg_offset += GET_SWZ(c->key.tex_swizzles[sampler], i); 1141 emit(BRW_OPCODE_MOV, l, r); 1142 } 1143 } 1144 this->result = swizzled_result; 1145 } 1146} 1147 1148void 1149fs_visitor::visit(ir_swizzle *ir) 1150{ 1151 this->result = reg_undef; 1152 ir->val->accept(this); 1153 fs_reg val = this->result; 1154 1155 if (ir->type->vector_elements == 1) { 1156 this->result.reg_offset += ir->mask.x; 1157 return; 1158 } 1159 1160 fs_reg result = fs_reg(this, ir->type); 1161 this->result = result; 1162 1163 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 1164 fs_reg channel = val; 1165 int swiz = 0; 1166 1167 switch (i) { 1168 case 0: 1169 swiz = ir->mask.x; 1170 break; 1171 case 1: 1172 swiz = ir->mask.y; 1173 break; 1174 case 2: 1175 swiz = ir->mask.z; 1176 break; 1177 case 3: 1178 swiz = ir->mask.w; 1179 break; 1180 } 1181 1182 channel.reg_offset += swiz; 1183 emit(BRW_OPCODE_MOV, result, channel); 1184 result.reg_offset++; 1185 } 1186} 1187 1188void 1189fs_visitor::visit(ir_discard *ir) 1190{ 1191 assert(ir->condition == NULL); /* FINISHME */ 1192 1193 emit(FS_OPCODE_DISCARD); 1194 kill_emitted = true; 1195} 1196 1197void 1198fs_visitor::visit(ir_constant *ir) 1199{ 1200 /* Set this->result to reg at the bottom of the function because some code 1201 * paths will cause this visitor to be applied to other fields. This will 1202 * cause the value stored in this->result to be modified. 1203 * 1204 * Make reg constant so that it doesn't get accidentally modified along the 1205 * way. Yes, I actually had this problem. :( 1206 */ 1207 const fs_reg reg(this, ir->type); 1208 fs_reg dst_reg = reg; 1209 1210 if (ir->type->is_array()) { 1211 const unsigned size = type_size(ir->type->fields.array); 1212 1213 for (unsigned i = 0; i < ir->type->length; i++) { 1214 this->result = reg_undef; 1215 ir->array_elements[i]->accept(this); 1216 fs_reg src_reg = this->result; 1217 1218 dst_reg.type = src_reg.type; 1219 for (unsigned j = 0; j < size; j++) { 1220 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1221 src_reg.reg_offset++; 1222 dst_reg.reg_offset++; 1223 } 1224 } 1225 } else if (ir->type->is_record()) { 1226 foreach_list(node, &ir->components) { 1227 ir_instruction *const field = (ir_instruction *) node; 1228 const unsigned size = type_size(field->type); 1229 1230 this->result = reg_undef; 1231 field->accept(this); 1232 fs_reg src_reg = this->result; 1233 1234 dst_reg.type = src_reg.type; 1235 for (unsigned j = 0; j < size; j++) { 1236 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1237 src_reg.reg_offset++; 1238 dst_reg.reg_offset++; 1239 } 1240 } 1241 } else { 1242 const unsigned size = type_size(ir->type); 1243 1244 for (unsigned i = 0; i < size; i++) { 1245 switch (ir->type->base_type) { 1246 case GLSL_TYPE_FLOAT: 1247 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i])); 1248 break; 1249 case GLSL_TYPE_UINT: 1250 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i])); 1251 break; 1252 case GLSL_TYPE_INT: 1253 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.i[i])); 1254 break; 1255 case GLSL_TYPE_BOOL: 1256 emit(BRW_OPCODE_MOV, dst_reg, fs_reg((int)ir->value.b[i])); 1257 break; 1258 default: 1259 assert(!"Non-float/uint/int/bool constant"); 1260 } 1261 dst_reg.reg_offset++; 1262 } 1263 } 1264 1265 this->result = reg; 1266} 1267 1268void 1269fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir) 1270{ 1271 ir_expression *expr = ir->as_expression(); 1272 1273 if (expr) { 1274 fs_reg op[2]; 1275 fs_inst *inst; 1276 1277 assert(expr->get_num_operands() <= 2); 1278 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1279 assert(expr->operands[i]->type->is_scalar()); 1280 1281 this->result = reg_undef; 1282 expr->operands[i]->accept(this); 1283 op[i] = this->result; 1284 } 1285 1286 switch (expr->operation) { 1287 case ir_unop_logic_not: 1288 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1)); 1289 inst->conditional_mod = BRW_CONDITIONAL_Z; 1290 break; 1291 1292 case ir_binop_logic_xor: 1293 inst = emit(BRW_OPCODE_XOR, reg_null_d, op[0], op[1]); 1294 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1295 break; 1296 1297 case ir_binop_logic_or: 1298 inst = emit(BRW_OPCODE_OR, reg_null_d, op[0], op[1]); 1299 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1300 break; 1301 1302 case ir_binop_logic_and: 1303 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], op[1]); 1304 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1305 break; 1306 1307 case ir_unop_f2b: 1308 if (intel->gen >= 6) { 1309 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0.0f)); 1310 } else { 1311 inst = emit(BRW_OPCODE_MOV, reg_null_f, op[0]); 1312 } 1313 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1314 break; 1315 1316 case ir_unop_i2b: 1317 if (intel->gen >= 6) { 1318 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0)); 1319 } else { 1320 inst = emit(BRW_OPCODE_MOV, reg_null_d, op[0]); 1321 } 1322 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1323 break; 1324 1325 case ir_binop_greater: 1326 case ir_binop_gequal: 1327 case ir_binop_less: 1328 case ir_binop_lequal: 1329 case ir_binop_equal: 1330 case ir_binop_all_equal: 1331 case ir_binop_nequal: 1332 case ir_binop_any_nequal: 1333 inst = emit(BRW_OPCODE_CMP, reg_null_cmp, op[0], op[1]); 1334 inst->conditional_mod = 1335 brw_conditional_for_comparison(expr->operation); 1336 break; 1337 1338 default: 1339 assert(!"not reached"); 1340 fail("bad cond code\n"); 1341 break; 1342 } 1343 return; 1344 } 1345 1346 this->result = reg_undef; 1347 ir->accept(this); 1348 1349 if (intel->gen >= 6) { 1350 fs_inst *inst = emit(BRW_OPCODE_AND, reg_null_d, this->result, fs_reg(1)); 1351 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1352 } else { 1353 fs_inst *inst = emit(BRW_OPCODE_MOV, reg_null_d, this->result); 1354 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1355 } 1356} 1357 1358/** 1359 * Emit a gen6 IF statement with the comparison folded into the IF 1360 * instruction. 1361 */ 1362void 1363fs_visitor::emit_if_gen6(ir_if *ir) 1364{ 1365 ir_expression *expr = ir->condition->as_expression(); 1366 1367 if (expr) { 1368 fs_reg op[2]; 1369 fs_inst *inst; 1370 fs_reg temp; 1371 1372 assert(expr->get_num_operands() <= 2); 1373 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1374 assert(expr->operands[i]->type->is_scalar()); 1375 1376 this->result = reg_undef; 1377 expr->operands[i]->accept(this); 1378 op[i] = this->result; 1379 } 1380 1381 switch (expr->operation) { 1382 case ir_unop_logic_not: 1383 inst = emit(BRW_OPCODE_IF, temp, op[0], fs_reg(0)); 1384 inst->conditional_mod = BRW_CONDITIONAL_Z; 1385 return; 1386 1387 case ir_binop_logic_xor: 1388 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1389 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1390 return; 1391 1392 case ir_binop_logic_or: 1393 temp = fs_reg(this, glsl_type::bool_type); 1394 emit(BRW_OPCODE_OR, temp, op[0], op[1]); 1395 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1396 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1397 return; 1398 1399 case ir_binop_logic_and: 1400 temp = fs_reg(this, glsl_type::bool_type); 1401 emit(BRW_OPCODE_AND, temp, op[0], op[1]); 1402 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1403 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1404 return; 1405 1406 case ir_unop_f2b: 1407 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0)); 1408 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1409 return; 1410 1411 case ir_unop_i2b: 1412 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1413 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1414 return; 1415 1416 case ir_binop_greater: 1417 case ir_binop_gequal: 1418 case ir_binop_less: 1419 case ir_binop_lequal: 1420 case ir_binop_equal: 1421 case ir_binop_all_equal: 1422 case ir_binop_nequal: 1423 case ir_binop_any_nequal: 1424 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1425 inst->conditional_mod = 1426 brw_conditional_for_comparison(expr->operation); 1427 return; 1428 default: 1429 assert(!"not reached"); 1430 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1431 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1432 fail("bad condition\n"); 1433 return; 1434 } 1435 return; 1436 } 1437 1438 this->result = reg_undef; 1439 ir->condition->accept(this); 1440 1441 fs_inst *inst = emit(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0)); 1442 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1443} 1444 1445void 1446fs_visitor::visit(ir_if *ir) 1447{ 1448 fs_inst *inst; 1449 1450 if (intel->gen != 6 && c->dispatch_width == 16) { 1451 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1452 } 1453 1454 /* Don't point the annotation at the if statement, because then it plus 1455 * the then and else blocks get printed. 1456 */ 1457 this->base_ir = ir->condition; 1458 1459 if (intel->gen == 6) { 1460 emit_if_gen6(ir); 1461 } else { 1462 emit_bool_to_cond_code(ir->condition); 1463 1464 inst = emit(BRW_OPCODE_IF); 1465 inst->predicated = true; 1466 } 1467 1468 foreach_iter(exec_list_iterator, iter, ir->then_instructions) { 1469 ir_instruction *ir = (ir_instruction *)iter.get(); 1470 this->base_ir = ir; 1471 this->result = reg_undef; 1472 ir->accept(this); 1473 } 1474 1475 if (!ir->else_instructions.is_empty()) { 1476 emit(BRW_OPCODE_ELSE); 1477 1478 foreach_iter(exec_list_iterator, iter, ir->else_instructions) { 1479 ir_instruction *ir = (ir_instruction *)iter.get(); 1480 this->base_ir = ir; 1481 this->result = reg_undef; 1482 ir->accept(this); 1483 } 1484 } 1485 1486 emit(BRW_OPCODE_ENDIF); 1487} 1488 1489void 1490fs_visitor::visit(ir_loop *ir) 1491{ 1492 fs_reg counter = reg_undef; 1493 1494 if (c->dispatch_width == 16) { 1495 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1496 } 1497 1498 if (ir->counter) { 1499 this->base_ir = ir->counter; 1500 ir->counter->accept(this); 1501 counter = *(variable_storage(ir->counter)); 1502 1503 if (ir->from) { 1504 this->result = counter; 1505 1506 this->base_ir = ir->from; 1507 this->result = counter; 1508 ir->from->accept(this); 1509 1510 if (!this->result.equals(&counter)) 1511 emit(BRW_OPCODE_MOV, counter, this->result); 1512 } 1513 } 1514 1515 emit(BRW_OPCODE_DO); 1516 1517 if (ir->to) { 1518 this->base_ir = ir->to; 1519 this->result = reg_undef; 1520 ir->to->accept(this); 1521 1522 fs_inst *inst = emit(BRW_OPCODE_CMP, reg_null_cmp, counter, this->result); 1523 inst->conditional_mod = brw_conditional_for_comparison(ir->cmp); 1524 1525 inst = emit(BRW_OPCODE_BREAK); 1526 inst->predicated = true; 1527 } 1528 1529 foreach_iter(exec_list_iterator, iter, ir->body_instructions) { 1530 ir_instruction *ir = (ir_instruction *)iter.get(); 1531 1532 this->base_ir = ir; 1533 this->result = reg_undef; 1534 ir->accept(this); 1535 } 1536 1537 if (ir->increment) { 1538 this->base_ir = ir->increment; 1539 this->result = reg_undef; 1540 ir->increment->accept(this); 1541 emit(BRW_OPCODE_ADD, counter, counter, this->result); 1542 } 1543 1544 emit(BRW_OPCODE_WHILE); 1545} 1546 1547void 1548fs_visitor::visit(ir_loop_jump *ir) 1549{ 1550 switch (ir->mode) { 1551 case ir_loop_jump::jump_break: 1552 emit(BRW_OPCODE_BREAK); 1553 break; 1554 case ir_loop_jump::jump_continue: 1555 emit(BRW_OPCODE_CONTINUE); 1556 break; 1557 } 1558} 1559 1560void 1561fs_visitor::visit(ir_call *ir) 1562{ 1563 assert(!"FINISHME"); 1564} 1565 1566void 1567fs_visitor::visit(ir_return *ir) 1568{ 1569 assert(!"FINISHME"); 1570} 1571 1572void 1573fs_visitor::visit(ir_function *ir) 1574{ 1575 /* Ignore function bodies other than main() -- we shouldn't see calls to 1576 * them since they should all be inlined before we get to ir_to_mesa. 1577 */ 1578 if (strcmp(ir->name, "main") == 0) { 1579 const ir_function_signature *sig; 1580 exec_list empty; 1581 1582 sig = ir->matching_signature(&empty); 1583 1584 assert(sig); 1585 1586 foreach_iter(exec_list_iterator, iter, sig->body) { 1587 ir_instruction *ir = (ir_instruction *)iter.get(); 1588 this->base_ir = ir; 1589 this->result = reg_undef; 1590 ir->accept(this); 1591 } 1592 } 1593} 1594 1595void 1596fs_visitor::visit(ir_function_signature *ir) 1597{ 1598 assert(!"not reached"); 1599 (void)ir; 1600} 1601 1602fs_inst * 1603fs_visitor::emit(fs_inst inst) 1604{ 1605 fs_inst *list_inst = new(mem_ctx) fs_inst; 1606 *list_inst = inst; 1607 1608 if (force_uncompressed_stack > 0) 1609 list_inst->force_uncompressed = true; 1610 else if (force_sechalf_stack > 0) 1611 list_inst->force_sechalf = true; 1612 1613 list_inst->annotation = this->current_annotation; 1614 list_inst->ir = this->base_ir; 1615 1616 this->instructions.push_tail(list_inst); 1617 1618 return list_inst; 1619} 1620 1621/** Emits a dummy fragment shader consisting of magenta for bringup purposes. */ 1622void 1623fs_visitor::emit_dummy_fs() 1624{ 1625 /* Everyone's favorite color. */ 1626 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2), fs_reg(1.0f)); 1627 emit(BRW_OPCODE_MOV, fs_reg(MRF, 3), fs_reg(0.0f)); 1628 emit(BRW_OPCODE_MOV, fs_reg(MRF, 4), fs_reg(1.0f)); 1629 emit(BRW_OPCODE_MOV, fs_reg(MRF, 5), fs_reg(0.0f)); 1630 1631 fs_inst *write; 1632 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0)); 1633 write->base_mrf = 2; 1634} 1635 1636/* The register location here is relative to the start of the URB 1637 * data. It will get adjusted to be a real location before 1638 * generate_code() time. 1639 */ 1640struct brw_reg 1641fs_visitor::interp_reg(int location, int channel) 1642{ 1643 int regnr = urb_setup[location] * 2 + channel / 2; 1644 int stride = (channel & 1) * 4; 1645 1646 assert(urb_setup[location] != -1); 1647 1648 return brw_vec1_grf(regnr, stride); 1649} 1650 1651/** Emits the interpolation for the varying inputs. */ 1652void 1653fs_visitor::emit_interpolation_setup_gen4() 1654{ 1655 this->current_annotation = "compute pixel centers"; 1656 this->pixel_x = fs_reg(this, glsl_type::uint_type); 1657 this->pixel_y = fs_reg(this, glsl_type::uint_type); 1658 this->pixel_x.type = BRW_REGISTER_TYPE_UW; 1659 this->pixel_y.type = BRW_REGISTER_TYPE_UW; 1660 1661 emit(FS_OPCODE_PIXEL_X, this->pixel_x); 1662 emit(FS_OPCODE_PIXEL_Y, this->pixel_y); 1663 1664 this->current_annotation = "compute pixel deltas from v0"; 1665 if (brw->has_pln) { 1666 this->delta_x = fs_reg(this, glsl_type::vec2_type); 1667 this->delta_y = this->delta_x; 1668 this->delta_y.reg_offset++; 1669 } else { 1670 this->delta_x = fs_reg(this, glsl_type::float_type); 1671 this->delta_y = fs_reg(this, glsl_type::float_type); 1672 } 1673 emit(BRW_OPCODE_ADD, this->delta_x, 1674 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))); 1675 emit(BRW_OPCODE_ADD, this->delta_y, 1676 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))); 1677 1678 this->current_annotation = "compute pos.w and 1/pos.w"; 1679 /* Compute wpos.w. It's always in our setup, since it's needed to 1680 * interpolate the other attributes. 1681 */ 1682 this->wpos_w = fs_reg(this, glsl_type::float_type); 1683 emit(FS_OPCODE_LINTERP, wpos_w, this->delta_x, this->delta_y, 1684 interp_reg(FRAG_ATTRIB_WPOS, 3)); 1685 /* Compute the pixel 1/W value from wpos.w. */ 1686 this->pixel_w = fs_reg(this, glsl_type::float_type); 1687 emit_math(FS_OPCODE_RCP, this->pixel_w, wpos_w); 1688 this->current_annotation = NULL; 1689} 1690 1691/** Emits the interpolation for the varying inputs. */ 1692void 1693fs_visitor::emit_interpolation_setup_gen6() 1694{ 1695 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); 1696 1697 /* If the pixel centers end up used, the setup is the same as for gen4. */ 1698 this->current_annotation = "compute pixel centers"; 1699 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type); 1700 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type); 1701 int_pixel_x.type = BRW_REGISTER_TYPE_UW; 1702 int_pixel_y.type = BRW_REGISTER_TYPE_UW; 1703 emit(BRW_OPCODE_ADD, 1704 int_pixel_x, 1705 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), 1706 fs_reg(brw_imm_v(0x10101010))); 1707 emit(BRW_OPCODE_ADD, 1708 int_pixel_y, 1709 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), 1710 fs_reg(brw_imm_v(0x11001100))); 1711 1712 /* As of gen6, we can no longer mix float and int sources. We have 1713 * to turn the integer pixel centers into floats for their actual 1714 * use. 1715 */ 1716 this->pixel_x = fs_reg(this, glsl_type::float_type); 1717 this->pixel_y = fs_reg(this, glsl_type::float_type); 1718 emit(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x); 1719 emit(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y); 1720 1721 this->current_annotation = "compute pos.w"; 1722 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0)); 1723 this->wpos_w = fs_reg(this, glsl_type::float_type); 1724 emit_math(FS_OPCODE_RCP, this->wpos_w, this->pixel_w); 1725 1726 this->delta_x = fs_reg(brw_vec8_grf(2, 0)); 1727 this->delta_y = fs_reg(brw_vec8_grf(3, 0)); 1728 1729 this->current_annotation = NULL; 1730} 1731 1732void 1733fs_visitor::emit_color_write(int index, int first_color_mrf, fs_reg color) 1734{ 1735 int reg_width = c->dispatch_width / 8; 1736 1737 if (c->dispatch_width == 8 || intel->gen == 6) { 1738 /* SIMD8 write looks like: 1739 * m + 0: r0 1740 * m + 1: r1 1741 * m + 2: g0 1742 * m + 3: g1 1743 * 1744 * gen6 SIMD16 DP write looks like: 1745 * m + 0: r0 1746 * m + 1: r1 1747 * m + 2: g0 1748 * m + 3: g1 1749 * m + 4: b0 1750 * m + 5: b1 1751 * m + 6: a0 1752 * m + 7: a1 1753 */ 1754 emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index * reg_width), 1755 color); 1756 } else { 1757 /* pre-gen6 SIMD16 single source DP write looks like: 1758 * m + 0: r0 1759 * m + 1: g0 1760 * m + 2: b0 1761 * m + 3: a0 1762 * m + 4: r1 1763 * m + 5: g1 1764 * m + 6: b1 1765 * m + 7: a1 1766 */ 1767 if (brw->has_compr4) { 1768 /* By setting the high bit of the MRF register number, we 1769 * indicate that we want COMPR4 mode - instead of doing the 1770 * usual destination + 1 for the second half we get 1771 * destination + 4. 1772 */ 1773 emit(BRW_OPCODE_MOV, 1774 fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index), color); 1775 } else { 1776 push_force_uncompressed(); 1777 emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index), color); 1778 pop_force_uncompressed(); 1779 1780 push_force_sechalf(); 1781 color.sechalf = true; 1782 emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index + 4), color); 1783 pop_force_sechalf(); 1784 color.sechalf = false; 1785 } 1786 } 1787} 1788 1789void 1790fs_visitor::emit_fb_writes() 1791{ 1792 this->current_annotation = "FB write header"; 1793 GLboolean header_present = GL_TRUE; 1794 int nr = 2; 1795 int reg_width = c->dispatch_width / 8; 1796 1797 if (intel->gen >= 6 && 1798 !this->kill_emitted && 1799 c->key.nr_color_regions == 1) { 1800 header_present = false; 1801 } 1802 1803 if (header_present) { 1804 /* m2, m3 header */ 1805 nr += 2; 1806 } 1807 1808 if (c->aa_dest_stencil_reg) { 1809 push_force_uncompressed(); 1810 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++), 1811 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))); 1812 pop_force_uncompressed(); 1813 } 1814 1815 /* Reserve space for color. It'll be filled in per MRT below. */ 1816 int color_mrf = nr; 1817 nr += 4 * reg_width; 1818 1819 if (c->source_depth_to_render_target) { 1820 if (intel->gen == 6 && c->dispatch_width == 16) { 1821 /* For outputting oDepth on gen6, SIMD8 writes have to be 1822 * used. This would require 8-wide moves of each half to 1823 * message regs, kind of like pre-gen5 SIMD16 FB writes. 1824 * Just bail on doing so for now. 1825 */ 1826 fail("Missing support for simd16 depth writes on gen6\n"); 1827 } 1828 1829 if (c->computes_depth) { 1830 /* Hand over gl_FragDepth. */ 1831 assert(this->frag_depth); 1832 fs_reg depth = *(variable_storage(this->frag_depth)); 1833 1834 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), depth); 1835 } else { 1836 /* Pass through the payload depth. */ 1837 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1838 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))); 1839 } 1840 nr += reg_width; 1841 } 1842 1843 if (c->dest_depth_reg) { 1844 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1845 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))); 1846 nr += reg_width; 1847 } 1848 1849 fs_reg color = reg_undef; 1850 if (this->frag_color) 1851 color = *(variable_storage(this->frag_color)); 1852 else if (this->frag_data) { 1853 color = *(variable_storage(this->frag_data)); 1854 color.type = BRW_REGISTER_TYPE_F; 1855 } 1856 1857 for (int target = 0; target < c->key.nr_color_regions; target++) { 1858 this->current_annotation = ralloc_asprintf(this->mem_ctx, 1859 "FB write target %d", 1860 target); 1861 if (this->frag_color || this->frag_data) { 1862 for (int i = 0; i < 4; i++) { 1863 emit_color_write(i, color_mrf, color); 1864 color.reg_offset++; 1865 } 1866 } 1867 1868 if (this->frag_color) 1869 color.reg_offset -= 4; 1870 1871 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1872 inst->target = target; 1873 inst->base_mrf = 2; 1874 inst->mlen = nr; 1875 if (target == c->key.nr_color_regions - 1) 1876 inst->eot = true; 1877 inst->header_present = header_present; 1878 } 1879 1880 if (c->key.nr_color_regions == 0) { 1881 if (c->key.alpha_test && (this->frag_color || this->frag_data)) { 1882 /* If the alpha test is enabled but there's no color buffer, 1883 * we still need to send alpha out the pipeline to our null 1884 * renderbuffer. 1885 */ 1886 color.reg_offset += 3; 1887 emit_color_write(3, color_mrf, color); 1888 } 1889 1890 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1891 inst->base_mrf = 2; 1892 inst->mlen = nr; 1893 inst->eot = true; 1894 inst->header_present = header_present; 1895 } 1896 1897 this->current_annotation = NULL; 1898} 1899