brw_fs_visitor.cpp revision b6bdcf2a908889532ef6d5eb643791176dffcb9d
1/* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24/** @file brw_fs_visitor.cpp 25 * 26 * This file supports generating the FS LIR from the GLSL IR. The LIR 27 * makes it easier to do backend-specific optimizations than doing so 28 * in the GLSL IR or in the native code. 29 */ 30extern "C" { 31 32#include <sys/types.h> 33 34#include "main/macros.h" 35#include "main/shaderobj.h" 36#include "main/uniforms.h" 37#include "program/prog_parameter.h" 38#include "program/prog_print.h" 39#include "program/prog_optimize.h" 40#include "program/register_allocate.h" 41#include "program/sampler.h" 42#include "program/hash_table.h" 43#include "brw_context.h" 44#include "brw_eu.h" 45#include "brw_wm.h" 46} 47#include "brw_shader.h" 48#include "brw_fs.h" 49#include "../glsl/glsl_types.h" 50#include "../glsl/ir_optimization.h" 51#include "../glsl/ir_print_visitor.h" 52 53void 54fs_visitor::visit(ir_variable *ir) 55{ 56 fs_reg *reg = NULL; 57 58 if (variable_storage(ir)) 59 return; 60 61 if (strcmp(ir->name, "gl_FragColor") == 0) { 62 this->frag_color = ir; 63 } else if (strcmp(ir->name, "gl_FragData") == 0) { 64 this->frag_data = ir; 65 } else if (strcmp(ir->name, "gl_FragDepth") == 0) { 66 this->frag_depth = ir; 67 } 68 69 if (ir->mode == ir_var_in) { 70 if (!strcmp(ir->name, "gl_FragCoord")) { 71 reg = emit_fragcoord_interpolation(ir); 72 } else if (!strcmp(ir->name, "gl_FrontFacing")) { 73 reg = emit_frontfacing_interpolation(ir); 74 } else { 75 reg = emit_general_interpolation(ir); 76 } 77 assert(reg); 78 hash_table_insert(this->variable_ht, reg, ir); 79 return; 80 } 81 82 if (ir->mode == ir_var_uniform) { 83 int param_index = c->prog_data.nr_params; 84 85 if (c->dispatch_width == 16) { 86 if (!variable_storage(ir)) { 87 fail("Failed to find uniform '%s' in 16-wide\n", ir->name); 88 } 89 return; 90 } 91 92 if (!strncmp(ir->name, "gl_", 3)) { 93 setup_builtin_uniform_values(ir); 94 } else { 95 setup_uniform_values(ir->location, ir->type); 96 } 97 98 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index); 99 reg->type = brw_type_for_base_type(ir->type); 100 } 101 102 if (!reg) 103 reg = new(this->mem_ctx) fs_reg(this, ir->type); 104 105 hash_table_insert(this->variable_ht, reg, ir); 106} 107 108void 109fs_visitor::visit(ir_dereference_variable *ir) 110{ 111 fs_reg *reg = variable_storage(ir->var); 112 this->result = *reg; 113} 114 115void 116fs_visitor::visit(ir_dereference_record *ir) 117{ 118 const glsl_type *struct_type = ir->record->type; 119 120 ir->record->accept(this); 121 122 unsigned int offset = 0; 123 for (unsigned int i = 0; i < struct_type->length; i++) { 124 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0) 125 break; 126 offset += type_size(struct_type->fields.structure[i].type); 127 } 128 this->result.reg_offset += offset; 129 this->result.type = brw_type_for_base_type(ir->type); 130} 131 132void 133fs_visitor::visit(ir_dereference_array *ir) 134{ 135 ir_constant *index; 136 int element_size; 137 138 ir->array->accept(this); 139 index = ir->array_index->as_constant(); 140 141 element_size = type_size(ir->type); 142 this->result.type = brw_type_for_base_type(ir->type); 143 144 if (index) { 145 assert(this->result.file == UNIFORM || this->result.file == GRF); 146 this->result.reg_offset += index->value.i[0] * element_size; 147 } else { 148 assert(!"FINISHME: non-constant array element"); 149 } 150} 151 152/* Instruction selection: Produce a MOV.sat instead of 153 * MIN(MAX(val, 0), 1) when possible. 154 */ 155bool 156fs_visitor::try_emit_saturate(ir_expression *ir) 157{ 158 ir_rvalue *sat_val = ir->as_rvalue_to_saturate(); 159 160 if (!sat_val) 161 return false; 162 163 this->result = reg_undef; 164 sat_val->accept(this); 165 fs_reg src = this->result; 166 167 this->result = fs_reg(this, ir->type); 168 fs_inst *inst = emit(BRW_OPCODE_MOV, this->result, src); 169 inst->saturate = true; 170 171 return true; 172} 173 174void 175fs_visitor::visit(ir_expression *ir) 176{ 177 unsigned int operand; 178 fs_reg op[2], temp; 179 fs_inst *inst; 180 181 assert(ir->get_num_operands() <= 2); 182 183 if (try_emit_saturate(ir)) 184 return; 185 186 /* This is where our caller would like us to put the result, if possible. */ 187 fs_reg saved_result_storage = this->result; 188 189 for (operand = 0; operand < ir->get_num_operands(); operand++) { 190 this->result = reg_undef; 191 ir->operands[operand]->accept(this); 192 if (this->result.file == BAD_FILE) { 193 ir_print_visitor v; 194 fail("Failed to get tree for expression operand:\n"); 195 ir->operands[operand]->accept(&v); 196 } 197 op[operand] = this->result; 198 199 /* Matrix expression operands should have been broken down to vector 200 * operations already. 201 */ 202 assert(!ir->operands[operand]->type->is_matrix()); 203 /* And then those vector operands should have been broken down to scalar. 204 */ 205 assert(!ir->operands[operand]->type->is_vector()); 206 } 207 208 /* Inherit storage from our parent if possible, and otherwise we 209 * alloc a temporary. 210 */ 211 if (saved_result_storage.file == BAD_FILE) { 212 this->result = fs_reg(this, ir->type); 213 } else { 214 this->result = saved_result_storage; 215 } 216 217 switch (ir->operation) { 218 case ir_unop_logic_not: 219 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is 220 * ones complement of the whole register, not just bit 0. 221 */ 222 emit(BRW_OPCODE_XOR, this->result, op[0], fs_reg(1)); 223 break; 224 case ir_unop_neg: 225 op[0].negate = !op[0].negate; 226 this->result = op[0]; 227 break; 228 case ir_unop_abs: 229 op[0].abs = true; 230 op[0].negate = false; 231 this->result = op[0]; 232 break; 233 case ir_unop_sign: 234 temp = fs_reg(this, ir->type); 235 236 /* Unalias the destination. (imagine a = sign(a)) */ 237 this->result = fs_reg(this, ir->type); 238 239 emit(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)); 240 241 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 242 inst->conditional_mod = BRW_CONDITIONAL_G; 243 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)); 244 inst->predicated = true; 245 246 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 247 inst->conditional_mod = BRW_CONDITIONAL_L; 248 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)); 249 inst->predicated = true; 250 251 break; 252 case ir_unop_rcp: 253 emit_math(SHADER_OPCODE_RCP, this->result, op[0]); 254 break; 255 256 case ir_unop_exp2: 257 emit_math(SHADER_OPCODE_EXP2, this->result, op[0]); 258 break; 259 case ir_unop_log2: 260 emit_math(SHADER_OPCODE_LOG2, this->result, op[0]); 261 break; 262 case ir_unop_exp: 263 case ir_unop_log: 264 assert(!"not reached: should be handled by ir_explog_to_explog2"); 265 break; 266 case ir_unop_sin: 267 case ir_unop_sin_reduced: 268 emit_math(SHADER_OPCODE_SIN, this->result, op[0]); 269 break; 270 case ir_unop_cos: 271 case ir_unop_cos_reduced: 272 emit_math(SHADER_OPCODE_COS, this->result, op[0]); 273 break; 274 275 case ir_unop_dFdx: 276 emit(FS_OPCODE_DDX, this->result, op[0]); 277 break; 278 case ir_unop_dFdy: 279 emit(FS_OPCODE_DDY, this->result, op[0]); 280 break; 281 282 case ir_binop_add: 283 emit(BRW_OPCODE_ADD, this->result, op[0], op[1]); 284 break; 285 case ir_binop_sub: 286 assert(!"not reached: should be handled by ir_sub_to_add_neg"); 287 break; 288 289 case ir_binop_mul: 290 if (ir->type->is_integer()) { 291 /* For integer multiplication, the MUL uses the low 16 bits 292 * of one of the operands (src0 on gen6, src1 on gen7). The 293 * MACH accumulates in the contribution of the upper 16 bits 294 * of that operand. 295 * 296 * FINISHME: Emit just the MUL if we know an operand is small 297 * enough. 298 */ 299 struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_D); 300 301 emit(BRW_OPCODE_MUL, acc, op[0], op[1]); 302 emit(BRW_OPCODE_MACH, reg_null_d, op[0], op[1]); 303 emit(BRW_OPCODE_MOV, this->result, fs_reg(acc)); 304 } else { 305 emit(BRW_OPCODE_MUL, this->result, op[0], op[1]); 306 } 307 break; 308 case ir_binop_div: 309 assert(!"not reached: should be handled by ir_div_to_mul_rcp"); 310 break; 311 case ir_binop_mod: 312 assert(!"ir_binop_mod should have been converted to b * fract(a/b)"); 313 break; 314 315 case ir_binop_less: 316 case ir_binop_greater: 317 case ir_binop_lequal: 318 case ir_binop_gequal: 319 case ir_binop_equal: 320 case ir_binop_all_equal: 321 case ir_binop_nequal: 322 case ir_binop_any_nequal: 323 temp = this->result; 324 /* original gen4 does implicit conversion before comparison. */ 325 if (intel->gen < 5) 326 temp.type = op[0].type; 327 328 inst = emit(BRW_OPCODE_CMP, temp, op[0], op[1]); 329 inst->conditional_mod = brw_conditional_for_comparison(ir->operation); 330 emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)); 331 break; 332 333 case ir_binop_logic_xor: 334 emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 335 break; 336 337 case ir_binop_logic_or: 338 emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 339 break; 340 341 case ir_binop_logic_and: 342 emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 343 break; 344 345 case ir_binop_dot: 346 case ir_unop_any: 347 assert(!"not reached: should be handled by brw_fs_channel_expressions"); 348 break; 349 350 case ir_unop_noise: 351 assert(!"not reached: should be handled by lower_noise"); 352 break; 353 354 case ir_quadop_vector: 355 assert(!"not reached: should be handled by lower_quadop_vector"); 356 break; 357 358 case ir_unop_sqrt: 359 emit_math(SHADER_OPCODE_SQRT, this->result, op[0]); 360 break; 361 362 case ir_unop_rsq: 363 emit_math(SHADER_OPCODE_RSQ, this->result, op[0]); 364 break; 365 366 case ir_unop_i2u: 367 op[0].type = BRW_REGISTER_TYPE_UD; 368 this->result = op[0]; 369 break; 370 case ir_unop_u2i: 371 op[0].type = BRW_REGISTER_TYPE_D; 372 this->result = op[0]; 373 break; 374 case ir_unop_i2f: 375 case ir_unop_b2f: 376 case ir_unop_b2i: 377 case ir_unop_f2i: 378 emit(BRW_OPCODE_MOV, this->result, op[0]); 379 break; 380 case ir_unop_f2b: 381 case ir_unop_i2b: 382 temp = this->result; 383 /* original gen4 does implicit conversion before comparison. */ 384 if (intel->gen < 5) 385 temp.type = op[0].type; 386 387 inst = emit(BRW_OPCODE_CMP, temp, op[0], fs_reg(0.0f)); 388 inst->conditional_mod = BRW_CONDITIONAL_NZ; 389 inst = emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(1)); 390 break; 391 392 case ir_unop_trunc: 393 emit(BRW_OPCODE_RNDZ, this->result, op[0]); 394 break; 395 case ir_unop_ceil: 396 op[0].negate = !op[0].negate; 397 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 398 this->result.negate = true; 399 break; 400 case ir_unop_floor: 401 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 402 break; 403 case ir_unop_fract: 404 inst = emit(BRW_OPCODE_FRC, this->result, op[0]); 405 break; 406 case ir_unop_round_even: 407 emit(BRW_OPCODE_RNDE, this->result, op[0]); 408 break; 409 410 case ir_binop_min: 411 if (intel->gen >= 6) { 412 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 413 inst->conditional_mod = BRW_CONDITIONAL_L; 414 } else { 415 /* Unalias the destination */ 416 this->result = fs_reg(this, ir->type); 417 418 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 419 inst->conditional_mod = BRW_CONDITIONAL_L; 420 421 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 422 inst->predicated = true; 423 } 424 break; 425 case ir_binop_max: 426 if (intel->gen >= 6) { 427 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 428 inst->conditional_mod = BRW_CONDITIONAL_GE; 429 } else { 430 /* Unalias the destination */ 431 this->result = fs_reg(this, ir->type); 432 433 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 434 inst->conditional_mod = BRW_CONDITIONAL_G; 435 436 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 437 inst->predicated = true; 438 } 439 break; 440 441 case ir_binop_pow: 442 emit_math(SHADER_OPCODE_POW, this->result, op[0], op[1]); 443 break; 444 445 case ir_unop_bit_not: 446 inst = emit(BRW_OPCODE_NOT, this->result, op[0]); 447 break; 448 case ir_binop_bit_and: 449 inst = emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 450 break; 451 case ir_binop_bit_xor: 452 inst = emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 453 break; 454 case ir_binop_bit_or: 455 inst = emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 456 break; 457 458 case ir_unop_u2f: 459 case ir_binop_lshift: 460 case ir_binop_rshift: 461 assert(!"GLSL 1.30 features unsupported"); 462 break; 463 } 464} 465 466void 467fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r, 468 const glsl_type *type, bool predicated) 469{ 470 switch (type->base_type) { 471 case GLSL_TYPE_FLOAT: 472 case GLSL_TYPE_UINT: 473 case GLSL_TYPE_INT: 474 case GLSL_TYPE_BOOL: 475 for (unsigned int i = 0; i < type->components(); i++) { 476 l.type = brw_type_for_base_type(type); 477 r.type = brw_type_for_base_type(type); 478 479 if (predicated || !l.equals(&r)) { 480 fs_inst *inst = emit(BRW_OPCODE_MOV, l, r); 481 inst->predicated = predicated; 482 } 483 484 l.reg_offset++; 485 r.reg_offset++; 486 } 487 break; 488 case GLSL_TYPE_ARRAY: 489 for (unsigned int i = 0; i < type->length; i++) { 490 emit_assignment_writes(l, r, type->fields.array, predicated); 491 } 492 break; 493 494 case GLSL_TYPE_STRUCT: 495 for (unsigned int i = 0; i < type->length; i++) { 496 emit_assignment_writes(l, r, type->fields.structure[i].type, 497 predicated); 498 } 499 break; 500 501 case GLSL_TYPE_SAMPLER: 502 break; 503 504 default: 505 assert(!"not reached"); 506 break; 507 } 508} 509 510void 511fs_visitor::visit(ir_assignment *ir) 512{ 513 fs_reg l, r; 514 fs_inst *inst; 515 516 /* FINISHME: arrays on the lhs */ 517 this->result = reg_undef; 518 ir->lhs->accept(this); 519 l = this->result; 520 521 /* If we're doing a direct assignment, an RHS expression could 522 * drop its result right into our destination. Otherwise, tell it 523 * not to. 524 */ 525 if (ir->condition || 526 !(ir->lhs->type->is_scalar() || 527 (ir->lhs->type->is_vector() && 528 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1))) { 529 this->result = reg_undef; 530 } 531 532 ir->rhs->accept(this); 533 r = this->result; 534 535 assert(l.file != BAD_FILE); 536 assert(r.file != BAD_FILE); 537 538 if (ir->condition) { 539 emit_bool_to_cond_code(ir->condition); 540 } 541 542 if (ir->lhs->type->is_scalar() || 543 ir->lhs->type->is_vector()) { 544 for (int i = 0; i < ir->lhs->type->vector_elements; i++) { 545 if (ir->write_mask & (1 << i)) { 546 if (ir->condition) { 547 inst = emit(BRW_OPCODE_MOV, l, r); 548 inst->predicated = true; 549 } else if (!l.equals(&r)) { 550 inst = emit(BRW_OPCODE_MOV, l, r); 551 } 552 553 r.reg_offset++; 554 } 555 l.reg_offset++; 556 } 557 } else { 558 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL); 559 } 560} 561 562fs_inst * 563fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate, 564 int sampler) 565{ 566 int mlen; 567 int base_mrf = 1; 568 bool simd16 = false; 569 fs_reg orig_dst; 570 571 /* g0 header. */ 572 mlen = 1; 573 574 if (ir->shadow_comparitor && ir->op != ir_txd) { 575 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 576 fs_inst *inst = emit(BRW_OPCODE_MOV, 577 fs_reg(MRF, base_mrf + mlen + i), coordinate); 578 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 579 inst->saturate = true; 580 581 coordinate.reg_offset++; 582 } 583 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 584 mlen += 3; 585 586 if (ir->op == ir_tex) { 587 /* There's no plain shadow compare message, so we use shadow 588 * compare with a bias of 0.0. 589 */ 590 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)); 591 mlen++; 592 } else if (ir->op == ir_txb) { 593 this->result = reg_undef; 594 ir->lod_info.bias->accept(this); 595 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 596 mlen++; 597 } else { 598 assert(ir->op == ir_txl); 599 this->result = reg_undef; 600 ir->lod_info.lod->accept(this); 601 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 602 mlen++; 603 } 604 605 this->result = reg_undef; 606 ir->shadow_comparitor->accept(this); 607 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 608 mlen++; 609 } else if (ir->op == ir_tex) { 610 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 611 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), 612 coordinate); 613 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 614 inst->saturate = true; 615 coordinate.reg_offset++; 616 } 617 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 618 mlen += 3; 619 } else if (ir->op == ir_txd) { 620 this->result = reg_undef; 621 ir->lod_info.grad.dPdx->accept(this); 622 fs_reg dPdx = this->result; 623 624 this->result = reg_undef; 625 ir->lod_info.grad.dPdy->accept(this); 626 fs_reg dPdy = this->result; 627 628 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 629 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); 630 coordinate.reg_offset++; 631 } 632 /* the slots for u and v are always present, but r is optional */ 633 mlen += MAX2(ir->coordinate->type->vector_elements, 2); 634 635 /* P = u, v, r 636 * dPdx = dudx, dvdx, drdx 637 * dPdy = dudy, dvdy, drdy 638 * 639 * 1-arg: Does not exist. 640 * 641 * 2-arg: dudx dvdx dudy dvdy 642 * dPdx.x dPdx.y dPdy.x dPdy.y 643 * m4 m5 m6 m7 644 * 645 * 3-arg: dudx dvdx drdx dudy dvdy drdy 646 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z 647 * m5 m6 m7 m8 m9 m10 648 */ 649 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 650 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 651 dPdx.reg_offset++; 652 } 653 mlen += MAX2(ir->lod_info.grad.dPdx->type->vector_elements, 2); 654 655 for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) { 656 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 657 dPdy.reg_offset++; 658 } 659 mlen += MAX2(ir->lod_info.grad.dPdy->type->vector_elements, 2); 660 } else { 661 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod 662 * instructions. We'll need to do SIMD16 here. 663 */ 664 assert(ir->op == ir_txb || ir->op == ir_txl); 665 666 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 667 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, 668 base_mrf + mlen + i * 2), 669 coordinate); 670 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 671 inst->saturate = true; 672 coordinate.reg_offset++; 673 } 674 675 /* lod/bias appears after u/v/r. */ 676 mlen += 6; 677 678 if (ir->op == ir_txb) { 679 this->result = reg_undef; 680 ir->lod_info.bias->accept(this); 681 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 682 mlen++; 683 } else { 684 this->result = reg_undef; 685 ir->lod_info.lod->accept(this); 686 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 687 mlen++; 688 } 689 690 /* The unused upper half. */ 691 mlen++; 692 693 /* Now, since we're doing simd16, the return is 2 interleaved 694 * vec4s where the odd-indexed ones are junk. We'll need to move 695 * this weirdness around to the expected layout. 696 */ 697 simd16 = true; 698 orig_dst = dst; 699 dst = fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type, 700 2)); 701 dst.type = BRW_REGISTER_TYPE_F; 702 } 703 704 fs_inst *inst = NULL; 705 switch (ir->op) { 706 case ir_tex: 707 inst = emit(FS_OPCODE_TEX, dst); 708 break; 709 case ir_txb: 710 inst = emit(FS_OPCODE_TXB, dst); 711 break; 712 case ir_txl: 713 inst = emit(FS_OPCODE_TXL, dst); 714 break; 715 case ir_txd: 716 inst = emit(FS_OPCODE_TXD, dst); 717 break; 718 case ir_txf: 719 case ir_txs: 720 assert(!"GLSL 1.30 features unsupported"); 721 break; 722 } 723 inst->base_mrf = base_mrf; 724 inst->mlen = mlen; 725 inst->header_present = true; 726 727 if (simd16) { 728 for (int i = 0; i < 4; i++) { 729 emit(BRW_OPCODE_MOV, orig_dst, dst); 730 orig_dst.reg_offset++; 731 dst.reg_offset += 2; 732 } 733 } 734 735 return inst; 736} 737 738/* gen5's sampler has slots for u, v, r, array index, then optional 739 * parameters like shadow comparitor or LOD bias. If optional 740 * parameters aren't present, those base slots are optional and don't 741 * need to be included in the message. 742 * 743 * We don't fill in the unnecessary slots regardless, which may look 744 * surprising in the disassembly. 745 */ 746fs_inst * 747fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate, 748 int sampler) 749{ 750 int mlen = 0; 751 int base_mrf = 2; 752 int reg_width = c->dispatch_width / 8; 753 bool header_present = false; 754 755 if (ir->offset) { 756 /* The offsets set up by the ir_texture visitor are in the 757 * m1 header, so we can't go headerless. 758 */ 759 header_present = true; 760 mlen++; 761 base_mrf--; 762 } 763 764 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 765 fs_inst *inst = emit(BRW_OPCODE_MOV, 766 fs_reg(MRF, base_mrf + mlen + i * reg_width), 767 coordinate); 768 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 769 inst->saturate = true; 770 coordinate.reg_offset++; 771 } 772 mlen += ir->coordinate->type->vector_elements * reg_width; 773 774 if (ir->shadow_comparitor && ir->op != ir_txd) { 775 mlen = MAX2(mlen, header_present + 4 * reg_width); 776 777 this->result = reg_undef; 778 ir->shadow_comparitor->accept(this); 779 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 780 mlen += reg_width; 781 } 782 783 fs_inst *inst = NULL; 784 switch (ir->op) { 785 case ir_tex: 786 inst = emit(FS_OPCODE_TEX, dst); 787 break; 788 case ir_txb: 789 this->result = reg_undef; 790 ir->lod_info.bias->accept(this); 791 mlen = MAX2(mlen, header_present + 4 * reg_width); 792 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 793 mlen += reg_width; 794 795 inst = emit(FS_OPCODE_TXB, dst); 796 797 break; 798 case ir_txl: 799 this->result = reg_undef; 800 ir->lod_info.lod->accept(this); 801 mlen = MAX2(mlen, header_present + 4 * reg_width); 802 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 803 mlen += reg_width; 804 805 inst = emit(FS_OPCODE_TXL, dst); 806 break; 807 case ir_txd: { 808 this->result = reg_undef; 809 ir->lod_info.grad.dPdx->accept(this); 810 fs_reg dPdx = this->result; 811 812 this->result = reg_undef; 813 ir->lod_info.grad.dPdy->accept(this); 814 fs_reg dPdy = this->result; 815 816 mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */ 817 818 /** 819 * P = u, v, r 820 * dPdx = dudx, dvdx, drdx 821 * dPdy = dudy, dvdy, drdy 822 * 823 * Load up these values: 824 * - dudx dudy dvdx dvdy drdx drdy 825 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z 826 */ 827 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 828 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 829 dPdx.reg_offset++; 830 mlen += reg_width; 831 832 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 833 dPdy.reg_offset++; 834 mlen += reg_width; 835 } 836 837 inst = emit(FS_OPCODE_TXD, dst); 838 break; 839 } 840 case ir_txf: 841 case ir_txs: 842 assert(!"GLSL 1.30 features unsupported"); 843 break; 844 } 845 inst->base_mrf = base_mrf; 846 inst->mlen = mlen; 847 inst->header_present = header_present; 848 849 if (mlen > 11) { 850 fail("Message length >11 disallowed by hardware\n"); 851 } 852 853 return inst; 854} 855 856fs_inst * 857fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate, 858 int sampler) 859{ 860 int mlen = 0; 861 int base_mrf = 2; 862 int reg_width = c->dispatch_width / 8; 863 bool header_present = false; 864 865 if (ir->offset) { 866 /* The offsets set up by the ir_texture visitor are in the 867 * m1 header, so we can't go headerless. 868 */ 869 header_present = true; 870 mlen++; 871 base_mrf--; 872 } 873 874 if (ir->shadow_comparitor && ir->op != ir_txd) { 875 this->result = reg_undef; 876 ir->shadow_comparitor->accept(this); 877 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 878 mlen += reg_width; 879 } 880 881 /* Set up the LOD info */ 882 switch (ir->op) { 883 case ir_tex: 884 break; 885 case ir_txb: 886 this->result = reg_undef; 887 ir->lod_info.bias->accept(this); 888 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 889 mlen += reg_width; 890 break; 891 case ir_txl: 892 this->result = reg_undef; 893 ir->lod_info.lod->accept(this); 894 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 895 mlen += reg_width; 896 break; 897 case ir_txd: { 898 if (c->dispatch_width == 16) 899 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode."); 900 901 this->result = reg_undef; 902 ir->lod_info.grad.dPdx->accept(this); 903 fs_reg dPdx = this->result; 904 905 this->result = reg_undef; 906 ir->lod_info.grad.dPdy->accept(this); 907 fs_reg dPdy = this->result; 908 909 /* Load dPdx and the coordinate together: 910 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z 911 */ 912 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 913 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 914 coordinate); 915 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 916 inst->saturate = true; 917 coordinate.reg_offset++; 918 mlen += reg_width; 919 920 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 921 dPdx.reg_offset++; 922 mlen += reg_width; 923 924 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 925 dPdy.reg_offset++; 926 mlen += reg_width; 927 } 928 break; 929 } 930 case ir_txf: 931 case ir_txs: 932 assert(!"GLSL 1.30 features unsupported"); 933 break; 934 } 935 936 /* Set up the coordinate (except for TXD where it was done earlier) */ 937 if (ir->op != ir_txd) { 938 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 939 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 940 coordinate); 941 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 942 inst->saturate = true; 943 coordinate.reg_offset++; 944 mlen += reg_width; 945 } 946 } 947 948 /* Generate the SEND */ 949 fs_inst *inst = NULL; 950 switch (ir->op) { 951 case ir_tex: inst = emit(FS_OPCODE_TEX, dst); break; 952 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break; 953 case ir_txl: inst = emit(FS_OPCODE_TXL, dst); break; 954 case ir_txd: inst = emit(FS_OPCODE_TXD, dst); break; 955 case ir_txf: assert(!"TXF unsupported."); break; 956 case ir_txs: assert(!"TXS unsupported."); break; 957 } 958 inst->base_mrf = base_mrf; 959 inst->mlen = mlen; 960 inst->header_present = header_present; 961 962 if (mlen > 11) { 963 fail("Message length >11 disallowed by hardware\n"); 964 } 965 966 return inst; 967} 968 969void 970fs_visitor::visit(ir_texture *ir) 971{ 972 fs_inst *inst = NULL; 973 974 int sampler = _mesa_get_sampler_uniform_value(ir->sampler, prog, &fp->Base); 975 sampler = fp->Base.SamplerUnits[sampler]; 976 977 /* Our hardware doesn't have a sample_d_c message, so shadow compares 978 * for textureGrad/TXD need to be emulated with instructions. 979 */ 980 bool hw_compare_supported = ir->op != ir_txd; 981 if (ir->shadow_comparitor && !hw_compare_supported) { 982 assert(c->key.compare_funcs[sampler] != GL_NONE); 983 /* No need to even sample for GL_ALWAYS or GL_NEVER...bail early */ 984 if (c->key.compare_funcs[sampler] == GL_ALWAYS) 985 return swizzle_result(ir, fs_reg(1.0f), sampler); 986 else if (c->key.compare_funcs[sampler] == GL_NEVER) 987 return swizzle_result(ir, fs_reg(0.0f), sampler); 988 } 989 990 this->result = reg_undef; 991 ir->coordinate->accept(this); 992 fs_reg coordinate = this->result; 993 994 if (ir->offset != NULL) { 995 ir_constant *offset = ir->offset->as_constant(); 996 assert(offset != NULL); 997 998 signed char offsets[3]; 999 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) 1000 offsets[i] = (signed char) offset->value.i[i]; 1001 1002 /* Combine all three offsets into a single unsigned dword: 1003 * 1004 * bits 11:8 - U Offset (X component) 1005 * bits 7:4 - V Offset (Y component) 1006 * bits 3:0 - R Offset (Z component) 1007 */ 1008 unsigned offset_bits = 0; 1009 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) { 1010 const unsigned shift = 4 * (2 - i); 1011 offset_bits |= (offsets[i] << shift) & (0xF << shift); 1012 } 1013 1014 /* Explicitly set up the message header by copying g0 to msg reg m1. */ 1015 emit(BRW_OPCODE_MOV, fs_reg(MRF, 1, BRW_REGISTER_TYPE_UD), 1016 fs_reg(GRF, 0, BRW_REGISTER_TYPE_UD)); 1017 1018 /* Then set the offset bits in DWord 2 of the message header. */ 1019 emit(BRW_OPCODE_MOV, 1020 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 1, 2), 1021 BRW_REGISTER_TYPE_UD)), 1022 fs_reg(brw_imm_uw(offset_bits))); 1023 } 1024 1025 /* Should be lowered by do_lower_texture_projection */ 1026 assert(!ir->projector); 1027 1028 /* The 965 requires the EU to do the normalization of GL rectangle 1029 * texture coordinates. We use the program parameter state 1030 * tracking to get the scaling factor. 1031 */ 1032 if (ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) { 1033 struct gl_program_parameter_list *params = c->fp->program.Base.Parameters; 1034 int tokens[STATE_LENGTH] = { 1035 STATE_INTERNAL, 1036 STATE_TEXRECT_SCALE, 1037 sampler, 1038 0, 1039 0 1040 }; 1041 1042 if (c->dispatch_width == 16) { 1043 fail("rectangle scale uniform setup not supported on 16-wide\n"); 1044 this->result = fs_reg(this, ir->type); 1045 return; 1046 } 1047 1048 c->prog_data.param_convert[c->prog_data.nr_params] = 1049 PARAM_NO_CONVERT; 1050 c->prog_data.param_convert[c->prog_data.nr_params + 1] = 1051 PARAM_NO_CONVERT; 1052 1053 fs_reg scale_x = fs_reg(UNIFORM, c->prog_data.nr_params); 1054 fs_reg scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1); 1055 GLuint index = _mesa_add_state_reference(params, 1056 (gl_state_index *)tokens); 1057 1058 this->param_index[c->prog_data.nr_params] = index; 1059 this->param_offset[c->prog_data.nr_params] = 0; 1060 c->prog_data.nr_params++; 1061 this->param_index[c->prog_data.nr_params] = index; 1062 this->param_offset[c->prog_data.nr_params] = 1; 1063 c->prog_data.nr_params++; 1064 1065 fs_reg dst = fs_reg(this, ir->coordinate->type); 1066 fs_reg src = coordinate; 1067 coordinate = dst; 1068 1069 emit(BRW_OPCODE_MUL, dst, src, scale_x); 1070 dst.reg_offset++; 1071 src.reg_offset++; 1072 emit(BRW_OPCODE_MUL, dst, src, scale_y); 1073 } 1074 1075 /* Writemasking doesn't eliminate channels on SIMD8 texture 1076 * samples, so don't worry about them. 1077 */ 1078 fs_reg dst = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 4, 1)); 1079 1080 if (intel->gen >= 7) { 1081 inst = emit_texture_gen7(ir, dst, coordinate, sampler); 1082 } else if (intel->gen >= 5) { 1083 inst = emit_texture_gen5(ir, dst, coordinate, sampler); 1084 } else { 1085 inst = emit_texture_gen4(ir, dst, coordinate, sampler); 1086 } 1087 1088 /* If there's an offset, we already set up m1. To avoid the implied move, 1089 * use the null register. Otherwise, we want an implied move from g0. 1090 */ 1091 if (ir->offset != NULL || !inst->header_present) 1092 inst->src[0] = reg_undef; 1093 else 1094 inst->src[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW)); 1095 1096 inst->sampler = sampler; 1097 1098 if (ir->shadow_comparitor) { 1099 if (hw_compare_supported) { 1100 inst->shadow_compare = true; 1101 } else { 1102 this->result = reg_undef; 1103 ir->shadow_comparitor->accept(this); 1104 fs_reg ref = this->result; 1105 1106 fs_reg value = dst; 1107 dst = fs_reg(this, glsl_type::vec4_type); 1108 1109 /* FINISHME: This needs to be done pre-filtering. */ 1110 1111 uint32_t conditional = 0; 1112 switch (c->key.compare_funcs[sampler]) { 1113 /* GL_ALWAYS and GL_NEVER were handled at the top of the function */ 1114 case GL_LESS: conditional = BRW_CONDITIONAL_L; break; 1115 case GL_GREATER: conditional = BRW_CONDITIONAL_G; break; 1116 case GL_LEQUAL: conditional = BRW_CONDITIONAL_LE; break; 1117 case GL_GEQUAL: conditional = BRW_CONDITIONAL_GE; break; 1118 case GL_EQUAL: conditional = BRW_CONDITIONAL_EQ; break; 1119 case GL_NOTEQUAL: conditional = BRW_CONDITIONAL_NEQ; break; 1120 default: assert(!"Should not get here: bad shadow compare function"); 1121 } 1122 1123 /* Use conditional moves to load 0 or 1 as the result */ 1124 this->current_annotation = "manual shadow comparison"; 1125 for (int i = 0; i < 4; i++) { 1126 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(0.0f)); 1127 1128 inst = emit(BRW_OPCODE_CMP, reg_null_f, ref, value); 1129 inst->conditional_mod = conditional; 1130 1131 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(1.0f)); 1132 inst->predicated = true; 1133 1134 dst.reg_offset++; 1135 value.reg_offset++; 1136 } 1137 dst.reg_offset = 0; 1138 } 1139 } 1140 1141 swizzle_result(ir, dst, sampler); 1142} 1143 1144/** 1145 * Swizzle the result of a texture result. This is necessary for 1146 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons. 1147 */ 1148void 1149fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler) 1150{ 1151 this->result = orig_val; 1152 1153 if (ir->type == glsl_type::float_type) { 1154 /* Ignore DEPTH_TEXTURE_MODE swizzling. */ 1155 assert(ir->sampler->type->sampler_shadow); 1156 } else if (c->key.tex_swizzles[sampler] != SWIZZLE_NOOP) { 1157 fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type); 1158 1159 for (int i = 0; i < 4; i++) { 1160 int swiz = GET_SWZ(c->key.tex_swizzles[sampler], i); 1161 fs_reg l = swizzled_result; 1162 l.reg_offset += i; 1163 1164 if (swiz == SWIZZLE_ZERO) { 1165 emit(BRW_OPCODE_MOV, l, fs_reg(0.0f)); 1166 } else if (swiz == SWIZZLE_ONE) { 1167 emit(BRW_OPCODE_MOV, l, fs_reg(1.0f)); 1168 } else { 1169 fs_reg r = orig_val; 1170 r.reg_offset += GET_SWZ(c->key.tex_swizzles[sampler], i); 1171 emit(BRW_OPCODE_MOV, l, r); 1172 } 1173 } 1174 this->result = swizzled_result; 1175 } 1176} 1177 1178void 1179fs_visitor::visit(ir_swizzle *ir) 1180{ 1181 this->result = reg_undef; 1182 ir->val->accept(this); 1183 fs_reg val = this->result; 1184 1185 if (ir->type->vector_elements == 1) { 1186 this->result.reg_offset += ir->mask.x; 1187 return; 1188 } 1189 1190 fs_reg result = fs_reg(this, ir->type); 1191 this->result = result; 1192 1193 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 1194 fs_reg channel = val; 1195 int swiz = 0; 1196 1197 switch (i) { 1198 case 0: 1199 swiz = ir->mask.x; 1200 break; 1201 case 1: 1202 swiz = ir->mask.y; 1203 break; 1204 case 2: 1205 swiz = ir->mask.z; 1206 break; 1207 case 3: 1208 swiz = ir->mask.w; 1209 break; 1210 } 1211 1212 channel.reg_offset += swiz; 1213 emit(BRW_OPCODE_MOV, result, channel); 1214 result.reg_offset++; 1215 } 1216} 1217 1218void 1219fs_visitor::visit(ir_discard *ir) 1220{ 1221 assert(ir->condition == NULL); /* FINISHME */ 1222 1223 emit(FS_OPCODE_DISCARD); 1224 kill_emitted = true; 1225} 1226 1227void 1228fs_visitor::visit(ir_constant *ir) 1229{ 1230 /* Set this->result to reg at the bottom of the function because some code 1231 * paths will cause this visitor to be applied to other fields. This will 1232 * cause the value stored in this->result to be modified. 1233 * 1234 * Make reg constant so that it doesn't get accidentally modified along the 1235 * way. Yes, I actually had this problem. :( 1236 */ 1237 const fs_reg reg(this, ir->type); 1238 fs_reg dst_reg = reg; 1239 1240 if (ir->type->is_array()) { 1241 const unsigned size = type_size(ir->type->fields.array); 1242 1243 for (unsigned i = 0; i < ir->type->length; i++) { 1244 this->result = reg_undef; 1245 ir->array_elements[i]->accept(this); 1246 fs_reg src_reg = this->result; 1247 1248 dst_reg.type = src_reg.type; 1249 for (unsigned j = 0; j < size; j++) { 1250 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1251 src_reg.reg_offset++; 1252 dst_reg.reg_offset++; 1253 } 1254 } 1255 } else if (ir->type->is_record()) { 1256 foreach_list(node, &ir->components) { 1257 ir_instruction *const field = (ir_instruction *) node; 1258 const unsigned size = type_size(field->type); 1259 1260 this->result = reg_undef; 1261 field->accept(this); 1262 fs_reg src_reg = this->result; 1263 1264 dst_reg.type = src_reg.type; 1265 for (unsigned j = 0; j < size; j++) { 1266 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1267 src_reg.reg_offset++; 1268 dst_reg.reg_offset++; 1269 } 1270 } 1271 } else { 1272 const unsigned size = type_size(ir->type); 1273 1274 for (unsigned i = 0; i < size; i++) { 1275 switch (ir->type->base_type) { 1276 case GLSL_TYPE_FLOAT: 1277 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i])); 1278 break; 1279 case GLSL_TYPE_UINT: 1280 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i])); 1281 break; 1282 case GLSL_TYPE_INT: 1283 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.i[i])); 1284 break; 1285 case GLSL_TYPE_BOOL: 1286 emit(BRW_OPCODE_MOV, dst_reg, fs_reg((int)ir->value.b[i])); 1287 break; 1288 default: 1289 assert(!"Non-float/uint/int/bool constant"); 1290 } 1291 dst_reg.reg_offset++; 1292 } 1293 } 1294 1295 this->result = reg; 1296} 1297 1298void 1299fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir) 1300{ 1301 ir_expression *expr = ir->as_expression(); 1302 1303 if (expr) { 1304 fs_reg op[2]; 1305 fs_inst *inst; 1306 1307 assert(expr->get_num_operands() <= 2); 1308 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1309 assert(expr->operands[i]->type->is_scalar()); 1310 1311 this->result = reg_undef; 1312 expr->operands[i]->accept(this); 1313 op[i] = this->result; 1314 } 1315 1316 switch (expr->operation) { 1317 case ir_unop_logic_not: 1318 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1)); 1319 inst->conditional_mod = BRW_CONDITIONAL_Z; 1320 break; 1321 1322 case ir_binop_logic_xor: 1323 inst = emit(BRW_OPCODE_XOR, reg_null_d, op[0], op[1]); 1324 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1325 break; 1326 1327 case ir_binop_logic_or: 1328 inst = emit(BRW_OPCODE_OR, reg_null_d, op[0], op[1]); 1329 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1330 break; 1331 1332 case ir_binop_logic_and: 1333 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], op[1]); 1334 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1335 break; 1336 1337 case ir_unop_f2b: 1338 if (intel->gen >= 6) { 1339 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0.0f)); 1340 } else { 1341 inst = emit(BRW_OPCODE_MOV, reg_null_f, op[0]); 1342 } 1343 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1344 break; 1345 1346 case ir_unop_i2b: 1347 if (intel->gen >= 6) { 1348 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0)); 1349 } else { 1350 inst = emit(BRW_OPCODE_MOV, reg_null_d, op[0]); 1351 } 1352 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1353 break; 1354 1355 case ir_binop_greater: 1356 case ir_binop_gequal: 1357 case ir_binop_less: 1358 case ir_binop_lequal: 1359 case ir_binop_equal: 1360 case ir_binop_all_equal: 1361 case ir_binop_nequal: 1362 case ir_binop_any_nequal: 1363 inst = emit(BRW_OPCODE_CMP, reg_null_cmp, op[0], op[1]); 1364 inst->conditional_mod = 1365 brw_conditional_for_comparison(expr->operation); 1366 break; 1367 1368 default: 1369 assert(!"not reached"); 1370 fail("bad cond code\n"); 1371 break; 1372 } 1373 return; 1374 } 1375 1376 this->result = reg_undef; 1377 ir->accept(this); 1378 1379 if (intel->gen >= 6) { 1380 fs_inst *inst = emit(BRW_OPCODE_AND, reg_null_d, this->result, fs_reg(1)); 1381 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1382 } else { 1383 fs_inst *inst = emit(BRW_OPCODE_MOV, reg_null_d, this->result); 1384 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1385 } 1386} 1387 1388/** 1389 * Emit a gen6 IF statement with the comparison folded into the IF 1390 * instruction. 1391 */ 1392void 1393fs_visitor::emit_if_gen6(ir_if *ir) 1394{ 1395 ir_expression *expr = ir->condition->as_expression(); 1396 1397 if (expr) { 1398 fs_reg op[2]; 1399 fs_inst *inst; 1400 fs_reg temp; 1401 1402 assert(expr->get_num_operands() <= 2); 1403 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1404 assert(expr->operands[i]->type->is_scalar()); 1405 1406 this->result = reg_undef; 1407 expr->operands[i]->accept(this); 1408 op[i] = this->result; 1409 } 1410 1411 switch (expr->operation) { 1412 case ir_unop_logic_not: 1413 inst = emit(BRW_OPCODE_IF, temp, op[0], fs_reg(0)); 1414 inst->conditional_mod = BRW_CONDITIONAL_Z; 1415 return; 1416 1417 case ir_binop_logic_xor: 1418 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1419 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1420 return; 1421 1422 case ir_binop_logic_or: 1423 temp = fs_reg(this, glsl_type::bool_type); 1424 emit(BRW_OPCODE_OR, temp, op[0], op[1]); 1425 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1426 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1427 return; 1428 1429 case ir_binop_logic_and: 1430 temp = fs_reg(this, glsl_type::bool_type); 1431 emit(BRW_OPCODE_AND, temp, op[0], op[1]); 1432 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1433 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1434 return; 1435 1436 case ir_unop_f2b: 1437 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0)); 1438 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1439 return; 1440 1441 case ir_unop_i2b: 1442 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1443 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1444 return; 1445 1446 case ir_binop_greater: 1447 case ir_binop_gequal: 1448 case ir_binop_less: 1449 case ir_binop_lequal: 1450 case ir_binop_equal: 1451 case ir_binop_all_equal: 1452 case ir_binop_nequal: 1453 case ir_binop_any_nequal: 1454 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1455 inst->conditional_mod = 1456 brw_conditional_for_comparison(expr->operation); 1457 return; 1458 default: 1459 assert(!"not reached"); 1460 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1461 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1462 fail("bad condition\n"); 1463 return; 1464 } 1465 return; 1466 } 1467 1468 this->result = reg_undef; 1469 ir->condition->accept(this); 1470 1471 fs_inst *inst = emit(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0)); 1472 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1473} 1474 1475void 1476fs_visitor::visit(ir_if *ir) 1477{ 1478 fs_inst *inst; 1479 1480 if (intel->gen != 6 && c->dispatch_width == 16) { 1481 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1482 } 1483 1484 /* Don't point the annotation at the if statement, because then it plus 1485 * the then and else blocks get printed. 1486 */ 1487 this->base_ir = ir->condition; 1488 1489 if (intel->gen == 6) { 1490 emit_if_gen6(ir); 1491 } else { 1492 emit_bool_to_cond_code(ir->condition); 1493 1494 inst = emit(BRW_OPCODE_IF); 1495 inst->predicated = true; 1496 } 1497 1498 foreach_list(node, &ir->then_instructions) { 1499 ir_instruction *ir = (ir_instruction *)node; 1500 this->base_ir = ir; 1501 this->result = reg_undef; 1502 ir->accept(this); 1503 } 1504 1505 if (!ir->else_instructions.is_empty()) { 1506 emit(BRW_OPCODE_ELSE); 1507 1508 foreach_list(node, &ir->else_instructions) { 1509 ir_instruction *ir = (ir_instruction *)node; 1510 this->base_ir = ir; 1511 this->result = reg_undef; 1512 ir->accept(this); 1513 } 1514 } 1515 1516 emit(BRW_OPCODE_ENDIF); 1517} 1518 1519void 1520fs_visitor::visit(ir_loop *ir) 1521{ 1522 fs_reg counter = reg_undef; 1523 1524 if (c->dispatch_width == 16) { 1525 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1526 } 1527 1528 if (ir->counter) { 1529 this->base_ir = ir->counter; 1530 ir->counter->accept(this); 1531 counter = *(variable_storage(ir->counter)); 1532 1533 if (ir->from) { 1534 this->result = counter; 1535 1536 this->base_ir = ir->from; 1537 this->result = counter; 1538 ir->from->accept(this); 1539 1540 if (!this->result.equals(&counter)) 1541 emit(BRW_OPCODE_MOV, counter, this->result); 1542 } 1543 } 1544 1545 emit(BRW_OPCODE_DO); 1546 1547 if (ir->to) { 1548 this->base_ir = ir->to; 1549 this->result = reg_undef; 1550 ir->to->accept(this); 1551 1552 fs_inst *inst = emit(BRW_OPCODE_CMP, reg_null_cmp, counter, this->result); 1553 inst->conditional_mod = brw_conditional_for_comparison(ir->cmp); 1554 1555 inst = emit(BRW_OPCODE_BREAK); 1556 inst->predicated = true; 1557 } 1558 1559 foreach_list(node, &ir->body_instructions) { 1560 ir_instruction *ir = (ir_instruction *)node; 1561 1562 this->base_ir = ir; 1563 this->result = reg_undef; 1564 ir->accept(this); 1565 } 1566 1567 if (ir->increment) { 1568 this->base_ir = ir->increment; 1569 this->result = reg_undef; 1570 ir->increment->accept(this); 1571 emit(BRW_OPCODE_ADD, counter, counter, this->result); 1572 } 1573 1574 emit(BRW_OPCODE_WHILE); 1575} 1576 1577void 1578fs_visitor::visit(ir_loop_jump *ir) 1579{ 1580 switch (ir->mode) { 1581 case ir_loop_jump::jump_break: 1582 emit(BRW_OPCODE_BREAK); 1583 break; 1584 case ir_loop_jump::jump_continue: 1585 emit(BRW_OPCODE_CONTINUE); 1586 break; 1587 } 1588} 1589 1590void 1591fs_visitor::visit(ir_call *ir) 1592{ 1593 assert(!"FINISHME"); 1594} 1595 1596void 1597fs_visitor::visit(ir_return *ir) 1598{ 1599 assert(!"FINISHME"); 1600} 1601 1602void 1603fs_visitor::visit(ir_function *ir) 1604{ 1605 /* Ignore function bodies other than main() -- we shouldn't see calls to 1606 * them since they should all be inlined before we get to ir_to_mesa. 1607 */ 1608 if (strcmp(ir->name, "main") == 0) { 1609 const ir_function_signature *sig; 1610 exec_list empty; 1611 1612 sig = ir->matching_signature(&empty); 1613 1614 assert(sig); 1615 1616 foreach_list(node, &sig->body) { 1617 ir_instruction *ir = (ir_instruction *)node; 1618 this->base_ir = ir; 1619 this->result = reg_undef; 1620 ir->accept(this); 1621 } 1622 } 1623} 1624 1625void 1626fs_visitor::visit(ir_function_signature *ir) 1627{ 1628 assert(!"not reached"); 1629 (void)ir; 1630} 1631 1632fs_inst * 1633fs_visitor::emit(fs_inst inst) 1634{ 1635 fs_inst *list_inst = new(mem_ctx) fs_inst; 1636 *list_inst = inst; 1637 1638 if (force_uncompressed_stack > 0) 1639 list_inst->force_uncompressed = true; 1640 else if (force_sechalf_stack > 0) 1641 list_inst->force_sechalf = true; 1642 1643 list_inst->annotation = this->current_annotation; 1644 list_inst->ir = this->base_ir; 1645 1646 this->instructions.push_tail(list_inst); 1647 1648 return list_inst; 1649} 1650 1651/** Emits a dummy fragment shader consisting of magenta for bringup purposes. */ 1652void 1653fs_visitor::emit_dummy_fs() 1654{ 1655 /* Everyone's favorite color. */ 1656 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2), fs_reg(1.0f)); 1657 emit(BRW_OPCODE_MOV, fs_reg(MRF, 3), fs_reg(0.0f)); 1658 emit(BRW_OPCODE_MOV, fs_reg(MRF, 4), fs_reg(1.0f)); 1659 emit(BRW_OPCODE_MOV, fs_reg(MRF, 5), fs_reg(0.0f)); 1660 1661 fs_inst *write; 1662 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0)); 1663 write->base_mrf = 2; 1664} 1665 1666/* The register location here is relative to the start of the URB 1667 * data. It will get adjusted to be a real location before 1668 * generate_code() time. 1669 */ 1670struct brw_reg 1671fs_visitor::interp_reg(int location, int channel) 1672{ 1673 int regnr = urb_setup[location] * 2 + channel / 2; 1674 int stride = (channel & 1) * 4; 1675 1676 assert(urb_setup[location] != -1); 1677 1678 return brw_vec1_grf(regnr, stride); 1679} 1680 1681/** Emits the interpolation for the varying inputs. */ 1682void 1683fs_visitor::emit_interpolation_setup_gen4() 1684{ 1685 this->current_annotation = "compute pixel centers"; 1686 this->pixel_x = fs_reg(this, glsl_type::uint_type); 1687 this->pixel_y = fs_reg(this, glsl_type::uint_type); 1688 this->pixel_x.type = BRW_REGISTER_TYPE_UW; 1689 this->pixel_y.type = BRW_REGISTER_TYPE_UW; 1690 1691 emit(FS_OPCODE_PIXEL_X, this->pixel_x); 1692 emit(FS_OPCODE_PIXEL_Y, this->pixel_y); 1693 1694 this->current_annotation = "compute pixel deltas from v0"; 1695 if (brw->has_pln) { 1696 this->delta_x = fs_reg(this, glsl_type::vec2_type); 1697 this->delta_y = this->delta_x; 1698 this->delta_y.reg_offset++; 1699 } else { 1700 this->delta_x = fs_reg(this, glsl_type::float_type); 1701 this->delta_y = fs_reg(this, glsl_type::float_type); 1702 } 1703 emit(BRW_OPCODE_ADD, this->delta_x, 1704 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))); 1705 emit(BRW_OPCODE_ADD, this->delta_y, 1706 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))); 1707 1708 this->current_annotation = "compute pos.w and 1/pos.w"; 1709 /* Compute wpos.w. It's always in our setup, since it's needed to 1710 * interpolate the other attributes. 1711 */ 1712 this->wpos_w = fs_reg(this, glsl_type::float_type); 1713 emit(FS_OPCODE_LINTERP, wpos_w, this->delta_x, this->delta_y, 1714 interp_reg(FRAG_ATTRIB_WPOS, 3)); 1715 /* Compute the pixel 1/W value from wpos.w. */ 1716 this->pixel_w = fs_reg(this, glsl_type::float_type); 1717 emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w); 1718 this->current_annotation = NULL; 1719} 1720 1721/** Emits the interpolation for the varying inputs. */ 1722void 1723fs_visitor::emit_interpolation_setup_gen6() 1724{ 1725 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); 1726 1727 /* If the pixel centers end up used, the setup is the same as for gen4. */ 1728 this->current_annotation = "compute pixel centers"; 1729 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type); 1730 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type); 1731 int_pixel_x.type = BRW_REGISTER_TYPE_UW; 1732 int_pixel_y.type = BRW_REGISTER_TYPE_UW; 1733 emit(BRW_OPCODE_ADD, 1734 int_pixel_x, 1735 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), 1736 fs_reg(brw_imm_v(0x10101010))); 1737 emit(BRW_OPCODE_ADD, 1738 int_pixel_y, 1739 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), 1740 fs_reg(brw_imm_v(0x11001100))); 1741 1742 /* As of gen6, we can no longer mix float and int sources. We have 1743 * to turn the integer pixel centers into floats for their actual 1744 * use. 1745 */ 1746 this->pixel_x = fs_reg(this, glsl_type::float_type); 1747 this->pixel_y = fs_reg(this, glsl_type::float_type); 1748 emit(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x); 1749 emit(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y); 1750 1751 this->current_annotation = "compute pos.w"; 1752 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0)); 1753 this->wpos_w = fs_reg(this, glsl_type::float_type); 1754 emit_math(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w); 1755 1756 this->delta_x = fs_reg(brw_vec8_grf(2, 0)); 1757 this->delta_y = fs_reg(brw_vec8_grf(3, 0)); 1758 1759 this->current_annotation = NULL; 1760} 1761 1762void 1763fs_visitor::emit_color_write(int index, int first_color_mrf, fs_reg color) 1764{ 1765 int reg_width = c->dispatch_width / 8; 1766 fs_inst *inst; 1767 1768 if (c->dispatch_width == 8 || intel->gen == 6) { 1769 /* SIMD8 write looks like: 1770 * m + 0: r0 1771 * m + 1: r1 1772 * m + 2: g0 1773 * m + 3: g1 1774 * 1775 * gen6 SIMD16 DP write looks like: 1776 * m + 0: r0 1777 * m + 1: r1 1778 * m + 2: g0 1779 * m + 3: g1 1780 * m + 4: b0 1781 * m + 5: b1 1782 * m + 6: a0 1783 * m + 7: a1 1784 */ 1785 inst = emit(BRW_OPCODE_MOV, 1786 fs_reg(MRF, first_color_mrf + index * reg_width), 1787 color); 1788 inst->saturate = c->key.clamp_fragment_color; 1789 } else { 1790 /* pre-gen6 SIMD16 single source DP write looks like: 1791 * m + 0: r0 1792 * m + 1: g0 1793 * m + 2: b0 1794 * m + 3: a0 1795 * m + 4: r1 1796 * m + 5: g1 1797 * m + 6: b1 1798 * m + 7: a1 1799 */ 1800 if (brw->has_compr4) { 1801 /* By setting the high bit of the MRF register number, we 1802 * indicate that we want COMPR4 mode - instead of doing the 1803 * usual destination + 1 for the second half we get 1804 * destination + 4. 1805 */ 1806 inst = emit(BRW_OPCODE_MOV, 1807 fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index), 1808 color); 1809 inst->saturate = c->key.clamp_fragment_color; 1810 } else { 1811 push_force_uncompressed(); 1812 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index), 1813 color); 1814 inst->saturate = c->key.clamp_fragment_color; 1815 pop_force_uncompressed(); 1816 1817 push_force_sechalf(); 1818 color.sechalf = true; 1819 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index + 4), 1820 color); 1821 inst->saturate = c->key.clamp_fragment_color; 1822 pop_force_sechalf(); 1823 color.sechalf = false; 1824 } 1825 } 1826} 1827 1828void 1829fs_visitor::emit_fb_writes() 1830{ 1831 this->current_annotation = "FB write header"; 1832 GLboolean header_present = GL_TRUE; 1833 int base_mrf = 2; 1834 int nr = base_mrf; 1835 int reg_width = c->dispatch_width / 8; 1836 1837 if (intel->gen >= 6 && 1838 !this->kill_emitted && 1839 c->key.nr_color_regions == 1) { 1840 header_present = false; 1841 } 1842 1843 if (header_present) { 1844 /* m2, m3 header */ 1845 nr += 2; 1846 } 1847 1848 if (c->aa_dest_stencil_reg) { 1849 push_force_uncompressed(); 1850 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++), 1851 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))); 1852 pop_force_uncompressed(); 1853 } 1854 1855 /* Reserve space for color. It'll be filled in per MRT below. */ 1856 int color_mrf = nr; 1857 nr += 4 * reg_width; 1858 1859 if (c->source_depth_to_render_target) { 1860 if (intel->gen == 6 && c->dispatch_width == 16) { 1861 /* For outputting oDepth on gen6, SIMD8 writes have to be 1862 * used. This would require 8-wide moves of each half to 1863 * message regs, kind of like pre-gen5 SIMD16 FB writes. 1864 * Just bail on doing so for now. 1865 */ 1866 fail("Missing support for simd16 depth writes on gen6\n"); 1867 } 1868 1869 if (c->computes_depth) { 1870 /* Hand over gl_FragDepth. */ 1871 assert(this->frag_depth); 1872 fs_reg depth = *(variable_storage(this->frag_depth)); 1873 1874 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), depth); 1875 } else { 1876 /* Pass through the payload depth. */ 1877 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1878 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))); 1879 } 1880 nr += reg_width; 1881 } 1882 1883 if (c->dest_depth_reg) { 1884 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1885 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))); 1886 nr += reg_width; 1887 } 1888 1889 fs_reg color = reg_undef; 1890 if (this->frag_color) 1891 color = *(variable_storage(this->frag_color)); 1892 else if (this->frag_data) { 1893 color = *(variable_storage(this->frag_data)); 1894 color.type = BRW_REGISTER_TYPE_F; 1895 } 1896 1897 for (int target = 0; target < c->key.nr_color_regions; target++) { 1898 this->current_annotation = ralloc_asprintf(this->mem_ctx, 1899 "FB write target %d", 1900 target); 1901 if (this->frag_color || this->frag_data) { 1902 for (int i = 0; i < 4; i++) { 1903 emit_color_write(i, color_mrf, color); 1904 color.reg_offset++; 1905 } 1906 } 1907 1908 if (this->frag_color) 1909 color.reg_offset -= 4; 1910 1911 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1912 inst->target = target; 1913 inst->base_mrf = base_mrf; 1914 inst->mlen = nr - base_mrf; 1915 if (target == c->key.nr_color_regions - 1) 1916 inst->eot = true; 1917 inst->header_present = header_present; 1918 } 1919 1920 if (c->key.nr_color_regions == 0) { 1921 if (c->key.alpha_test && (this->frag_color || this->frag_data)) { 1922 /* If the alpha test is enabled but there's no color buffer, 1923 * we still need to send alpha out the pipeline to our null 1924 * renderbuffer. 1925 */ 1926 color.reg_offset += 3; 1927 emit_color_write(3, color_mrf, color); 1928 } 1929 1930 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1931 inst->base_mrf = base_mrf; 1932 inst->mlen = nr - base_mrf; 1933 inst->eot = true; 1934 inst->header_present = header_present; 1935 } 1936 1937 this->current_annotation = NULL; 1938} 1939