brw_fs_visitor.cpp revision d1f70a8a6c6ec7007bad22d3d6013415be2d243a
1/* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24/** @file brw_fs_visitor.cpp 25 * 26 * This file supports generating the FS LIR from the GLSL IR. The LIR 27 * makes it easier to do backend-specific optimizations than doing so 28 * in the GLSL IR or in the native code. 29 */ 30extern "C" { 31 32#include <sys/types.h> 33 34#include "main/macros.h" 35#include "main/shaderobj.h" 36#include "main/uniforms.h" 37#include "program/prog_parameter.h" 38#include "program/prog_print.h" 39#include "program/prog_optimize.h" 40#include "program/register_allocate.h" 41#include "program/sampler.h" 42#include "program/hash_table.h" 43#include "brw_context.h" 44#include "brw_eu.h" 45#include "brw_wm.h" 46} 47#include "brw_shader.h" 48#include "brw_fs.h" 49#include "../glsl/glsl_types.h" 50#include "../glsl/ir_optimization.h" 51#include "../glsl/ir_print_visitor.h" 52 53void 54fs_visitor::visit(ir_variable *ir) 55{ 56 fs_reg *reg = NULL; 57 58 if (variable_storage(ir)) 59 return; 60 61 if (strcmp(ir->name, "gl_FragColor") == 0) { 62 this->frag_color = ir; 63 } else if (strcmp(ir->name, "gl_FragData") == 0) { 64 this->frag_data = ir; 65 } else if (strcmp(ir->name, "gl_FragDepth") == 0) { 66 this->frag_depth = ir; 67 } 68 69 if (ir->mode == ir_var_in) { 70 if (!strcmp(ir->name, "gl_FragCoord")) { 71 reg = emit_fragcoord_interpolation(ir); 72 } else if (!strcmp(ir->name, "gl_FrontFacing")) { 73 reg = emit_frontfacing_interpolation(ir); 74 } else { 75 reg = emit_general_interpolation(ir); 76 } 77 assert(reg); 78 hash_table_insert(this->variable_ht, reg, ir); 79 return; 80 } 81 82 if (ir->mode == ir_var_uniform) { 83 int param_index = c->prog_data.nr_params; 84 85 if (c->dispatch_width == 16) { 86 if (!variable_storage(ir)) { 87 fail("Failed to find uniform '%s' in 16-wide\n", ir->name); 88 } 89 return; 90 } 91 92 if (!strncmp(ir->name, "gl_", 3)) { 93 setup_builtin_uniform_values(ir); 94 } else { 95 setup_uniform_values(ir->location, ir->type); 96 } 97 98 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index); 99 reg->type = brw_type_for_base_type(ir->type); 100 } 101 102 if (!reg) 103 reg = new(this->mem_ctx) fs_reg(this, ir->type); 104 105 hash_table_insert(this->variable_ht, reg, ir); 106} 107 108void 109fs_visitor::visit(ir_dereference_variable *ir) 110{ 111 fs_reg *reg = variable_storage(ir->var); 112 this->result = *reg; 113} 114 115void 116fs_visitor::visit(ir_dereference_record *ir) 117{ 118 const glsl_type *struct_type = ir->record->type; 119 120 ir->record->accept(this); 121 122 unsigned int offset = 0; 123 for (unsigned int i = 0; i < struct_type->length; i++) { 124 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0) 125 break; 126 offset += type_size(struct_type->fields.structure[i].type); 127 } 128 this->result.reg_offset += offset; 129 this->result.type = brw_type_for_base_type(ir->type); 130} 131 132void 133fs_visitor::visit(ir_dereference_array *ir) 134{ 135 ir_constant *index; 136 int element_size; 137 138 ir->array->accept(this); 139 index = ir->array_index->as_constant(); 140 141 element_size = type_size(ir->type); 142 this->result.type = brw_type_for_base_type(ir->type); 143 144 if (index) { 145 assert(this->result.file == UNIFORM || 146 (this->result.file == GRF && 147 this->result.reg != 0)); 148 this->result.reg_offset += index->value.i[0] * element_size; 149 } else { 150 assert(!"FINISHME: non-constant array element"); 151 } 152} 153 154/* Instruction selection: Produce a MOV.sat instead of 155 * MIN(MAX(val, 0), 1) when possible. 156 */ 157bool 158fs_visitor::try_emit_saturate(ir_expression *ir) 159{ 160 ir_rvalue *sat_val = ir->as_rvalue_to_saturate(); 161 162 if (!sat_val) 163 return false; 164 165 this->result = reg_undef; 166 sat_val->accept(this); 167 fs_reg src = this->result; 168 169 this->result = fs_reg(this, ir->type); 170 fs_inst *inst = emit(BRW_OPCODE_MOV, this->result, src); 171 inst->saturate = true; 172 173 return true; 174} 175 176void 177fs_visitor::visit(ir_expression *ir) 178{ 179 unsigned int operand; 180 fs_reg op[2], temp; 181 fs_inst *inst; 182 183 assert(ir->get_num_operands() <= 2); 184 185 if (try_emit_saturate(ir)) 186 return; 187 188 /* This is where our caller would like us to put the result, if possible. */ 189 fs_reg saved_result_storage = this->result; 190 191 for (operand = 0; operand < ir->get_num_operands(); operand++) { 192 this->result = reg_undef; 193 ir->operands[operand]->accept(this); 194 if (this->result.file == BAD_FILE) { 195 ir_print_visitor v; 196 fail("Failed to get tree for expression operand:\n"); 197 ir->operands[operand]->accept(&v); 198 } 199 op[operand] = this->result; 200 201 /* Matrix expression operands should have been broken down to vector 202 * operations already. 203 */ 204 assert(!ir->operands[operand]->type->is_matrix()); 205 /* And then those vector operands should have been broken down to scalar. 206 */ 207 assert(!ir->operands[operand]->type->is_vector()); 208 } 209 210 /* Inherit storage from our parent if possible, and otherwise we 211 * alloc a temporary. 212 */ 213 if (saved_result_storage.file == BAD_FILE) { 214 this->result = fs_reg(this, ir->type); 215 } else { 216 this->result = saved_result_storage; 217 } 218 219 switch (ir->operation) { 220 case ir_unop_logic_not: 221 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is 222 * ones complement of the whole register, not just bit 0. 223 */ 224 emit(BRW_OPCODE_XOR, this->result, op[0], fs_reg(1)); 225 break; 226 case ir_unop_neg: 227 op[0].negate = !op[0].negate; 228 this->result = op[0]; 229 break; 230 case ir_unop_abs: 231 op[0].abs = true; 232 op[0].negate = false; 233 this->result = op[0]; 234 break; 235 case ir_unop_sign: 236 temp = fs_reg(this, ir->type); 237 238 /* Unalias the destination. (imagine a = sign(a)) */ 239 this->result = fs_reg(this, ir->type); 240 241 emit(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)); 242 243 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 244 inst->conditional_mod = BRW_CONDITIONAL_G; 245 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)); 246 inst->predicated = true; 247 248 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 249 inst->conditional_mod = BRW_CONDITIONAL_L; 250 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)); 251 inst->predicated = true; 252 253 break; 254 case ir_unop_rcp: 255 emit_math(FS_OPCODE_RCP, this->result, op[0]); 256 break; 257 258 case ir_unop_exp2: 259 emit_math(FS_OPCODE_EXP2, this->result, op[0]); 260 break; 261 case ir_unop_log2: 262 emit_math(FS_OPCODE_LOG2, this->result, op[0]); 263 break; 264 case ir_unop_exp: 265 case ir_unop_log: 266 assert(!"not reached: should be handled by ir_explog_to_explog2"); 267 break; 268 case ir_unop_sin: 269 case ir_unop_sin_reduced: 270 emit_math(FS_OPCODE_SIN, this->result, op[0]); 271 break; 272 case ir_unop_cos: 273 case ir_unop_cos_reduced: 274 emit_math(FS_OPCODE_COS, this->result, op[0]); 275 break; 276 277 case ir_unop_dFdx: 278 emit(FS_OPCODE_DDX, this->result, op[0]); 279 break; 280 case ir_unop_dFdy: 281 emit(FS_OPCODE_DDY, this->result, op[0]); 282 break; 283 284 case ir_binop_add: 285 emit(BRW_OPCODE_ADD, this->result, op[0], op[1]); 286 break; 287 case ir_binop_sub: 288 assert(!"not reached: should be handled by ir_sub_to_add_neg"); 289 break; 290 291 case ir_binop_mul: 292 emit(BRW_OPCODE_MUL, this->result, op[0], op[1]); 293 break; 294 case ir_binop_div: 295 assert(!"not reached: should be handled by ir_div_to_mul_rcp"); 296 break; 297 case ir_binop_mod: 298 assert(!"ir_binop_mod should have been converted to b * fract(a/b)"); 299 break; 300 301 case ir_binop_less: 302 case ir_binop_greater: 303 case ir_binop_lequal: 304 case ir_binop_gequal: 305 case ir_binop_equal: 306 case ir_binop_all_equal: 307 case ir_binop_nequal: 308 case ir_binop_any_nequal: 309 temp = this->result; 310 /* original gen4 does implicit conversion before comparison. */ 311 if (intel->gen < 5) 312 temp.type = op[0].type; 313 314 inst = emit(BRW_OPCODE_CMP, temp, op[0], op[1]); 315 inst->conditional_mod = brw_conditional_for_comparison(ir->operation); 316 emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)); 317 break; 318 319 case ir_binop_logic_xor: 320 emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 321 break; 322 323 case ir_binop_logic_or: 324 emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 325 break; 326 327 case ir_binop_logic_and: 328 emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 329 break; 330 331 case ir_binop_dot: 332 case ir_unop_any: 333 assert(!"not reached: should be handled by brw_fs_channel_expressions"); 334 break; 335 336 case ir_unop_noise: 337 assert(!"not reached: should be handled by lower_noise"); 338 break; 339 340 case ir_quadop_vector: 341 assert(!"not reached: should be handled by lower_quadop_vector"); 342 break; 343 344 case ir_unop_sqrt: 345 emit_math(FS_OPCODE_SQRT, this->result, op[0]); 346 break; 347 348 case ir_unop_rsq: 349 emit_math(FS_OPCODE_RSQ, this->result, op[0]); 350 break; 351 352 case ir_unop_i2f: 353 case ir_unop_b2f: 354 case ir_unop_b2i: 355 case ir_unop_f2i: 356 emit(BRW_OPCODE_MOV, this->result, op[0]); 357 break; 358 case ir_unop_f2b: 359 case ir_unop_i2b: 360 temp = this->result; 361 /* original gen4 does implicit conversion before comparison. */ 362 if (intel->gen < 5) 363 temp.type = op[0].type; 364 365 inst = emit(BRW_OPCODE_CMP, temp, op[0], fs_reg(0.0f)); 366 inst->conditional_mod = BRW_CONDITIONAL_NZ; 367 inst = emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(1)); 368 break; 369 370 case ir_unop_trunc: 371 emit(BRW_OPCODE_RNDZ, this->result, op[0]); 372 break; 373 case ir_unop_ceil: 374 op[0].negate = !op[0].negate; 375 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 376 this->result.negate = true; 377 break; 378 case ir_unop_floor: 379 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 380 break; 381 case ir_unop_fract: 382 inst = emit(BRW_OPCODE_FRC, this->result, op[0]); 383 break; 384 case ir_unop_round_even: 385 emit(BRW_OPCODE_RNDE, this->result, op[0]); 386 break; 387 388 case ir_binop_min: 389 /* Unalias the destination */ 390 this->result = fs_reg(this, ir->type); 391 392 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 393 inst->conditional_mod = BRW_CONDITIONAL_L; 394 395 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 396 inst->predicated = true; 397 break; 398 case ir_binop_max: 399 /* Unalias the destination */ 400 this->result = fs_reg(this, ir->type); 401 402 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 403 inst->conditional_mod = BRW_CONDITIONAL_G; 404 405 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 406 inst->predicated = true; 407 break; 408 409 case ir_binop_pow: 410 emit_math(FS_OPCODE_POW, this->result, op[0], op[1]); 411 break; 412 413 case ir_unop_bit_not: 414 inst = emit(BRW_OPCODE_NOT, this->result, op[0]); 415 break; 416 case ir_binop_bit_and: 417 inst = emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 418 break; 419 case ir_binop_bit_xor: 420 inst = emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 421 break; 422 case ir_binop_bit_or: 423 inst = emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 424 break; 425 426 case ir_unop_u2f: 427 case ir_binop_lshift: 428 case ir_binop_rshift: 429 assert(!"GLSL 1.30 features unsupported"); 430 break; 431 } 432} 433 434void 435fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r, 436 const glsl_type *type, bool predicated) 437{ 438 switch (type->base_type) { 439 case GLSL_TYPE_FLOAT: 440 case GLSL_TYPE_UINT: 441 case GLSL_TYPE_INT: 442 case GLSL_TYPE_BOOL: 443 for (unsigned int i = 0; i < type->components(); i++) { 444 l.type = brw_type_for_base_type(type); 445 r.type = brw_type_for_base_type(type); 446 447 if (predicated || !l.equals(&r)) { 448 fs_inst *inst = emit(BRW_OPCODE_MOV, l, r); 449 inst->predicated = predicated; 450 } 451 452 l.reg_offset++; 453 r.reg_offset++; 454 } 455 break; 456 case GLSL_TYPE_ARRAY: 457 for (unsigned int i = 0; i < type->length; i++) { 458 emit_assignment_writes(l, r, type->fields.array, predicated); 459 } 460 break; 461 462 case GLSL_TYPE_STRUCT: 463 for (unsigned int i = 0; i < type->length; i++) { 464 emit_assignment_writes(l, r, type->fields.structure[i].type, 465 predicated); 466 } 467 break; 468 469 case GLSL_TYPE_SAMPLER: 470 break; 471 472 default: 473 assert(!"not reached"); 474 break; 475 } 476} 477 478void 479fs_visitor::visit(ir_assignment *ir) 480{ 481 struct fs_reg l, r; 482 fs_inst *inst; 483 484 /* FINISHME: arrays on the lhs */ 485 this->result = reg_undef; 486 ir->lhs->accept(this); 487 l = this->result; 488 489 /* If we're doing a direct assignment, an RHS expression could 490 * drop its result right into our destination. Otherwise, tell it 491 * not to. 492 */ 493 if (ir->condition || 494 !(ir->lhs->type->is_scalar() || 495 (ir->lhs->type->is_vector() && 496 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1))) { 497 this->result = reg_undef; 498 } 499 500 ir->rhs->accept(this); 501 r = this->result; 502 503 assert(l.file != BAD_FILE); 504 assert(r.file != BAD_FILE); 505 506 if (ir->condition) { 507 emit_bool_to_cond_code(ir->condition); 508 } 509 510 if (ir->lhs->type->is_scalar() || 511 ir->lhs->type->is_vector()) { 512 for (int i = 0; i < ir->lhs->type->vector_elements; i++) { 513 if (ir->write_mask & (1 << i)) { 514 if (ir->condition) { 515 inst = emit(BRW_OPCODE_MOV, l, r); 516 inst->predicated = true; 517 } else if (!l.equals(&r)) { 518 inst = emit(BRW_OPCODE_MOV, l, r); 519 } 520 521 r.reg_offset++; 522 } 523 l.reg_offset++; 524 } 525 } else { 526 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL); 527 } 528} 529 530fs_inst * 531fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate, 532 int sampler) 533{ 534 int mlen; 535 int base_mrf = 1; 536 bool simd16 = false; 537 fs_reg orig_dst; 538 539 /* g0 header. */ 540 mlen = 1; 541 542 if (ir->shadow_comparitor) { 543 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 544 fs_inst *inst = emit(BRW_OPCODE_MOV, 545 fs_reg(MRF, base_mrf + mlen + i), coordinate); 546 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 547 inst->saturate = true; 548 549 coordinate.reg_offset++; 550 } 551 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 552 mlen += 3; 553 554 if (ir->op == ir_tex) { 555 /* There's no plain shadow compare message, so we use shadow 556 * compare with a bias of 0.0. 557 */ 558 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)); 559 mlen++; 560 } else if (ir->op == ir_txb) { 561 this->result = reg_undef; 562 ir->lod_info.bias->accept(this); 563 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 564 mlen++; 565 } else { 566 assert(ir->op == ir_txl); 567 this->result = reg_undef; 568 ir->lod_info.lod->accept(this); 569 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 570 mlen++; 571 } 572 573 this->result = reg_undef; 574 ir->shadow_comparitor->accept(this); 575 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 576 mlen++; 577 } else if (ir->op == ir_tex) { 578 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 579 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), 580 coordinate); 581 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 582 inst->saturate = true; 583 coordinate.reg_offset++; 584 } 585 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 586 mlen += 3; 587 } else if (ir->op == ir_txd) { 588 assert(!"TXD isn't supported on gen4 yet."); 589 } else { 590 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod 591 * instructions. We'll need to do SIMD16 here. 592 */ 593 assert(ir->op == ir_txb || ir->op == ir_txl); 594 595 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 596 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, 597 base_mrf + mlen + i * 2), 598 coordinate); 599 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 600 inst->saturate = true; 601 coordinate.reg_offset++; 602 } 603 604 /* lod/bias appears after u/v/r. */ 605 mlen += 6; 606 607 if (ir->op == ir_txb) { 608 this->result = reg_undef; 609 ir->lod_info.bias->accept(this); 610 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 611 mlen++; 612 } else { 613 this->result = reg_undef; 614 ir->lod_info.lod->accept(this); 615 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 616 mlen++; 617 } 618 619 /* The unused upper half. */ 620 mlen++; 621 622 /* Now, since we're doing simd16, the return is 2 interleaved 623 * vec4s where the odd-indexed ones are junk. We'll need to move 624 * this weirdness around to the expected layout. 625 */ 626 simd16 = true; 627 orig_dst = dst; 628 dst = fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type, 629 2)); 630 dst.type = BRW_REGISTER_TYPE_F; 631 } 632 633 fs_inst *inst = NULL; 634 switch (ir->op) { 635 case ir_tex: 636 inst = emit(FS_OPCODE_TEX, dst); 637 break; 638 case ir_txb: 639 inst = emit(FS_OPCODE_TXB, dst); 640 break; 641 case ir_txl: 642 inst = emit(FS_OPCODE_TXL, dst); 643 break; 644 case ir_txd: 645 inst = emit(FS_OPCODE_TXD, dst); 646 break; 647 case ir_txf: 648 assert(!"GLSL 1.30 features unsupported"); 649 break; 650 } 651 inst->base_mrf = base_mrf; 652 inst->mlen = mlen; 653 inst->header_present = true; 654 655 if (simd16) { 656 for (int i = 0; i < 4; i++) { 657 emit(BRW_OPCODE_MOV, orig_dst, dst); 658 orig_dst.reg_offset++; 659 dst.reg_offset += 2; 660 } 661 } 662 663 return inst; 664} 665 666/* gen5's sampler has slots for u, v, r, array index, then optional 667 * parameters like shadow comparitor or LOD bias. If optional 668 * parameters aren't present, those base slots are optional and don't 669 * need to be included in the message. 670 * 671 * We don't fill in the unnecessary slots regardless, which may look 672 * surprising in the disassembly. 673 */ 674fs_inst * 675fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate, 676 int sampler) 677{ 678 int mlen = 0; 679 int base_mrf = 2; 680 int reg_width = c->dispatch_width / 8; 681 bool header_present = false; 682 683 if (ir->offset) { 684 /* The offsets set up by the ir_texture visitor are in the 685 * m1 header, so we can't go headerless. 686 */ 687 header_present = true; 688 mlen++; 689 base_mrf--; 690 } 691 692 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 693 fs_inst *inst = emit(BRW_OPCODE_MOV, 694 fs_reg(MRF, base_mrf + mlen + i * reg_width), 695 coordinate); 696 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 697 inst->saturate = true; 698 coordinate.reg_offset++; 699 } 700 mlen += ir->coordinate->type->vector_elements * reg_width; 701 702 if (ir->shadow_comparitor) { 703 mlen = MAX2(mlen, header_present + 4 * reg_width); 704 705 this->result = reg_undef; 706 ir->shadow_comparitor->accept(this); 707 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 708 mlen += reg_width; 709 } 710 711 fs_inst *inst = NULL; 712 switch (ir->op) { 713 case ir_tex: 714 inst = emit(FS_OPCODE_TEX, dst); 715 break; 716 case ir_txb: 717 this->result = reg_undef; 718 ir->lod_info.bias->accept(this); 719 mlen = MAX2(mlen, header_present + 4 * reg_width); 720 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 721 mlen += reg_width; 722 723 inst = emit(FS_OPCODE_TXB, dst); 724 725 break; 726 case ir_txl: 727 this->result = reg_undef; 728 ir->lod_info.lod->accept(this); 729 mlen = MAX2(mlen, header_present + 4 * reg_width); 730 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 731 mlen += reg_width; 732 733 inst = emit(FS_OPCODE_TXL, dst); 734 break; 735 case ir_txd: 736 case ir_txf: 737 assert(!"GLSL 1.30 features unsupported"); 738 break; 739 } 740 inst->base_mrf = base_mrf; 741 inst->mlen = mlen; 742 inst->header_present = header_present; 743 744 if (mlen > 11) { 745 fail("Message length >11 disallowed by hardware\n"); 746 } 747 748 return inst; 749} 750 751fs_inst * 752fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate, 753 int sampler) 754{ 755 int mlen = 0; 756 int base_mrf = 2; 757 int reg_width = c->dispatch_width / 8; 758 bool header_present = false; 759 760 if (ir->offset) { 761 /* The offsets set up by the ir_texture visitor are in the 762 * m1 header, so we can't go headerless. 763 */ 764 header_present = true; 765 mlen++; 766 base_mrf--; 767 } 768 769 if (ir->shadow_comparitor) { 770 ir->shadow_comparitor->accept(this); 771 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 772 mlen += reg_width; 773 } 774 775 /* Set up the LOD info */ 776 switch (ir->op) { 777 case ir_tex: 778 break; 779 case ir_txb: 780 ir->lod_info.bias->accept(this); 781 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 782 mlen += reg_width; 783 break; 784 case ir_txl: 785 ir->lod_info.lod->accept(this); 786 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 787 mlen += reg_width; 788 break; 789 case ir_txd: 790 case ir_txf: 791 assert(!"GLSL 1.30 features unsupported"); 792 break; 793 } 794 795 /* Set up the coordinate */ 796 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 797 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 798 coordinate); 799 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 800 inst->saturate = true; 801 coordinate.reg_offset++; 802 mlen += reg_width; 803 } 804 805 /* Generate the SEND */ 806 fs_inst *inst = NULL; 807 switch (ir->op) { 808 case ir_tex: inst = emit(FS_OPCODE_TEX, dst); break; 809 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break; 810 case ir_txl: inst = emit(FS_OPCODE_TXL, dst); break; 811 case ir_txd: inst = emit(FS_OPCODE_TXD, dst); break; 812 case ir_txf: assert(!"TXF unsupported."); 813 } 814 inst->base_mrf = base_mrf; 815 inst->mlen = mlen; 816 inst->header_present = header_present; 817 818 if (mlen > 11) { 819 fail("Message length >11 disallowed by hardware\n"); 820 } 821 822 return inst; 823} 824 825void 826fs_visitor::visit(ir_texture *ir) 827{ 828 int sampler; 829 fs_inst *inst = NULL; 830 831 this->result = reg_undef; 832 ir->coordinate->accept(this); 833 fs_reg coordinate = this->result; 834 835 if (ir->offset != NULL) { 836 ir_constant *offset = ir->offset->as_constant(); 837 assert(offset != NULL); 838 839 signed char offsets[3]; 840 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) 841 offsets[i] = (signed char) offset->value.i[i]; 842 843 /* Combine all three offsets into a single unsigned dword: 844 * 845 * bits 11:8 - U Offset (X component) 846 * bits 7:4 - V Offset (Y component) 847 * bits 3:0 - R Offset (Z component) 848 */ 849 unsigned offset_bits = 0; 850 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) { 851 const unsigned shift = 4 * (2 - i); 852 offset_bits |= (offsets[i] << shift) & (0xF << shift); 853 } 854 855 /* Explicitly set up the message header by copying g0 to msg reg m1. */ 856 emit(BRW_OPCODE_MOV, fs_reg(MRF, 1, BRW_REGISTER_TYPE_UD), 857 fs_reg(GRF, 0, BRW_REGISTER_TYPE_UD)); 858 859 /* Then set the offset bits in DWord 2 of the message header. */ 860 emit(BRW_OPCODE_MOV, 861 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 1, 2), 862 BRW_REGISTER_TYPE_UD)), 863 fs_reg(brw_imm_uw(offset_bits))); 864 } 865 866 /* Should be lowered by do_lower_texture_projection */ 867 assert(!ir->projector); 868 869 sampler = _mesa_get_sampler_uniform_value(ir->sampler, 870 ctx->Shader.CurrentFragmentProgram, 871 &brw->fragment_program->Base); 872 sampler = c->fp->program.Base.SamplerUnits[sampler]; 873 874 /* The 965 requires the EU to do the normalization of GL rectangle 875 * texture coordinates. We use the program parameter state 876 * tracking to get the scaling factor. 877 */ 878 if (ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) { 879 struct gl_program_parameter_list *params = c->fp->program.Base.Parameters; 880 int tokens[STATE_LENGTH] = { 881 STATE_INTERNAL, 882 STATE_TEXRECT_SCALE, 883 sampler, 884 0, 885 0 886 }; 887 888 if (c->dispatch_width == 16) { 889 fail("rectangle scale uniform setup not supported on 16-wide\n"); 890 this->result = fs_reg(this, ir->type); 891 return; 892 } 893 894 c->prog_data.param_convert[c->prog_data.nr_params] = 895 PARAM_NO_CONVERT; 896 c->prog_data.param_convert[c->prog_data.nr_params + 1] = 897 PARAM_NO_CONVERT; 898 899 fs_reg scale_x = fs_reg(UNIFORM, c->prog_data.nr_params); 900 fs_reg scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1); 901 GLuint index = _mesa_add_state_reference(params, 902 (gl_state_index *)tokens); 903 904 this->param_index[c->prog_data.nr_params] = index; 905 this->param_offset[c->prog_data.nr_params] = 0; 906 c->prog_data.nr_params++; 907 this->param_index[c->prog_data.nr_params] = index; 908 this->param_offset[c->prog_data.nr_params] = 1; 909 c->prog_data.nr_params++; 910 911 fs_reg dst = fs_reg(this, ir->coordinate->type); 912 fs_reg src = coordinate; 913 coordinate = dst; 914 915 emit(BRW_OPCODE_MUL, dst, src, scale_x); 916 dst.reg_offset++; 917 src.reg_offset++; 918 emit(BRW_OPCODE_MUL, dst, src, scale_y); 919 } 920 921 /* Writemasking doesn't eliminate channels on SIMD8 texture 922 * samples, so don't worry about them. 923 */ 924 fs_reg dst = fs_reg(this, glsl_type::vec4_type); 925 926 if (intel->gen >= 7) { 927 inst = emit_texture_gen7(ir, dst, coordinate, sampler); 928 } else if (intel->gen >= 5) { 929 inst = emit_texture_gen5(ir, dst, coordinate, sampler); 930 } else { 931 inst = emit_texture_gen4(ir, dst, coordinate, sampler); 932 } 933 934 /* If there's an offset, we already set up m1. To avoid the implied move, 935 * use the null register. Otherwise, we want an implied move from g0. 936 */ 937 if (ir->offset != NULL || !inst->header_present) 938 inst->src[0] = reg_undef; 939 else 940 inst->src[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW)); 941 942 inst->sampler = sampler; 943 944 this->result = dst; 945 946 if (ir->shadow_comparitor) 947 inst->shadow_compare = true; 948 949 if (ir->type == glsl_type::float_type) { 950 /* Ignore DEPTH_TEXTURE_MODE swizzling. */ 951 assert(ir->sampler->type->sampler_shadow); 952 } else if (c->key.tex_swizzles[inst->sampler] != SWIZZLE_NOOP) { 953 fs_reg swizzle_dst = fs_reg(this, glsl_type::vec4_type); 954 955 for (int i = 0; i < 4; i++) { 956 int swiz = GET_SWZ(c->key.tex_swizzles[inst->sampler], i); 957 fs_reg l = swizzle_dst; 958 l.reg_offset += i; 959 960 if (swiz == SWIZZLE_ZERO) { 961 emit(BRW_OPCODE_MOV, l, fs_reg(0.0f)); 962 } else if (swiz == SWIZZLE_ONE) { 963 emit(BRW_OPCODE_MOV, l, fs_reg(1.0f)); 964 } else { 965 fs_reg r = dst; 966 r.reg_offset += GET_SWZ(c->key.tex_swizzles[inst->sampler], i); 967 emit(BRW_OPCODE_MOV, l, r); 968 } 969 } 970 this->result = swizzle_dst; 971 } 972} 973 974void 975fs_visitor::visit(ir_swizzle *ir) 976{ 977 this->result = reg_undef; 978 ir->val->accept(this); 979 fs_reg val = this->result; 980 981 if (ir->type->vector_elements == 1) { 982 this->result.reg_offset += ir->mask.x; 983 return; 984 } 985 986 fs_reg result = fs_reg(this, ir->type); 987 this->result = result; 988 989 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 990 fs_reg channel = val; 991 int swiz = 0; 992 993 switch (i) { 994 case 0: 995 swiz = ir->mask.x; 996 break; 997 case 1: 998 swiz = ir->mask.y; 999 break; 1000 case 2: 1001 swiz = ir->mask.z; 1002 break; 1003 case 3: 1004 swiz = ir->mask.w; 1005 break; 1006 } 1007 1008 channel.reg_offset += swiz; 1009 emit(BRW_OPCODE_MOV, result, channel); 1010 result.reg_offset++; 1011 } 1012} 1013 1014void 1015fs_visitor::visit(ir_discard *ir) 1016{ 1017 assert(ir->condition == NULL); /* FINISHME */ 1018 1019 emit(FS_OPCODE_DISCARD); 1020 kill_emitted = true; 1021} 1022 1023void 1024fs_visitor::visit(ir_constant *ir) 1025{ 1026 /* Set this->result to reg at the bottom of the function because some code 1027 * paths will cause this visitor to be applied to other fields. This will 1028 * cause the value stored in this->result to be modified. 1029 * 1030 * Make reg constant so that it doesn't get accidentally modified along the 1031 * way. Yes, I actually had this problem. :( 1032 */ 1033 const fs_reg reg(this, ir->type); 1034 fs_reg dst_reg = reg; 1035 1036 if (ir->type->is_array()) { 1037 const unsigned size = type_size(ir->type->fields.array); 1038 1039 for (unsigned i = 0; i < ir->type->length; i++) { 1040 this->result = reg_undef; 1041 ir->array_elements[i]->accept(this); 1042 fs_reg src_reg = this->result; 1043 1044 dst_reg.type = src_reg.type; 1045 for (unsigned j = 0; j < size; j++) { 1046 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1047 src_reg.reg_offset++; 1048 dst_reg.reg_offset++; 1049 } 1050 } 1051 } else if (ir->type->is_record()) { 1052 foreach_list(node, &ir->components) { 1053 ir_instruction *const field = (ir_instruction *) node; 1054 const unsigned size = type_size(field->type); 1055 1056 this->result = reg_undef; 1057 field->accept(this); 1058 fs_reg src_reg = this->result; 1059 1060 dst_reg.type = src_reg.type; 1061 for (unsigned j = 0; j < size; j++) { 1062 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1063 src_reg.reg_offset++; 1064 dst_reg.reg_offset++; 1065 } 1066 } 1067 } else { 1068 const unsigned size = type_size(ir->type); 1069 1070 for (unsigned i = 0; i < size; i++) { 1071 switch (ir->type->base_type) { 1072 case GLSL_TYPE_FLOAT: 1073 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i])); 1074 break; 1075 case GLSL_TYPE_UINT: 1076 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i])); 1077 break; 1078 case GLSL_TYPE_INT: 1079 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.i[i])); 1080 break; 1081 case GLSL_TYPE_BOOL: 1082 emit(BRW_OPCODE_MOV, dst_reg, fs_reg((int)ir->value.b[i])); 1083 break; 1084 default: 1085 assert(!"Non-float/uint/int/bool constant"); 1086 } 1087 dst_reg.reg_offset++; 1088 } 1089 } 1090 1091 this->result = reg; 1092} 1093 1094void 1095fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir) 1096{ 1097 ir_expression *expr = ir->as_expression(); 1098 1099 if (expr) { 1100 fs_reg op[2]; 1101 fs_inst *inst; 1102 1103 assert(expr->get_num_operands() <= 2); 1104 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1105 assert(expr->operands[i]->type->is_scalar()); 1106 1107 this->result = reg_undef; 1108 expr->operands[i]->accept(this); 1109 op[i] = this->result; 1110 } 1111 1112 switch (expr->operation) { 1113 case ir_unop_logic_not: 1114 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1)); 1115 inst->conditional_mod = BRW_CONDITIONAL_Z; 1116 break; 1117 1118 case ir_binop_logic_xor: 1119 inst = emit(BRW_OPCODE_XOR, reg_null_d, op[0], op[1]); 1120 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1121 break; 1122 1123 case ir_binop_logic_or: 1124 inst = emit(BRW_OPCODE_OR, reg_null_d, op[0], op[1]); 1125 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1126 break; 1127 1128 case ir_binop_logic_and: 1129 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], op[1]); 1130 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1131 break; 1132 1133 case ir_unop_f2b: 1134 if (intel->gen >= 6) { 1135 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0.0f)); 1136 } else { 1137 inst = emit(BRW_OPCODE_MOV, reg_null_f, op[0]); 1138 } 1139 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1140 break; 1141 1142 case ir_unop_i2b: 1143 if (intel->gen >= 6) { 1144 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0)); 1145 } else { 1146 inst = emit(BRW_OPCODE_MOV, reg_null_d, op[0]); 1147 } 1148 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1149 break; 1150 1151 case ir_binop_greater: 1152 case ir_binop_gequal: 1153 case ir_binop_less: 1154 case ir_binop_lequal: 1155 case ir_binop_equal: 1156 case ir_binop_all_equal: 1157 case ir_binop_nequal: 1158 case ir_binop_any_nequal: 1159 inst = emit(BRW_OPCODE_CMP, reg_null_cmp, op[0], op[1]); 1160 inst->conditional_mod = 1161 brw_conditional_for_comparison(expr->operation); 1162 break; 1163 1164 default: 1165 assert(!"not reached"); 1166 fail("bad cond code\n"); 1167 break; 1168 } 1169 return; 1170 } 1171 1172 this->result = reg_undef; 1173 ir->accept(this); 1174 1175 if (intel->gen >= 6) { 1176 fs_inst *inst = emit(BRW_OPCODE_AND, reg_null_d, this->result, fs_reg(1)); 1177 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1178 } else { 1179 fs_inst *inst = emit(BRW_OPCODE_MOV, reg_null_d, this->result); 1180 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1181 } 1182} 1183 1184/** 1185 * Emit a gen6 IF statement with the comparison folded into the IF 1186 * instruction. 1187 */ 1188void 1189fs_visitor::emit_if_gen6(ir_if *ir) 1190{ 1191 ir_expression *expr = ir->condition->as_expression(); 1192 1193 if (expr) { 1194 fs_reg op[2]; 1195 fs_inst *inst; 1196 fs_reg temp; 1197 1198 assert(expr->get_num_operands() <= 2); 1199 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1200 assert(expr->operands[i]->type->is_scalar()); 1201 1202 this->result = reg_undef; 1203 expr->operands[i]->accept(this); 1204 op[i] = this->result; 1205 } 1206 1207 switch (expr->operation) { 1208 case ir_unop_logic_not: 1209 inst = emit(BRW_OPCODE_IF, temp, op[0], fs_reg(0)); 1210 inst->conditional_mod = BRW_CONDITIONAL_Z; 1211 return; 1212 1213 case ir_binop_logic_xor: 1214 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1215 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1216 return; 1217 1218 case ir_binop_logic_or: 1219 temp = fs_reg(this, glsl_type::bool_type); 1220 emit(BRW_OPCODE_OR, temp, op[0], op[1]); 1221 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1222 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1223 return; 1224 1225 case ir_binop_logic_and: 1226 temp = fs_reg(this, glsl_type::bool_type); 1227 emit(BRW_OPCODE_AND, temp, op[0], op[1]); 1228 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1229 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1230 return; 1231 1232 case ir_unop_f2b: 1233 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0)); 1234 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1235 return; 1236 1237 case ir_unop_i2b: 1238 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1239 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1240 return; 1241 1242 case ir_binop_greater: 1243 case ir_binop_gequal: 1244 case ir_binop_less: 1245 case ir_binop_lequal: 1246 case ir_binop_equal: 1247 case ir_binop_all_equal: 1248 case ir_binop_nequal: 1249 case ir_binop_any_nequal: 1250 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1251 inst->conditional_mod = 1252 brw_conditional_for_comparison(expr->operation); 1253 return; 1254 default: 1255 assert(!"not reached"); 1256 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1257 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1258 fail("bad condition\n"); 1259 return; 1260 } 1261 return; 1262 } 1263 1264 this->result = reg_undef; 1265 ir->condition->accept(this); 1266 1267 fs_inst *inst = emit(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0)); 1268 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1269} 1270 1271void 1272fs_visitor::visit(ir_if *ir) 1273{ 1274 fs_inst *inst; 1275 1276 if (intel->gen != 6 && c->dispatch_width == 16) { 1277 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1278 } 1279 1280 /* Don't point the annotation at the if statement, because then it plus 1281 * the then and else blocks get printed. 1282 */ 1283 this->base_ir = ir->condition; 1284 1285 if (intel->gen == 6) { 1286 emit_if_gen6(ir); 1287 } else { 1288 emit_bool_to_cond_code(ir->condition); 1289 1290 inst = emit(BRW_OPCODE_IF); 1291 inst->predicated = true; 1292 } 1293 1294 foreach_iter(exec_list_iterator, iter, ir->then_instructions) { 1295 ir_instruction *ir = (ir_instruction *)iter.get(); 1296 this->base_ir = ir; 1297 this->result = reg_undef; 1298 ir->accept(this); 1299 } 1300 1301 if (!ir->else_instructions.is_empty()) { 1302 emit(BRW_OPCODE_ELSE); 1303 1304 foreach_iter(exec_list_iterator, iter, ir->else_instructions) { 1305 ir_instruction *ir = (ir_instruction *)iter.get(); 1306 this->base_ir = ir; 1307 this->result = reg_undef; 1308 ir->accept(this); 1309 } 1310 } 1311 1312 emit(BRW_OPCODE_ENDIF); 1313} 1314 1315void 1316fs_visitor::visit(ir_loop *ir) 1317{ 1318 fs_reg counter = reg_undef; 1319 1320 if (c->dispatch_width == 16) { 1321 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1322 } 1323 1324 if (ir->counter) { 1325 this->base_ir = ir->counter; 1326 ir->counter->accept(this); 1327 counter = *(variable_storage(ir->counter)); 1328 1329 if (ir->from) { 1330 this->result = counter; 1331 1332 this->base_ir = ir->from; 1333 this->result = counter; 1334 ir->from->accept(this); 1335 1336 if (!this->result.equals(&counter)) 1337 emit(BRW_OPCODE_MOV, counter, this->result); 1338 } 1339 } 1340 1341 emit(BRW_OPCODE_DO); 1342 1343 if (ir->to) { 1344 this->base_ir = ir->to; 1345 this->result = reg_undef; 1346 ir->to->accept(this); 1347 1348 fs_inst *inst = emit(BRW_OPCODE_CMP, reg_null_cmp, counter, this->result); 1349 inst->conditional_mod = brw_conditional_for_comparison(ir->cmp); 1350 1351 inst = emit(BRW_OPCODE_BREAK); 1352 inst->predicated = true; 1353 } 1354 1355 foreach_iter(exec_list_iterator, iter, ir->body_instructions) { 1356 ir_instruction *ir = (ir_instruction *)iter.get(); 1357 1358 this->base_ir = ir; 1359 this->result = reg_undef; 1360 ir->accept(this); 1361 } 1362 1363 if (ir->increment) { 1364 this->base_ir = ir->increment; 1365 this->result = reg_undef; 1366 ir->increment->accept(this); 1367 emit(BRW_OPCODE_ADD, counter, counter, this->result); 1368 } 1369 1370 emit(BRW_OPCODE_WHILE); 1371} 1372 1373void 1374fs_visitor::visit(ir_loop_jump *ir) 1375{ 1376 switch (ir->mode) { 1377 case ir_loop_jump::jump_break: 1378 emit(BRW_OPCODE_BREAK); 1379 break; 1380 case ir_loop_jump::jump_continue: 1381 emit(BRW_OPCODE_CONTINUE); 1382 break; 1383 } 1384} 1385 1386void 1387fs_visitor::visit(ir_call *ir) 1388{ 1389 assert(!"FINISHME"); 1390} 1391 1392void 1393fs_visitor::visit(ir_return *ir) 1394{ 1395 assert(!"FINISHME"); 1396} 1397 1398void 1399fs_visitor::visit(ir_function *ir) 1400{ 1401 /* Ignore function bodies other than main() -- we shouldn't see calls to 1402 * them since they should all be inlined before we get to ir_to_mesa. 1403 */ 1404 if (strcmp(ir->name, "main") == 0) { 1405 const ir_function_signature *sig; 1406 exec_list empty; 1407 1408 sig = ir->matching_signature(&empty); 1409 1410 assert(sig); 1411 1412 foreach_iter(exec_list_iterator, iter, sig->body) { 1413 ir_instruction *ir = (ir_instruction *)iter.get(); 1414 this->base_ir = ir; 1415 this->result = reg_undef; 1416 ir->accept(this); 1417 } 1418 } 1419} 1420 1421void 1422fs_visitor::visit(ir_function_signature *ir) 1423{ 1424 assert(!"not reached"); 1425 (void)ir; 1426} 1427 1428fs_inst * 1429fs_visitor::emit(fs_inst inst) 1430{ 1431 fs_inst *list_inst = new(mem_ctx) fs_inst; 1432 *list_inst = inst; 1433 1434 if (force_uncompressed_stack > 0) 1435 list_inst->force_uncompressed = true; 1436 else if (force_sechalf_stack > 0) 1437 list_inst->force_sechalf = true; 1438 1439 list_inst->annotation = this->current_annotation; 1440 list_inst->ir = this->base_ir; 1441 1442 this->instructions.push_tail(list_inst); 1443 1444 return list_inst; 1445} 1446 1447/** Emits a dummy fragment shader consisting of magenta for bringup purposes. */ 1448void 1449fs_visitor::emit_dummy_fs() 1450{ 1451 /* Everyone's favorite color. */ 1452 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2), fs_reg(1.0f)); 1453 emit(BRW_OPCODE_MOV, fs_reg(MRF, 3), fs_reg(0.0f)); 1454 emit(BRW_OPCODE_MOV, fs_reg(MRF, 4), fs_reg(1.0f)); 1455 emit(BRW_OPCODE_MOV, fs_reg(MRF, 5), fs_reg(0.0f)); 1456 1457 fs_inst *write; 1458 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0)); 1459 write->base_mrf = 0; 1460} 1461 1462/* The register location here is relative to the start of the URB 1463 * data. It will get adjusted to be a real location before 1464 * generate_code() time. 1465 */ 1466struct brw_reg 1467fs_visitor::interp_reg(int location, int channel) 1468{ 1469 int regnr = urb_setup[location] * 2 + channel / 2; 1470 int stride = (channel & 1) * 4; 1471 1472 assert(urb_setup[location] != -1); 1473 1474 return brw_vec1_grf(regnr, stride); 1475} 1476 1477/** Emits the interpolation for the varying inputs. */ 1478void 1479fs_visitor::emit_interpolation_setup_gen4() 1480{ 1481 this->current_annotation = "compute pixel centers"; 1482 this->pixel_x = fs_reg(this, glsl_type::uint_type); 1483 this->pixel_y = fs_reg(this, glsl_type::uint_type); 1484 this->pixel_x.type = BRW_REGISTER_TYPE_UW; 1485 this->pixel_y.type = BRW_REGISTER_TYPE_UW; 1486 1487 emit(FS_OPCODE_PIXEL_X, this->pixel_x); 1488 emit(FS_OPCODE_PIXEL_Y, this->pixel_y); 1489 1490 this->current_annotation = "compute pixel deltas from v0"; 1491 if (brw->has_pln) { 1492 this->delta_x = fs_reg(this, glsl_type::vec2_type); 1493 this->delta_y = this->delta_x; 1494 this->delta_y.reg_offset++; 1495 } else { 1496 this->delta_x = fs_reg(this, glsl_type::float_type); 1497 this->delta_y = fs_reg(this, glsl_type::float_type); 1498 } 1499 emit(BRW_OPCODE_ADD, this->delta_x, 1500 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))); 1501 emit(BRW_OPCODE_ADD, this->delta_y, 1502 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))); 1503 1504 this->current_annotation = "compute pos.w and 1/pos.w"; 1505 /* Compute wpos.w. It's always in our setup, since it's needed to 1506 * interpolate the other attributes. 1507 */ 1508 this->wpos_w = fs_reg(this, glsl_type::float_type); 1509 emit(FS_OPCODE_LINTERP, wpos_w, this->delta_x, this->delta_y, 1510 interp_reg(FRAG_ATTRIB_WPOS, 3)); 1511 /* Compute the pixel 1/W value from wpos.w. */ 1512 this->pixel_w = fs_reg(this, glsl_type::float_type); 1513 emit_math(FS_OPCODE_RCP, this->pixel_w, wpos_w); 1514 this->current_annotation = NULL; 1515} 1516 1517/** Emits the interpolation for the varying inputs. */ 1518void 1519fs_visitor::emit_interpolation_setup_gen6() 1520{ 1521 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); 1522 1523 /* If the pixel centers end up used, the setup is the same as for gen4. */ 1524 this->current_annotation = "compute pixel centers"; 1525 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type); 1526 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type); 1527 int_pixel_x.type = BRW_REGISTER_TYPE_UW; 1528 int_pixel_y.type = BRW_REGISTER_TYPE_UW; 1529 emit(BRW_OPCODE_ADD, 1530 int_pixel_x, 1531 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), 1532 fs_reg(brw_imm_v(0x10101010))); 1533 emit(BRW_OPCODE_ADD, 1534 int_pixel_y, 1535 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), 1536 fs_reg(brw_imm_v(0x11001100))); 1537 1538 /* As of gen6, we can no longer mix float and int sources. We have 1539 * to turn the integer pixel centers into floats for their actual 1540 * use. 1541 */ 1542 this->pixel_x = fs_reg(this, glsl_type::float_type); 1543 this->pixel_y = fs_reg(this, glsl_type::float_type); 1544 emit(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x); 1545 emit(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y); 1546 1547 this->current_annotation = "compute pos.w"; 1548 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0)); 1549 this->wpos_w = fs_reg(this, glsl_type::float_type); 1550 emit_math(FS_OPCODE_RCP, this->wpos_w, this->pixel_w); 1551 1552 this->delta_x = fs_reg(brw_vec8_grf(2, 0)); 1553 this->delta_y = fs_reg(brw_vec8_grf(3, 0)); 1554 1555 this->current_annotation = NULL; 1556} 1557 1558void 1559fs_visitor::emit_color_write(int index, int first_color_mrf, fs_reg color) 1560{ 1561 int reg_width = c->dispatch_width / 8; 1562 1563 if (c->dispatch_width == 8 || intel->gen == 6) { 1564 /* SIMD8 write looks like: 1565 * m + 0: r0 1566 * m + 1: r1 1567 * m + 2: g0 1568 * m + 3: g1 1569 * 1570 * gen6 SIMD16 DP write looks like: 1571 * m + 0: r0 1572 * m + 1: r1 1573 * m + 2: g0 1574 * m + 3: g1 1575 * m + 4: b0 1576 * m + 5: b1 1577 * m + 6: a0 1578 * m + 7: a1 1579 */ 1580 emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index * reg_width), 1581 color); 1582 } else { 1583 /* pre-gen6 SIMD16 single source DP write looks like: 1584 * m + 0: r0 1585 * m + 1: g0 1586 * m + 2: b0 1587 * m + 3: a0 1588 * m + 4: r1 1589 * m + 5: g1 1590 * m + 6: b1 1591 * m + 7: a1 1592 */ 1593 if (brw->has_compr4) { 1594 /* By setting the high bit of the MRF register number, we 1595 * indicate that we want COMPR4 mode - instead of doing the 1596 * usual destination + 1 for the second half we get 1597 * destination + 4. 1598 */ 1599 emit(BRW_OPCODE_MOV, 1600 fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index), color); 1601 } else { 1602 push_force_uncompressed(); 1603 emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index), color); 1604 pop_force_uncompressed(); 1605 1606 push_force_sechalf(); 1607 color.sechalf = true; 1608 emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index + 4), color); 1609 pop_force_sechalf(); 1610 color.sechalf = false; 1611 } 1612 } 1613} 1614 1615void 1616fs_visitor::emit_fb_writes() 1617{ 1618 this->current_annotation = "FB write header"; 1619 GLboolean header_present = GL_TRUE; 1620 int nr = 0; 1621 int reg_width = c->dispatch_width / 8; 1622 1623 if (intel->gen >= 6 && 1624 !this->kill_emitted && 1625 c->key.nr_color_regions == 1) { 1626 header_present = false; 1627 } 1628 1629 if (header_present) { 1630 /* m0, m1 header */ 1631 nr += 2; 1632 } 1633 1634 if (c->aa_dest_stencil_reg) { 1635 push_force_uncompressed(); 1636 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++), 1637 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))); 1638 pop_force_uncompressed(); 1639 } 1640 1641 /* Reserve space for color. It'll be filled in per MRT below. */ 1642 int color_mrf = nr; 1643 nr += 4 * reg_width; 1644 1645 if (c->source_depth_to_render_target) { 1646 if (intel->gen == 6 && c->dispatch_width == 16) { 1647 /* For outputting oDepth on gen6, SIMD8 writes have to be 1648 * used. This would require 8-wide moves of each half to 1649 * message regs, kind of like pre-gen5 SIMD16 FB writes. 1650 * Just bail on doing so for now. 1651 */ 1652 fail("Missing support for simd16 depth writes on gen6\n"); 1653 } 1654 1655 if (c->computes_depth) { 1656 /* Hand over gl_FragDepth. */ 1657 assert(this->frag_depth); 1658 fs_reg depth = *(variable_storage(this->frag_depth)); 1659 1660 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), depth); 1661 } else { 1662 /* Pass through the payload depth. */ 1663 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1664 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))); 1665 } 1666 nr += reg_width; 1667 } 1668 1669 if (c->dest_depth_reg) { 1670 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1671 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))); 1672 nr += reg_width; 1673 } 1674 1675 fs_reg color = reg_undef; 1676 if (this->frag_color) 1677 color = *(variable_storage(this->frag_color)); 1678 else if (this->frag_data) { 1679 color = *(variable_storage(this->frag_data)); 1680 color.type = BRW_REGISTER_TYPE_F; 1681 } 1682 1683 for (int target = 0; target < c->key.nr_color_regions; target++) { 1684 this->current_annotation = ralloc_asprintf(this->mem_ctx, 1685 "FB write target %d", 1686 target); 1687 if (this->frag_color || this->frag_data) { 1688 for (int i = 0; i < 4; i++) { 1689 emit_color_write(i, color_mrf, color); 1690 color.reg_offset++; 1691 } 1692 } 1693 1694 if (this->frag_color) 1695 color.reg_offset -= 4; 1696 1697 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1698 inst->target = target; 1699 inst->base_mrf = 0; 1700 inst->mlen = nr; 1701 if (target == c->key.nr_color_regions - 1) 1702 inst->eot = true; 1703 inst->header_present = header_present; 1704 } 1705 1706 if (c->key.nr_color_regions == 0) { 1707 if (c->key.alpha_test && (this->frag_color || this->frag_data)) { 1708 /* If the alpha test is enabled but there's no color buffer, 1709 * we still need to send alpha out the pipeline to our null 1710 * renderbuffer. 1711 */ 1712 color.reg_offset += 3; 1713 emit_color_write(3, color_mrf, color); 1714 } 1715 1716 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1717 inst->base_mrf = 0; 1718 inst->mlen = nr; 1719 inst->eot = true; 1720 inst->header_present = header_present; 1721 } 1722 1723 this->current_annotation = NULL; 1724} 1725