brw_fs_visitor.cpp revision dc42910e98dc00760255cc4579da458de09175b9
1/* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24/** @file brw_fs_visitor.cpp 25 * 26 * This file supports generating the FS LIR from the GLSL IR. The LIR 27 * makes it easier to do backend-specific optimizations than doing so 28 * in the GLSL IR or in the native code. 29 */ 30extern "C" { 31 32#include <sys/types.h> 33 34#include "main/macros.h" 35#include "main/shaderobj.h" 36#include "main/uniforms.h" 37#include "program/prog_parameter.h" 38#include "program/prog_print.h" 39#include "program/prog_optimize.h" 40#include "program/register_allocate.h" 41#include "program/sampler.h" 42#include "program/hash_table.h" 43#include "brw_context.h" 44#include "brw_eu.h" 45#include "brw_wm.h" 46} 47#include "brw_shader.h" 48#include "brw_fs.h" 49#include "glsl/glsl_types.h" 50#include "glsl/ir_optimization.h" 51#include "glsl/ir_print_visitor.h" 52 53void 54fs_visitor::visit(ir_variable *ir) 55{ 56 fs_reg *reg = NULL; 57 58 if (variable_storage(ir)) 59 return; 60 61 if (ir->mode == ir_var_in) { 62 if (!strcmp(ir->name, "gl_FragCoord")) { 63 reg = emit_fragcoord_interpolation(ir); 64 } else if (!strcmp(ir->name, "gl_FrontFacing")) { 65 reg = emit_frontfacing_interpolation(ir); 66 } else { 67 reg = emit_general_interpolation(ir); 68 } 69 assert(reg); 70 hash_table_insert(this->variable_ht, reg, ir); 71 return; 72 } else if (ir->mode == ir_var_out) { 73 reg = new(this->mem_ctx) fs_reg(this, ir->type); 74 75 if (ir->location == FRAG_RESULT_COLOR) { 76 /* Writing gl_FragColor outputs to all color regions. */ 77 for (int i = 0; i < MAX2(c->key.nr_color_regions, 1); i++) { 78 this->outputs[i] = *reg; 79 } 80 } else if (ir->location == FRAG_RESULT_DEPTH) { 81 this->frag_depth = ir; 82 } else { 83 /* gl_FragData or a user-defined FS output */ 84 assert(ir->location >= FRAG_RESULT_DATA0 && 85 ir->location < FRAG_RESULT_DATA0 + BRW_MAX_DRAW_BUFFERS); 86 87 /* General color output. */ 88 for (unsigned int i = 0; i < MAX2(1, ir->type->length); i++) { 89 int output = ir->location - FRAG_RESULT_DATA0 + i; 90 this->outputs[output] = *reg; 91 this->outputs[output].reg_offset += 4 * i; 92 } 93 } 94 } else if (ir->mode == ir_var_uniform) { 95 int param_index = c->prog_data.nr_params; 96 97 if (c->dispatch_width == 16) { 98 if (!variable_storage(ir)) { 99 fail("Failed to find uniform '%s' in 16-wide\n", ir->name); 100 } 101 return; 102 } 103 104 if (!strncmp(ir->name, "gl_", 3)) { 105 setup_builtin_uniform_values(ir); 106 } else { 107 setup_uniform_values(ir->location, ir->type); 108 } 109 110 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index); 111 reg->type = brw_type_for_base_type(ir->type); 112 } 113 114 if (!reg) 115 reg = new(this->mem_ctx) fs_reg(this, ir->type); 116 117 hash_table_insert(this->variable_ht, reg, ir); 118} 119 120void 121fs_visitor::visit(ir_dereference_variable *ir) 122{ 123 fs_reg *reg = variable_storage(ir->var); 124 this->result = *reg; 125} 126 127void 128fs_visitor::visit(ir_dereference_record *ir) 129{ 130 const glsl_type *struct_type = ir->record->type; 131 132 ir->record->accept(this); 133 134 unsigned int offset = 0; 135 for (unsigned int i = 0; i < struct_type->length; i++) { 136 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0) 137 break; 138 offset += type_size(struct_type->fields.structure[i].type); 139 } 140 this->result.reg_offset += offset; 141 this->result.type = brw_type_for_base_type(ir->type); 142} 143 144void 145fs_visitor::visit(ir_dereference_array *ir) 146{ 147 ir_constant *index; 148 int element_size; 149 150 ir->array->accept(this); 151 index = ir->array_index->as_constant(); 152 153 element_size = type_size(ir->type); 154 this->result.type = brw_type_for_base_type(ir->type); 155 156 if (index) { 157 assert(this->result.file == UNIFORM || this->result.file == GRF); 158 this->result.reg_offset += index->value.i[0] * element_size; 159 } else { 160 assert(!"FINISHME: non-constant array element"); 161 } 162} 163 164/* Instruction selection: Produce a MOV.sat instead of 165 * MIN(MAX(val, 0), 1) when possible. 166 */ 167bool 168fs_visitor::try_emit_saturate(ir_expression *ir) 169{ 170 ir_rvalue *sat_val = ir->as_rvalue_to_saturate(); 171 172 if (!sat_val) 173 return false; 174 175 fs_inst *pre_inst = (fs_inst *) this->instructions.get_tail(); 176 177 sat_val->accept(this); 178 fs_reg src = this->result; 179 180 fs_inst *last_inst = (fs_inst *) this->instructions.get_tail(); 181 182 /* If the last instruction from our accept() didn't generate our 183 * src, generate a saturated MOV 184 */ 185 fs_inst *modify = get_instruction_generating_reg(pre_inst, last_inst, src); 186 if (!modify || modify->regs_written() != 1) { 187 fs_inst *inst = emit(BRW_OPCODE_MOV, this->result, src); 188 inst->saturate = true; 189 } else { 190 modify->saturate = true; 191 this->result = src; 192 } 193 194 195 return true; 196} 197 198bool 199fs_visitor::try_emit_mad(ir_expression *ir, int mul_arg) 200{ 201 /* 3-src instructions were introduced in gen6. */ 202 if (intel->gen < 6) 203 return false; 204 205 /* MAD can only handle floating-point data. */ 206 if (ir->type != glsl_type::float_type) 207 return false; 208 209 ir_rvalue *nonmul = ir->operands[1 - mul_arg]; 210 ir_expression *mul = ir->operands[mul_arg]->as_expression(); 211 212 if (!mul || mul->operation != ir_binop_mul) 213 return false; 214 215 if (nonmul->as_constant() || 216 mul->operands[0]->as_constant() || 217 mul->operands[1]->as_constant()) 218 return false; 219 220 nonmul->accept(this); 221 fs_reg src0 = this->result; 222 223 mul->operands[0]->accept(this); 224 fs_reg src1 = this->result; 225 226 mul->operands[1]->accept(this); 227 fs_reg src2 = this->result; 228 229 this->result = fs_reg(this, ir->type); 230 emit(BRW_OPCODE_MAD, this->result, src0, src1, src2); 231 232 return true; 233} 234 235void 236fs_visitor::visit(ir_expression *ir) 237{ 238 unsigned int operand; 239 fs_reg op[2], temp; 240 fs_inst *inst; 241 242 assert(ir->get_num_operands() <= 2); 243 244 if (try_emit_saturate(ir)) 245 return; 246 if (ir->operation == ir_binop_add) { 247 if (try_emit_mad(ir, 0) || try_emit_mad(ir, 1)) 248 return; 249 } 250 251 for (operand = 0; operand < ir->get_num_operands(); operand++) { 252 ir->operands[operand]->accept(this); 253 if (this->result.file == BAD_FILE) { 254 ir_print_visitor v; 255 fail("Failed to get tree for expression operand:\n"); 256 ir->operands[operand]->accept(&v); 257 } 258 op[operand] = this->result; 259 260 /* Matrix expression operands should have been broken down to vector 261 * operations already. 262 */ 263 assert(!ir->operands[operand]->type->is_matrix()); 264 /* And then those vector operands should have been broken down to scalar. 265 */ 266 assert(!ir->operands[operand]->type->is_vector()); 267 } 268 269 /* Storage for our result. If our result goes into an assignment, it will 270 * just get copy-propagated out, so no worries. 271 */ 272 this->result = fs_reg(this, ir->type); 273 274 switch (ir->operation) { 275 case ir_unop_logic_not: 276 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is 277 * ones complement of the whole register, not just bit 0. 278 */ 279 emit(BRW_OPCODE_XOR, this->result, op[0], fs_reg(1)); 280 break; 281 case ir_unop_neg: 282 op[0].negate = !op[0].negate; 283 this->result = op[0]; 284 break; 285 case ir_unop_abs: 286 op[0].abs = true; 287 op[0].negate = false; 288 this->result = op[0]; 289 break; 290 case ir_unop_sign: 291 temp = fs_reg(this, ir->type); 292 293 emit(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)); 294 295 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 296 inst->conditional_mod = BRW_CONDITIONAL_G; 297 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)); 298 inst->predicated = true; 299 300 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 301 inst->conditional_mod = BRW_CONDITIONAL_L; 302 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)); 303 inst->predicated = true; 304 305 break; 306 case ir_unop_rcp: 307 emit_math(SHADER_OPCODE_RCP, this->result, op[0]); 308 break; 309 310 case ir_unop_exp2: 311 emit_math(SHADER_OPCODE_EXP2, this->result, op[0]); 312 break; 313 case ir_unop_log2: 314 emit_math(SHADER_OPCODE_LOG2, this->result, op[0]); 315 break; 316 case ir_unop_exp: 317 case ir_unop_log: 318 assert(!"not reached: should be handled by ir_explog_to_explog2"); 319 break; 320 case ir_unop_sin: 321 case ir_unop_sin_reduced: 322 emit_math(SHADER_OPCODE_SIN, this->result, op[0]); 323 break; 324 case ir_unop_cos: 325 case ir_unop_cos_reduced: 326 emit_math(SHADER_OPCODE_COS, this->result, op[0]); 327 break; 328 329 case ir_unop_dFdx: 330 emit(FS_OPCODE_DDX, this->result, op[0]); 331 break; 332 case ir_unop_dFdy: 333 emit(FS_OPCODE_DDY, this->result, op[0]); 334 break; 335 336 case ir_binop_add: 337 emit(BRW_OPCODE_ADD, this->result, op[0], op[1]); 338 break; 339 case ir_binop_sub: 340 assert(!"not reached: should be handled by ir_sub_to_add_neg"); 341 break; 342 343 case ir_binop_mul: 344 if (ir->type->is_integer()) { 345 /* For integer multiplication, the MUL uses the low 16 bits 346 * of one of the operands (src0 on gen6, src1 on gen7). The 347 * MACH accumulates in the contribution of the upper 16 bits 348 * of that operand. 349 * 350 * FINISHME: Emit just the MUL if we know an operand is small 351 * enough. 352 */ 353 if (intel->gen >= 7 && c->dispatch_width == 16) 354 fail("16-wide explicit accumulator operands unsupported\n"); 355 356 struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_D); 357 358 emit(BRW_OPCODE_MUL, acc, op[0], op[1]); 359 emit(BRW_OPCODE_MACH, reg_null_d, op[0], op[1]); 360 emit(BRW_OPCODE_MOV, this->result, fs_reg(acc)); 361 } else { 362 emit(BRW_OPCODE_MUL, this->result, op[0], op[1]); 363 } 364 break; 365 case ir_binop_div: 366 if (intel->gen >= 7 && c->dispatch_width == 16) 367 fail("16-wide INTDIV unsupported\n"); 368 369 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */ 370 assert(ir->type->is_integer()); 371 emit_math(SHADER_OPCODE_INT_QUOTIENT, this->result, op[0], op[1]); 372 break; 373 case ir_binop_mod: 374 if (intel->gen >= 7 && c->dispatch_width == 16) 375 fail("16-wide INTDIV unsupported\n"); 376 377 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */ 378 assert(ir->type->is_integer()); 379 emit_math(SHADER_OPCODE_INT_REMAINDER, this->result, op[0], op[1]); 380 break; 381 382 case ir_binop_less: 383 case ir_binop_greater: 384 case ir_binop_lequal: 385 case ir_binop_gequal: 386 case ir_binop_equal: 387 case ir_binop_all_equal: 388 case ir_binop_nequal: 389 case ir_binop_any_nequal: 390 temp = this->result; 391 /* original gen4 does implicit conversion before comparison. */ 392 if (intel->gen < 5) 393 temp.type = op[0].type; 394 395 resolve_ud_negate(&op[0]); 396 resolve_ud_negate(&op[1]); 397 398 resolve_bool_comparison(ir->operands[0], &op[0]); 399 resolve_bool_comparison(ir->operands[1], &op[1]); 400 401 inst = emit(BRW_OPCODE_CMP, temp, op[0], op[1]); 402 inst->conditional_mod = brw_conditional_for_comparison(ir->operation); 403 break; 404 405 case ir_binop_logic_xor: 406 emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 407 break; 408 409 case ir_binop_logic_or: 410 emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 411 break; 412 413 case ir_binop_logic_and: 414 emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 415 break; 416 417 case ir_binop_dot: 418 case ir_unop_any: 419 assert(!"not reached: should be handled by brw_fs_channel_expressions"); 420 break; 421 422 case ir_unop_noise: 423 assert(!"not reached: should be handled by lower_noise"); 424 break; 425 426 case ir_quadop_vector: 427 assert(!"not reached: should be handled by lower_quadop_vector"); 428 break; 429 430 case ir_unop_sqrt: 431 emit_math(SHADER_OPCODE_SQRT, this->result, op[0]); 432 break; 433 434 case ir_unop_rsq: 435 emit_math(SHADER_OPCODE_RSQ, this->result, op[0]); 436 break; 437 438 case ir_unop_i2u: 439 op[0].type = BRW_REGISTER_TYPE_UD; 440 this->result = op[0]; 441 break; 442 case ir_unop_u2i: 443 op[0].type = BRW_REGISTER_TYPE_D; 444 this->result = op[0]; 445 break; 446 case ir_unop_i2f: 447 case ir_unop_u2f: 448 case ir_unop_f2i: 449 emit(BRW_OPCODE_MOV, this->result, op[0]); 450 break; 451 452 case ir_unop_b2i: 453 inst = emit(BRW_OPCODE_AND, this->result, op[0], fs_reg(1)); 454 break; 455 case ir_unop_b2f: 456 temp = fs_reg(this, glsl_type::int_type); 457 emit(BRW_OPCODE_AND, temp, op[0], fs_reg(1)); 458 emit(BRW_OPCODE_MOV, this->result, temp); 459 break; 460 461 case ir_unop_f2b: 462 case ir_unop_i2b: 463 temp = this->result; 464 /* original gen4 does implicit conversion before comparison. */ 465 if (intel->gen < 5) 466 temp.type = op[0].type; 467 468 resolve_ud_negate(&op[0]); 469 470 inst = emit(BRW_OPCODE_CMP, temp, op[0], fs_reg(0.0f)); 471 inst->conditional_mod = BRW_CONDITIONAL_NZ; 472 break; 473 474 case ir_unop_trunc: 475 emit(BRW_OPCODE_RNDZ, this->result, op[0]); 476 break; 477 case ir_unop_ceil: 478 op[0].negate = !op[0].negate; 479 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 480 this->result.negate = true; 481 break; 482 case ir_unop_floor: 483 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 484 break; 485 case ir_unop_fract: 486 inst = emit(BRW_OPCODE_FRC, this->result, op[0]); 487 break; 488 case ir_unop_round_even: 489 emit(BRW_OPCODE_RNDE, this->result, op[0]); 490 break; 491 492 case ir_binop_min: 493 resolve_ud_negate(&op[0]); 494 resolve_ud_negate(&op[1]); 495 496 if (intel->gen >= 6) { 497 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 498 inst->conditional_mod = BRW_CONDITIONAL_L; 499 } else { 500 /* Unalias the destination */ 501 this->result = fs_reg(this, ir->type); 502 503 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 504 inst->conditional_mod = BRW_CONDITIONAL_L; 505 506 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 507 inst->predicated = true; 508 } 509 break; 510 case ir_binop_max: 511 resolve_ud_negate(&op[0]); 512 resolve_ud_negate(&op[1]); 513 514 if (intel->gen >= 6) { 515 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 516 inst->conditional_mod = BRW_CONDITIONAL_GE; 517 } else { 518 /* Unalias the destination */ 519 this->result = fs_reg(this, ir->type); 520 521 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 522 inst->conditional_mod = BRW_CONDITIONAL_G; 523 524 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 525 inst->predicated = true; 526 } 527 break; 528 529 case ir_binop_pow: 530 emit_math(SHADER_OPCODE_POW, this->result, op[0], op[1]); 531 break; 532 533 case ir_unop_bit_not: 534 inst = emit(BRW_OPCODE_NOT, this->result, op[0]); 535 break; 536 case ir_binop_bit_and: 537 inst = emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 538 break; 539 case ir_binop_bit_xor: 540 inst = emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 541 break; 542 case ir_binop_bit_or: 543 inst = emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 544 break; 545 546 case ir_binop_lshift: 547 inst = emit(BRW_OPCODE_SHL, this->result, op[0], op[1]); 548 break; 549 550 case ir_binop_rshift: 551 if (ir->type->base_type == GLSL_TYPE_INT) 552 inst = emit(BRW_OPCODE_ASR, this->result, op[0], op[1]); 553 else 554 inst = emit(BRW_OPCODE_SHR, this->result, op[0], op[1]); 555 break; 556 } 557} 558 559void 560fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r, 561 const glsl_type *type, bool predicated) 562{ 563 switch (type->base_type) { 564 case GLSL_TYPE_FLOAT: 565 case GLSL_TYPE_UINT: 566 case GLSL_TYPE_INT: 567 case GLSL_TYPE_BOOL: 568 for (unsigned int i = 0; i < type->components(); i++) { 569 l.type = brw_type_for_base_type(type); 570 r.type = brw_type_for_base_type(type); 571 572 if (predicated || !l.equals(&r)) { 573 fs_inst *inst = emit(BRW_OPCODE_MOV, l, r); 574 inst->predicated = predicated; 575 } 576 577 l.reg_offset++; 578 r.reg_offset++; 579 } 580 break; 581 case GLSL_TYPE_ARRAY: 582 for (unsigned int i = 0; i < type->length; i++) { 583 emit_assignment_writes(l, r, type->fields.array, predicated); 584 } 585 break; 586 587 case GLSL_TYPE_STRUCT: 588 for (unsigned int i = 0; i < type->length; i++) { 589 emit_assignment_writes(l, r, type->fields.structure[i].type, 590 predicated); 591 } 592 break; 593 594 case GLSL_TYPE_SAMPLER: 595 break; 596 597 default: 598 assert(!"not reached"); 599 break; 600 } 601} 602 603/* If the RHS processing resulted in an instruction generating a 604 * temporary value, and it would be easy to rewrite the instruction to 605 * generate its result right into the LHS instead, do so. This ends 606 * up reliably removing instructions where it can be tricky to do so 607 * later without real UD chain information. 608 */ 609bool 610fs_visitor::try_rewrite_rhs_to_dst(ir_assignment *ir, 611 fs_reg dst, 612 fs_reg src, 613 fs_inst *pre_rhs_inst, 614 fs_inst *last_rhs_inst) 615{ 616 /* Only attempt if we're doing a direct assignment. */ 617 if (ir->condition || 618 !(ir->lhs->type->is_scalar() || 619 (ir->lhs->type->is_vector() && 620 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1))) 621 return false; 622 623 /* Make sure the last instruction generated our source reg. */ 624 fs_inst *modify = get_instruction_generating_reg(pre_rhs_inst, 625 last_rhs_inst, 626 src); 627 if (!modify) 628 return false; 629 630 /* If last_rhs_inst wrote a different number of components than our LHS, 631 * we can't safely rewrite it. 632 */ 633 if (ir->lhs->type->vector_elements != modify->regs_written()) 634 return false; 635 636 /* Success! Rewrite the instruction. */ 637 modify->dst = dst; 638 639 return true; 640} 641 642void 643fs_visitor::visit(ir_assignment *ir) 644{ 645 fs_reg l, r; 646 fs_inst *inst; 647 648 /* FINISHME: arrays on the lhs */ 649 ir->lhs->accept(this); 650 l = this->result; 651 652 fs_inst *pre_rhs_inst = (fs_inst *) this->instructions.get_tail(); 653 654 ir->rhs->accept(this); 655 r = this->result; 656 657 fs_inst *last_rhs_inst = (fs_inst *) this->instructions.get_tail(); 658 659 assert(l.file != BAD_FILE); 660 assert(r.file != BAD_FILE); 661 662 if (try_rewrite_rhs_to_dst(ir, l, r, pre_rhs_inst, last_rhs_inst)) 663 return; 664 665 if (ir->condition) { 666 emit_bool_to_cond_code(ir->condition); 667 } 668 669 if (ir->lhs->type->is_scalar() || 670 ir->lhs->type->is_vector()) { 671 for (int i = 0; i < ir->lhs->type->vector_elements; i++) { 672 if (ir->write_mask & (1 << i)) { 673 inst = emit(BRW_OPCODE_MOV, l, r); 674 if (ir->condition) 675 inst->predicated = true; 676 r.reg_offset++; 677 } 678 l.reg_offset++; 679 } 680 } else { 681 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL); 682 } 683} 684 685fs_inst * 686fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate, 687 int sampler) 688{ 689 int mlen; 690 int base_mrf = 1; 691 bool simd16 = false; 692 fs_reg orig_dst; 693 694 /* g0 header. */ 695 mlen = 1; 696 697 if (ir->shadow_comparitor && ir->op != ir_txd) { 698 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 699 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); 700 coordinate.reg_offset++; 701 } 702 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 703 mlen += 3; 704 705 if (ir->op == ir_tex) { 706 /* There's no plain shadow compare message, so we use shadow 707 * compare with a bias of 0.0. 708 */ 709 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)); 710 mlen++; 711 } else if (ir->op == ir_txb) { 712 ir->lod_info.bias->accept(this); 713 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 714 mlen++; 715 } else { 716 assert(ir->op == ir_txl); 717 ir->lod_info.lod->accept(this); 718 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 719 mlen++; 720 } 721 722 ir->shadow_comparitor->accept(this); 723 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 724 mlen++; 725 } else if (ir->op == ir_tex) { 726 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 727 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); 728 coordinate.reg_offset++; 729 } 730 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 731 mlen += 3; 732 } else if (ir->op == ir_txd) { 733 ir->lod_info.grad.dPdx->accept(this); 734 fs_reg dPdx = this->result; 735 736 ir->lod_info.grad.dPdy->accept(this); 737 fs_reg dPdy = this->result; 738 739 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 740 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); 741 coordinate.reg_offset++; 742 } 743 /* the slots for u and v are always present, but r is optional */ 744 mlen += MAX2(ir->coordinate->type->vector_elements, 2); 745 746 /* P = u, v, r 747 * dPdx = dudx, dvdx, drdx 748 * dPdy = dudy, dvdy, drdy 749 * 750 * 1-arg: Does not exist. 751 * 752 * 2-arg: dudx dvdx dudy dvdy 753 * dPdx.x dPdx.y dPdy.x dPdy.y 754 * m4 m5 m6 m7 755 * 756 * 3-arg: dudx dvdx drdx dudy dvdy drdy 757 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z 758 * m5 m6 m7 m8 m9 m10 759 */ 760 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 761 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 762 dPdx.reg_offset++; 763 } 764 mlen += MAX2(ir->lod_info.grad.dPdx->type->vector_elements, 2); 765 766 for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) { 767 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 768 dPdy.reg_offset++; 769 } 770 mlen += MAX2(ir->lod_info.grad.dPdy->type->vector_elements, 2); 771 } else if (ir->op == ir_txs) { 772 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */ 773 simd16 = true; 774 ir->lod_info.lod->accept(this); 775 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 776 mlen += 2; 777 } else { 778 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod 779 * instructions. We'll need to do SIMD16 here. 780 */ 781 simd16 = true; 782 assert(ir->op == ir_txb || ir->op == ir_txl || ir->op == ir_txf); 783 784 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 785 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i * 2, coordinate.type), 786 coordinate); 787 coordinate.reg_offset++; 788 } 789 790 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to 791 * be necessary for TXF (ld), but seems wise to do for all messages. 792 */ 793 for (int i = ir->coordinate->type->vector_elements; i < 3; i++) { 794 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i * 2), fs_reg(0.0f)); 795 } 796 797 /* lod/bias appears after u/v/r. */ 798 mlen += 6; 799 800 if (ir->op == ir_txb) { 801 ir->lod_info.bias->accept(this); 802 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 803 mlen++; 804 } else { 805 ir->lod_info.lod->accept(this); 806 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, this->result.type), 807 this->result); 808 mlen++; 809 } 810 811 /* The unused upper half. */ 812 mlen++; 813 } 814 815 if (simd16) { 816 /* Now, since we're doing simd16, the return is 2 interleaved 817 * vec4s where the odd-indexed ones are junk. We'll need to move 818 * this weirdness around to the expected layout. 819 */ 820 orig_dst = dst; 821 const glsl_type *vec_type = 822 glsl_type::get_instance(ir->type->base_type, 4, 1); 823 dst = fs_reg(this, glsl_type::get_array_instance(vec_type, 2)); 824 dst.type = intel->is_g4x ? brw_type_for_base_type(ir->type) 825 : BRW_REGISTER_TYPE_F; 826 } 827 828 fs_inst *inst = NULL; 829 switch (ir->op) { 830 case ir_tex: 831 inst = emit(SHADER_OPCODE_TEX, dst); 832 break; 833 case ir_txb: 834 inst = emit(FS_OPCODE_TXB, dst); 835 break; 836 case ir_txl: 837 inst = emit(SHADER_OPCODE_TXL, dst); 838 break; 839 case ir_txd: 840 inst = emit(SHADER_OPCODE_TXD, dst); 841 break; 842 case ir_txs: 843 inst = emit(SHADER_OPCODE_TXS, dst); 844 break; 845 case ir_txf: 846 inst = emit(SHADER_OPCODE_TXF, dst); 847 break; 848 } 849 inst->base_mrf = base_mrf; 850 inst->mlen = mlen; 851 inst->header_present = true; 852 853 if (simd16) { 854 for (int i = 0; i < 4; i++) { 855 emit(BRW_OPCODE_MOV, orig_dst, dst); 856 orig_dst.reg_offset++; 857 dst.reg_offset += 2; 858 } 859 } 860 861 return inst; 862} 863 864/* gen5's sampler has slots for u, v, r, array index, then optional 865 * parameters like shadow comparitor or LOD bias. If optional 866 * parameters aren't present, those base slots are optional and don't 867 * need to be included in the message. 868 * 869 * We don't fill in the unnecessary slots regardless, which may look 870 * surprising in the disassembly. 871 */ 872fs_inst * 873fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate, 874 int sampler) 875{ 876 int mlen = 0; 877 int base_mrf = 2; 878 int reg_width = c->dispatch_width / 8; 879 bool header_present = false; 880 const int vector_elements = 881 ir->coordinate ? ir->coordinate->type->vector_elements : 0; 882 883 if (ir->offset) { 884 /* The offsets set up by the ir_texture visitor are in the 885 * m1 header, so we can't go headerless. 886 */ 887 header_present = true; 888 mlen++; 889 base_mrf--; 890 } 891 892 for (int i = 0; i < vector_elements; i++) { 893 emit(BRW_OPCODE_MOV, 894 fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type), 895 coordinate); 896 coordinate.reg_offset++; 897 } 898 mlen += vector_elements * reg_width; 899 900 if (ir->shadow_comparitor && ir->op != ir_txd) { 901 mlen = MAX2(mlen, header_present + 4 * reg_width); 902 903 ir->shadow_comparitor->accept(this); 904 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 905 mlen += reg_width; 906 } 907 908 fs_inst *inst = NULL; 909 switch (ir->op) { 910 case ir_tex: 911 inst = emit(SHADER_OPCODE_TEX, dst); 912 break; 913 case ir_txb: 914 ir->lod_info.bias->accept(this); 915 mlen = MAX2(mlen, header_present + 4 * reg_width); 916 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 917 mlen += reg_width; 918 919 inst = emit(FS_OPCODE_TXB, dst); 920 921 break; 922 case ir_txl: 923 ir->lod_info.lod->accept(this); 924 mlen = MAX2(mlen, header_present + 4 * reg_width); 925 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 926 mlen += reg_width; 927 928 inst = emit(SHADER_OPCODE_TXL, dst); 929 break; 930 case ir_txd: { 931 ir->lod_info.grad.dPdx->accept(this); 932 fs_reg dPdx = this->result; 933 934 ir->lod_info.grad.dPdy->accept(this); 935 fs_reg dPdy = this->result; 936 937 mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */ 938 939 /** 940 * P = u, v, r 941 * dPdx = dudx, dvdx, drdx 942 * dPdy = dudy, dvdy, drdy 943 * 944 * Load up these values: 945 * - dudx dudy dvdx dvdy drdx drdy 946 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z 947 */ 948 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 949 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 950 dPdx.reg_offset++; 951 mlen += reg_width; 952 953 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 954 dPdy.reg_offset++; 955 mlen += reg_width; 956 } 957 958 inst = emit(SHADER_OPCODE_TXD, dst); 959 break; 960 } 961 case ir_txs: 962 ir->lod_info.lod->accept(this); 963 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 964 mlen += reg_width; 965 inst = emit(SHADER_OPCODE_TXS, dst); 966 break; 967 case ir_txf: 968 mlen = header_present + 4 * reg_width; 969 970 ir->lod_info.lod->accept(this); 971 emit(BRW_OPCODE_MOV, 972 fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), 973 this->result); 974 inst = emit(SHADER_OPCODE_TXF, dst); 975 break; 976 } 977 inst->base_mrf = base_mrf; 978 inst->mlen = mlen; 979 inst->header_present = header_present; 980 981 if (mlen > 11) { 982 fail("Message length >11 disallowed by hardware\n"); 983 } 984 985 return inst; 986} 987 988fs_inst * 989fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate, 990 int sampler) 991{ 992 int mlen = 0; 993 int base_mrf = 2; 994 int reg_width = c->dispatch_width / 8; 995 bool header_present = false; 996 int offsets[3]; 997 998 if (ir->offset && ir->op != ir_txf) { 999 /* The offsets set up by the ir_texture visitor are in the 1000 * m1 header, so we can't go headerless. 1001 */ 1002 header_present = true; 1003 mlen++; 1004 base_mrf--; 1005 } 1006 1007 if (ir->shadow_comparitor && ir->op != ir_txd) { 1008 ir->shadow_comparitor->accept(this); 1009 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 1010 mlen += reg_width; 1011 } 1012 1013 /* Set up the LOD info */ 1014 switch (ir->op) { 1015 case ir_tex: 1016 break; 1017 case ir_txb: 1018 ir->lod_info.bias->accept(this); 1019 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 1020 mlen += reg_width; 1021 break; 1022 case ir_txl: 1023 ir->lod_info.lod->accept(this); 1024 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 1025 mlen += reg_width; 1026 break; 1027 case ir_txd: { 1028 if (c->dispatch_width == 16) 1029 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode."); 1030 1031 ir->lod_info.grad.dPdx->accept(this); 1032 fs_reg dPdx = this->result; 1033 1034 ir->lod_info.grad.dPdy->accept(this); 1035 fs_reg dPdy = this->result; 1036 1037 /* Load dPdx and the coordinate together: 1038 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z 1039 */ 1040 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 1041 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), coordinate); 1042 coordinate.reg_offset++; 1043 mlen += reg_width; 1044 1045 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 1046 dPdx.reg_offset++; 1047 mlen += reg_width; 1048 1049 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 1050 dPdy.reg_offset++; 1051 mlen += reg_width; 1052 } 1053 break; 1054 } 1055 case ir_txs: 1056 ir->lod_info.lod->accept(this); 1057 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 1058 mlen += reg_width; 1059 break; 1060 case ir_txf: 1061 /* It appears that the ld instruction used for txf does its 1062 * address bounds check before adding in the offset. To work 1063 * around this, just add the integer offset to the integer texel 1064 * coordinate, and don't put the offset in the header. 1065 */ 1066 if (ir->offset) { 1067 ir_constant *offset = ir->offset->as_constant(); 1068 offsets[0] = offset->value.i[0]; 1069 offsets[1] = offset->value.i[1]; 1070 offsets[2] = offset->value.i[2]; 1071 } else { 1072 memset(offsets, 0, sizeof(offsets)); 1073 } 1074 1075 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */ 1076 emit(BRW_OPCODE_ADD, 1077 fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), coordinate, offsets[0]); 1078 coordinate.reg_offset++; 1079 mlen += reg_width; 1080 1081 ir->lod_info.lod->accept(this); 1082 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), this->result); 1083 mlen += reg_width; 1084 1085 for (int i = 1; i < ir->coordinate->type->vector_elements; i++) { 1086 emit(BRW_OPCODE_ADD, 1087 fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), coordinate, offsets[i]); 1088 coordinate.reg_offset++; 1089 mlen += reg_width; 1090 } 1091 break; 1092 } 1093 1094 /* Set up the coordinate (except for cases where it was done above) */ 1095 if (ir->op != ir_txd && ir->op != ir_txs && ir->op != ir_txf) { 1096 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 1097 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), coordinate); 1098 coordinate.reg_offset++; 1099 mlen += reg_width; 1100 } 1101 } 1102 1103 /* Generate the SEND */ 1104 fs_inst *inst = NULL; 1105 switch (ir->op) { 1106 case ir_tex: inst = emit(SHADER_OPCODE_TEX, dst); break; 1107 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break; 1108 case ir_txl: inst = emit(SHADER_OPCODE_TXL, dst); break; 1109 case ir_txd: inst = emit(SHADER_OPCODE_TXD, dst); break; 1110 case ir_txf: inst = emit(SHADER_OPCODE_TXF, dst); break; 1111 case ir_txs: inst = emit(SHADER_OPCODE_TXS, dst); break; 1112 } 1113 inst->base_mrf = base_mrf; 1114 inst->mlen = mlen; 1115 inst->header_present = header_present; 1116 1117 if (mlen > 11) { 1118 fail("Message length >11 disallowed by hardware\n"); 1119 } 1120 1121 return inst; 1122} 1123 1124void 1125fs_visitor::visit(ir_texture *ir) 1126{ 1127 fs_inst *inst = NULL; 1128 1129 int sampler = _mesa_get_sampler_uniform_value(ir->sampler, prog, &fp->Base); 1130 sampler = fp->Base.SamplerUnits[sampler]; 1131 1132 /* Our hardware doesn't have a sample_d_c message, so shadow compares 1133 * for textureGrad/TXD need to be emulated with instructions. 1134 */ 1135 bool hw_compare_supported = ir->op != ir_txd; 1136 if (ir->shadow_comparitor && !hw_compare_supported) { 1137 assert(c->key.tex.compare_funcs[sampler] != GL_NONE); 1138 /* No need to even sample for GL_ALWAYS or GL_NEVER...bail early */ 1139 if (c->key.tex.compare_funcs[sampler] == GL_ALWAYS) 1140 return swizzle_result(ir, fs_reg(1.0f), sampler); 1141 else if (c->key.tex.compare_funcs[sampler] == GL_NEVER) 1142 return swizzle_result(ir, fs_reg(0.0f), sampler); 1143 } 1144 1145 if (ir->coordinate) 1146 ir->coordinate->accept(this); 1147 fs_reg coordinate = this->result; 1148 1149 if (ir->offset != NULL && !(intel->gen == 7 && ir->op == ir_txf)) { 1150 uint32_t offset_bits = brw_texture_offset(ir->offset->as_constant()); 1151 1152 /* Explicitly set up the message header by copying g0 to msg reg m1. */ 1153 emit(BRW_OPCODE_MOV, fs_reg(MRF, 1, BRW_REGISTER_TYPE_UD), 1154 fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD))); 1155 1156 /* Then set the offset bits in DWord 2 of the message header. */ 1157 emit(BRW_OPCODE_MOV, 1158 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 1, 2), 1159 BRW_REGISTER_TYPE_UD)), 1160 fs_reg(brw_imm_uw(offset_bits))); 1161 } 1162 1163 /* Should be lowered by do_lower_texture_projection */ 1164 assert(!ir->projector); 1165 1166 bool needs_gl_clamp = true; 1167 1168 fs_reg scale_x, scale_y; 1169 1170 /* The 965 requires the EU to do the normalization of GL rectangle 1171 * texture coordinates. We use the program parameter state 1172 * tracking to get the scaling factor. 1173 */ 1174 if (ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT && 1175 (intel->gen < 6 || 1176 (intel->gen >= 6 && (c->key.tex.gl_clamp_mask[0] & (1 << sampler) || 1177 c->key.tex.gl_clamp_mask[1] & (1 << sampler))))) { 1178 struct gl_program_parameter_list *params = c->fp->program.Base.Parameters; 1179 int tokens[STATE_LENGTH] = { 1180 STATE_INTERNAL, 1181 STATE_TEXRECT_SCALE, 1182 sampler, 1183 0, 1184 0 1185 }; 1186 1187 if (c->dispatch_width == 16) { 1188 fail("rectangle scale uniform setup not supported on 16-wide\n"); 1189 this->result = fs_reg(this, ir->type); 1190 return; 1191 } 1192 1193 c->prog_data.param_convert[c->prog_data.nr_params] = 1194 PARAM_NO_CONVERT; 1195 c->prog_data.param_convert[c->prog_data.nr_params + 1] = 1196 PARAM_NO_CONVERT; 1197 1198 scale_x = fs_reg(UNIFORM, c->prog_data.nr_params); 1199 scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1); 1200 1201 GLuint index = _mesa_add_state_reference(params, 1202 (gl_state_index *)tokens); 1203 1204 this->param_index[c->prog_data.nr_params] = index; 1205 this->param_offset[c->prog_data.nr_params] = 0; 1206 c->prog_data.nr_params++; 1207 this->param_index[c->prog_data.nr_params] = index; 1208 this->param_offset[c->prog_data.nr_params] = 1; 1209 c->prog_data.nr_params++; 1210 } 1211 1212 /* The 965 requires the EU to do the normalization of GL rectangle 1213 * texture coordinates. We use the program parameter state 1214 * tracking to get the scaling factor. 1215 */ 1216 if (intel->gen < 6 && 1217 ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) { 1218 fs_reg dst = fs_reg(this, ir->coordinate->type); 1219 fs_reg src = coordinate; 1220 coordinate = dst; 1221 1222 emit(BRW_OPCODE_MUL, dst, src, scale_x); 1223 dst.reg_offset++; 1224 src.reg_offset++; 1225 emit(BRW_OPCODE_MUL, dst, src, scale_y); 1226 } else if (ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) { 1227 /* On gen6+, the sampler handles the rectangle coordinates 1228 * natively, without needing rescaling. But that means we have 1229 * to do GL_CLAMP clamping at the [0, width], [0, height] scale, 1230 * not [0, 1] like the default case below. 1231 */ 1232 needs_gl_clamp = false; 1233 1234 for (int i = 0; i < 2; i++) { 1235 if (c->key.tex.gl_clamp_mask[i] & (1 << sampler)) { 1236 fs_reg chan = coordinate; 1237 chan.reg_offset += i; 1238 1239 inst = emit(BRW_OPCODE_SEL, chan, chan, brw_imm_f(0.0)); 1240 inst->conditional_mod = BRW_CONDITIONAL_G; 1241 1242 /* Our parameter comes in as 1.0/width or 1.0/height, 1243 * because that's what people normally want for doing 1244 * texture rectangle handling. We need width or height 1245 * for clamping, but we don't care enough to make a new 1246 * parameter type, so just invert back. 1247 */ 1248 fs_reg limit = fs_reg(this, glsl_type::float_type); 1249 emit(BRW_OPCODE_MOV, limit, i == 0 ? scale_x : scale_y); 1250 emit(SHADER_OPCODE_RCP, limit, limit); 1251 1252 inst = emit(BRW_OPCODE_SEL, chan, chan, limit); 1253 inst->conditional_mod = BRW_CONDITIONAL_L; 1254 } 1255 } 1256 } 1257 1258 if (ir->coordinate && needs_gl_clamp) { 1259 for (int i = 0; i < MIN2(ir->coordinate->type->vector_elements, 3); i++) { 1260 if (c->key.tex.gl_clamp_mask[i] & (1 << sampler)) { 1261 fs_reg chan = coordinate; 1262 chan.reg_offset += i; 1263 1264 fs_inst *inst = emit(BRW_OPCODE_MOV, chan, chan); 1265 inst->saturate = true; 1266 } 1267 } 1268 } 1269 1270 /* Writemasking doesn't eliminate channels on SIMD8 texture 1271 * samples, so don't worry about them. 1272 */ 1273 fs_reg dst = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 4, 1)); 1274 1275 if (intel->gen >= 7) { 1276 inst = emit_texture_gen7(ir, dst, coordinate, sampler); 1277 } else if (intel->gen >= 5) { 1278 inst = emit_texture_gen5(ir, dst, coordinate, sampler); 1279 } else { 1280 inst = emit_texture_gen4(ir, dst, coordinate, sampler); 1281 } 1282 1283 /* If there's an offset, we already set up m1. To avoid the implied move, 1284 * use the null register. Otherwise, we want an implied move from g0. 1285 */ 1286 if (ir->offset != NULL || !inst->header_present) 1287 inst->src[0] = reg_undef; 1288 else 1289 inst->src[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW)); 1290 1291 inst->sampler = sampler; 1292 1293 if (ir->shadow_comparitor) { 1294 if (hw_compare_supported) { 1295 inst->shadow_compare = true; 1296 } else { 1297 ir->shadow_comparitor->accept(this); 1298 fs_reg ref = this->result; 1299 1300 fs_reg value = dst; 1301 dst = fs_reg(this, glsl_type::vec4_type); 1302 1303 /* FINISHME: This needs to be done pre-filtering. */ 1304 1305 uint32_t conditional = 0; 1306 switch (c->key.tex.compare_funcs[sampler]) { 1307 /* GL_ALWAYS and GL_NEVER were handled at the top of the function */ 1308 case GL_LESS: conditional = BRW_CONDITIONAL_L; break; 1309 case GL_GREATER: conditional = BRW_CONDITIONAL_G; break; 1310 case GL_LEQUAL: conditional = BRW_CONDITIONAL_LE; break; 1311 case GL_GEQUAL: conditional = BRW_CONDITIONAL_GE; break; 1312 case GL_EQUAL: conditional = BRW_CONDITIONAL_EQ; break; 1313 case GL_NOTEQUAL: conditional = BRW_CONDITIONAL_NEQ; break; 1314 default: assert(!"Should not get here: bad shadow compare function"); 1315 } 1316 1317 /* Use conditional moves to load 0 or 1 as the result */ 1318 this->current_annotation = "manual shadow comparison"; 1319 for (int i = 0; i < 4; i++) { 1320 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(0.0f)); 1321 1322 inst = emit(BRW_OPCODE_CMP, reg_null_f, ref, value); 1323 inst->conditional_mod = conditional; 1324 1325 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(1.0f)); 1326 inst->predicated = true; 1327 1328 dst.reg_offset++; 1329 value.reg_offset++; 1330 } 1331 dst.reg_offset = 0; 1332 } 1333 } 1334 1335 swizzle_result(ir, dst, sampler); 1336} 1337 1338/** 1339 * Swizzle the result of a texture result. This is necessary for 1340 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons. 1341 */ 1342void 1343fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler) 1344{ 1345 this->result = orig_val; 1346 1347 if (ir->op == ir_txs) 1348 return; 1349 1350 if (ir->type == glsl_type::float_type) { 1351 /* Ignore DEPTH_TEXTURE_MODE swizzling. */ 1352 assert(ir->sampler->type->sampler_shadow); 1353 } else if (c->key.tex.swizzles[sampler] != SWIZZLE_NOOP) { 1354 fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type); 1355 1356 for (int i = 0; i < 4; i++) { 1357 int swiz = GET_SWZ(c->key.tex.swizzles[sampler], i); 1358 fs_reg l = swizzled_result; 1359 l.reg_offset += i; 1360 1361 if (swiz == SWIZZLE_ZERO) { 1362 emit(BRW_OPCODE_MOV, l, fs_reg(0.0f)); 1363 } else if (swiz == SWIZZLE_ONE) { 1364 emit(BRW_OPCODE_MOV, l, fs_reg(1.0f)); 1365 } else { 1366 fs_reg r = orig_val; 1367 r.reg_offset += GET_SWZ(c->key.tex.swizzles[sampler], i); 1368 emit(BRW_OPCODE_MOV, l, r); 1369 } 1370 } 1371 this->result = swizzled_result; 1372 } 1373} 1374 1375void 1376fs_visitor::visit(ir_swizzle *ir) 1377{ 1378 ir->val->accept(this); 1379 fs_reg val = this->result; 1380 1381 if (ir->type->vector_elements == 1) { 1382 this->result.reg_offset += ir->mask.x; 1383 return; 1384 } 1385 1386 fs_reg result = fs_reg(this, ir->type); 1387 this->result = result; 1388 1389 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 1390 fs_reg channel = val; 1391 int swiz = 0; 1392 1393 switch (i) { 1394 case 0: 1395 swiz = ir->mask.x; 1396 break; 1397 case 1: 1398 swiz = ir->mask.y; 1399 break; 1400 case 2: 1401 swiz = ir->mask.z; 1402 break; 1403 case 3: 1404 swiz = ir->mask.w; 1405 break; 1406 } 1407 1408 channel.reg_offset += swiz; 1409 emit(BRW_OPCODE_MOV, result, channel); 1410 result.reg_offset++; 1411 } 1412} 1413 1414void 1415fs_visitor::visit(ir_discard *ir) 1416{ 1417 assert(ir->condition == NULL); /* FINISHME */ 1418 1419 emit(FS_OPCODE_DISCARD); 1420 kill_emitted = true; 1421} 1422 1423void 1424fs_visitor::visit(ir_constant *ir) 1425{ 1426 /* Set this->result to reg at the bottom of the function because some code 1427 * paths will cause this visitor to be applied to other fields. This will 1428 * cause the value stored in this->result to be modified. 1429 * 1430 * Make reg constant so that it doesn't get accidentally modified along the 1431 * way. Yes, I actually had this problem. :( 1432 */ 1433 const fs_reg reg(this, ir->type); 1434 fs_reg dst_reg = reg; 1435 1436 if (ir->type->is_array()) { 1437 const unsigned size = type_size(ir->type->fields.array); 1438 1439 for (unsigned i = 0; i < ir->type->length; i++) { 1440 ir->array_elements[i]->accept(this); 1441 fs_reg src_reg = this->result; 1442 1443 dst_reg.type = src_reg.type; 1444 for (unsigned j = 0; j < size; j++) { 1445 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1446 src_reg.reg_offset++; 1447 dst_reg.reg_offset++; 1448 } 1449 } 1450 } else if (ir->type->is_record()) { 1451 foreach_list(node, &ir->components) { 1452 ir_constant *const field = (ir_constant *) node; 1453 const unsigned size = type_size(field->type); 1454 1455 field->accept(this); 1456 fs_reg src_reg = this->result; 1457 1458 dst_reg.type = src_reg.type; 1459 for (unsigned j = 0; j < size; j++) { 1460 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1461 src_reg.reg_offset++; 1462 dst_reg.reg_offset++; 1463 } 1464 } 1465 } else { 1466 const unsigned size = type_size(ir->type); 1467 1468 for (unsigned i = 0; i < size; i++) { 1469 switch (ir->type->base_type) { 1470 case GLSL_TYPE_FLOAT: 1471 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i])); 1472 break; 1473 case GLSL_TYPE_UINT: 1474 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i])); 1475 break; 1476 case GLSL_TYPE_INT: 1477 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.i[i])); 1478 break; 1479 case GLSL_TYPE_BOOL: 1480 emit(BRW_OPCODE_MOV, dst_reg, fs_reg((int)ir->value.b[i])); 1481 break; 1482 default: 1483 assert(!"Non-float/uint/int/bool constant"); 1484 } 1485 dst_reg.reg_offset++; 1486 } 1487 } 1488 1489 this->result = reg; 1490} 1491 1492void 1493fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir) 1494{ 1495 ir_expression *expr = ir->as_expression(); 1496 1497 if (expr) { 1498 fs_reg op[2]; 1499 fs_inst *inst; 1500 1501 assert(expr->get_num_operands() <= 2); 1502 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1503 assert(expr->operands[i]->type->is_scalar()); 1504 1505 expr->operands[i]->accept(this); 1506 op[i] = this->result; 1507 1508 resolve_ud_negate(&op[i]); 1509 } 1510 1511 switch (expr->operation) { 1512 case ir_unop_logic_not: 1513 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1)); 1514 inst->conditional_mod = BRW_CONDITIONAL_Z; 1515 break; 1516 1517 case ir_binop_logic_xor: 1518 case ir_binop_logic_or: 1519 case ir_binop_logic_and: 1520 goto out; 1521 1522 case ir_unop_f2b: 1523 if (intel->gen >= 6) { 1524 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0.0f)); 1525 } else { 1526 inst = emit(BRW_OPCODE_MOV, reg_null_f, op[0]); 1527 } 1528 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1529 break; 1530 1531 case ir_unop_i2b: 1532 if (intel->gen >= 6) { 1533 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0)); 1534 } else { 1535 inst = emit(BRW_OPCODE_MOV, reg_null_d, op[0]); 1536 } 1537 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1538 break; 1539 1540 case ir_binop_greater: 1541 case ir_binop_gequal: 1542 case ir_binop_less: 1543 case ir_binop_lequal: 1544 case ir_binop_equal: 1545 case ir_binop_all_equal: 1546 case ir_binop_nequal: 1547 case ir_binop_any_nequal: 1548 resolve_bool_comparison(expr->operands[0], &op[0]); 1549 resolve_bool_comparison(expr->operands[1], &op[1]); 1550 1551 inst = emit(BRW_OPCODE_CMP, reg_null_cmp, op[0], op[1]); 1552 inst->conditional_mod = 1553 brw_conditional_for_comparison(expr->operation); 1554 break; 1555 1556 default: 1557 assert(!"not reached"); 1558 fail("bad cond code\n"); 1559 break; 1560 } 1561 return; 1562 } 1563 1564out: 1565 ir->accept(this); 1566 1567 fs_inst *inst = emit(BRW_OPCODE_AND, reg_null_d, this->result, fs_reg(1)); 1568 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1569} 1570 1571/** 1572 * Emit a gen6 IF statement with the comparison folded into the IF 1573 * instruction. 1574 */ 1575void 1576fs_visitor::emit_if_gen6(ir_if *ir) 1577{ 1578 ir_expression *expr = ir->condition->as_expression(); 1579 1580 if (expr) { 1581 fs_reg op[2]; 1582 fs_inst *inst; 1583 fs_reg temp; 1584 1585 assert(expr->get_num_operands() <= 2); 1586 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1587 assert(expr->operands[i]->type->is_scalar()); 1588 1589 expr->operands[i]->accept(this); 1590 op[i] = this->result; 1591 } 1592 1593 switch (expr->operation) { 1594 case ir_unop_logic_not: 1595 inst = emit(BRW_OPCODE_IF, temp, op[0], fs_reg(0)); 1596 inst->conditional_mod = BRW_CONDITIONAL_Z; 1597 return; 1598 1599 case ir_binop_logic_xor: 1600 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1601 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1602 return; 1603 1604 case ir_binop_logic_or: 1605 temp = fs_reg(this, glsl_type::bool_type); 1606 emit(BRW_OPCODE_OR, temp, op[0], op[1]); 1607 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1608 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1609 return; 1610 1611 case ir_binop_logic_and: 1612 temp = fs_reg(this, glsl_type::bool_type); 1613 emit(BRW_OPCODE_AND, temp, op[0], op[1]); 1614 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1615 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1616 return; 1617 1618 case ir_unop_f2b: 1619 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0)); 1620 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1621 return; 1622 1623 case ir_unop_i2b: 1624 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1625 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1626 return; 1627 1628 case ir_binop_greater: 1629 case ir_binop_gequal: 1630 case ir_binop_less: 1631 case ir_binop_lequal: 1632 case ir_binop_equal: 1633 case ir_binop_all_equal: 1634 case ir_binop_nequal: 1635 case ir_binop_any_nequal: 1636 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1637 inst->conditional_mod = 1638 brw_conditional_for_comparison(expr->operation); 1639 return; 1640 default: 1641 assert(!"not reached"); 1642 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1643 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1644 fail("bad condition\n"); 1645 return; 1646 } 1647 return; 1648 } 1649 1650 ir->condition->accept(this); 1651 1652 fs_inst *inst = emit(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0)); 1653 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1654} 1655 1656void 1657fs_visitor::visit(ir_if *ir) 1658{ 1659 fs_inst *inst; 1660 1661 if (intel->gen < 6 && c->dispatch_width == 16) { 1662 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1663 } 1664 1665 /* Don't point the annotation at the if statement, because then it plus 1666 * the then and else blocks get printed. 1667 */ 1668 this->base_ir = ir->condition; 1669 1670 if (intel->gen == 6) { 1671 emit_if_gen6(ir); 1672 } else { 1673 emit_bool_to_cond_code(ir->condition); 1674 1675 inst = emit(BRW_OPCODE_IF); 1676 inst->predicated = true; 1677 } 1678 1679 foreach_list(node, &ir->then_instructions) { 1680 ir_instruction *ir = (ir_instruction *)node; 1681 this->base_ir = ir; 1682 1683 ir->accept(this); 1684 } 1685 1686 if (!ir->else_instructions.is_empty()) { 1687 emit(BRW_OPCODE_ELSE); 1688 1689 foreach_list(node, &ir->else_instructions) { 1690 ir_instruction *ir = (ir_instruction *)node; 1691 this->base_ir = ir; 1692 1693 ir->accept(this); 1694 } 1695 } 1696 1697 emit(BRW_OPCODE_ENDIF); 1698} 1699 1700void 1701fs_visitor::visit(ir_loop *ir) 1702{ 1703 fs_reg counter = reg_undef; 1704 1705 if (intel->gen < 6 && c->dispatch_width == 16) { 1706 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1707 } 1708 1709 if (ir->counter) { 1710 this->base_ir = ir->counter; 1711 ir->counter->accept(this); 1712 counter = *(variable_storage(ir->counter)); 1713 1714 if (ir->from) { 1715 this->base_ir = ir->from; 1716 ir->from->accept(this); 1717 1718 emit(BRW_OPCODE_MOV, counter, this->result); 1719 } 1720 } 1721 1722 this->base_ir = NULL; 1723 emit(BRW_OPCODE_DO); 1724 1725 if (ir->to) { 1726 this->base_ir = ir->to; 1727 ir->to->accept(this); 1728 1729 fs_inst *inst = emit(BRW_OPCODE_CMP, reg_null_cmp, counter, this->result); 1730 inst->conditional_mod = brw_conditional_for_comparison(ir->cmp); 1731 1732 inst = emit(BRW_OPCODE_BREAK); 1733 inst->predicated = true; 1734 } 1735 1736 foreach_list(node, &ir->body_instructions) { 1737 ir_instruction *ir = (ir_instruction *)node; 1738 1739 this->base_ir = ir; 1740 ir->accept(this); 1741 } 1742 1743 if (ir->increment) { 1744 this->base_ir = ir->increment; 1745 ir->increment->accept(this); 1746 emit(BRW_OPCODE_ADD, counter, counter, this->result); 1747 } 1748 1749 this->base_ir = NULL; 1750 emit(BRW_OPCODE_WHILE); 1751} 1752 1753void 1754fs_visitor::visit(ir_loop_jump *ir) 1755{ 1756 switch (ir->mode) { 1757 case ir_loop_jump::jump_break: 1758 emit(BRW_OPCODE_BREAK); 1759 break; 1760 case ir_loop_jump::jump_continue: 1761 emit(BRW_OPCODE_CONTINUE); 1762 break; 1763 } 1764} 1765 1766void 1767fs_visitor::visit(ir_call *ir) 1768{ 1769 assert(!"FINISHME"); 1770} 1771 1772void 1773fs_visitor::visit(ir_return *ir) 1774{ 1775 assert(!"FINISHME"); 1776} 1777 1778void 1779fs_visitor::visit(ir_function *ir) 1780{ 1781 /* Ignore function bodies other than main() -- we shouldn't see calls to 1782 * them since they should all be inlined before we get to ir_to_mesa. 1783 */ 1784 if (strcmp(ir->name, "main") == 0) { 1785 const ir_function_signature *sig; 1786 exec_list empty; 1787 1788 sig = ir->matching_signature(&empty); 1789 1790 assert(sig); 1791 1792 foreach_list(node, &sig->body) { 1793 ir_instruction *ir = (ir_instruction *)node; 1794 this->base_ir = ir; 1795 1796 ir->accept(this); 1797 } 1798 } 1799} 1800 1801void 1802fs_visitor::visit(ir_function_signature *ir) 1803{ 1804 assert(!"not reached"); 1805 (void)ir; 1806} 1807 1808fs_inst * 1809fs_visitor::emit(fs_inst inst) 1810{ 1811 fs_inst *list_inst = new(mem_ctx) fs_inst; 1812 *list_inst = inst; 1813 1814 if (force_uncompressed_stack > 0) 1815 list_inst->force_uncompressed = true; 1816 else if (force_sechalf_stack > 0) 1817 list_inst->force_sechalf = true; 1818 1819 list_inst->annotation = this->current_annotation; 1820 list_inst->ir = this->base_ir; 1821 1822 this->instructions.push_tail(list_inst); 1823 1824 return list_inst; 1825} 1826 1827/** Emits a dummy fragment shader consisting of magenta for bringup purposes. */ 1828void 1829fs_visitor::emit_dummy_fs() 1830{ 1831 int reg_width = c->dispatch_width / 8; 1832 1833 /* Everyone's favorite color. */ 1834 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2 + 0 * reg_width), fs_reg(1.0f)); 1835 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2 + 1 * reg_width), fs_reg(0.0f)); 1836 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2 + 2 * reg_width), fs_reg(1.0f)); 1837 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2 + 3 * reg_width), fs_reg(0.0f)); 1838 1839 fs_inst *write; 1840 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0)); 1841 write->base_mrf = 2; 1842 write->mlen = 4 * reg_width; 1843 write->eot = true; 1844} 1845 1846/* The register location here is relative to the start of the URB 1847 * data. It will get adjusted to be a real location before 1848 * generate_code() time. 1849 */ 1850struct brw_reg 1851fs_visitor::interp_reg(int location, int channel) 1852{ 1853 int regnr = urb_setup[location] * 2 + channel / 2; 1854 int stride = (channel & 1) * 4; 1855 1856 assert(urb_setup[location] != -1); 1857 1858 return brw_vec1_grf(regnr, stride); 1859} 1860 1861/** Emits the interpolation for the varying inputs. */ 1862void 1863fs_visitor::emit_interpolation_setup_gen4() 1864{ 1865 this->current_annotation = "compute pixel centers"; 1866 this->pixel_x = fs_reg(this, glsl_type::uint_type); 1867 this->pixel_y = fs_reg(this, glsl_type::uint_type); 1868 this->pixel_x.type = BRW_REGISTER_TYPE_UW; 1869 this->pixel_y.type = BRW_REGISTER_TYPE_UW; 1870 1871 emit(FS_OPCODE_PIXEL_X, this->pixel_x); 1872 emit(FS_OPCODE_PIXEL_Y, this->pixel_y); 1873 1874 this->current_annotation = "compute pixel deltas from v0"; 1875 if (brw->has_pln) { 1876 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] = 1877 fs_reg(this, glsl_type::vec2_type); 1878 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] = 1879 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC]; 1880 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].reg_offset++; 1881 } else { 1882 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] = 1883 fs_reg(this, glsl_type::float_type); 1884 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] = 1885 fs_reg(this, glsl_type::float_type); 1886 } 1887 emit(BRW_OPCODE_ADD, this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC], 1888 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))); 1889 emit(BRW_OPCODE_ADD, this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC], 1890 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))); 1891 1892 this->current_annotation = "compute pos.w and 1/pos.w"; 1893 /* Compute wpos.w. It's always in our setup, since it's needed to 1894 * interpolate the other attributes. 1895 */ 1896 this->wpos_w = fs_reg(this, glsl_type::float_type); 1897 emit(FS_OPCODE_LINTERP, wpos_w, 1898 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC], 1899 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC], 1900 interp_reg(FRAG_ATTRIB_WPOS, 3)); 1901 /* Compute the pixel 1/W value from wpos.w. */ 1902 this->pixel_w = fs_reg(this, glsl_type::float_type); 1903 emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w); 1904 this->current_annotation = NULL; 1905} 1906 1907/** Emits the interpolation for the varying inputs. */ 1908void 1909fs_visitor::emit_interpolation_setup_gen6() 1910{ 1911 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); 1912 1913 /* If the pixel centers end up used, the setup is the same as for gen4. */ 1914 this->current_annotation = "compute pixel centers"; 1915 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type); 1916 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type); 1917 int_pixel_x.type = BRW_REGISTER_TYPE_UW; 1918 int_pixel_y.type = BRW_REGISTER_TYPE_UW; 1919 emit(BRW_OPCODE_ADD, 1920 int_pixel_x, 1921 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), 1922 fs_reg(brw_imm_v(0x10101010))); 1923 emit(BRW_OPCODE_ADD, 1924 int_pixel_y, 1925 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), 1926 fs_reg(brw_imm_v(0x11001100))); 1927 1928 /* As of gen6, we can no longer mix float and int sources. We have 1929 * to turn the integer pixel centers into floats for their actual 1930 * use. 1931 */ 1932 this->pixel_x = fs_reg(this, glsl_type::float_type); 1933 this->pixel_y = fs_reg(this, glsl_type::float_type); 1934 emit(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x); 1935 emit(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y); 1936 1937 this->current_annotation = "compute pos.w"; 1938 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0)); 1939 this->wpos_w = fs_reg(this, glsl_type::float_type); 1940 emit_math(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w); 1941 1942 for (int i = 0; i < BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT; ++i) { 1943 uint8_t reg = c->barycentric_coord_reg[i]; 1944 this->delta_x[i] = fs_reg(brw_vec8_grf(reg, 0)); 1945 this->delta_y[i] = fs_reg(brw_vec8_grf(reg + 1, 0)); 1946 } 1947 1948 this->current_annotation = NULL; 1949} 1950 1951void 1952fs_visitor::emit_color_write(int target, int index, int first_color_mrf) 1953{ 1954 int reg_width = c->dispatch_width / 8; 1955 fs_inst *inst; 1956 fs_reg color = outputs[target]; 1957 fs_reg mrf; 1958 1959 /* If there's no color data to be written, skip it. */ 1960 if (color.file == BAD_FILE) 1961 return; 1962 1963 color.reg_offset += index; 1964 1965 if (c->dispatch_width == 8 || intel->gen >= 6) { 1966 /* SIMD8 write looks like: 1967 * m + 0: r0 1968 * m + 1: r1 1969 * m + 2: g0 1970 * m + 3: g1 1971 * 1972 * gen6 SIMD16 DP write looks like: 1973 * m + 0: r0 1974 * m + 1: r1 1975 * m + 2: g0 1976 * m + 3: g1 1977 * m + 4: b0 1978 * m + 5: b1 1979 * m + 6: a0 1980 * m + 7: a1 1981 */ 1982 inst = emit(BRW_OPCODE_MOV, 1983 fs_reg(MRF, first_color_mrf + index * reg_width, color.type), 1984 color); 1985 inst->saturate = c->key.clamp_fragment_color; 1986 } else { 1987 /* pre-gen6 SIMD16 single source DP write looks like: 1988 * m + 0: r0 1989 * m + 1: g0 1990 * m + 2: b0 1991 * m + 3: a0 1992 * m + 4: r1 1993 * m + 5: g1 1994 * m + 6: b1 1995 * m + 7: a1 1996 */ 1997 if (brw->has_compr4) { 1998 /* By setting the high bit of the MRF register number, we 1999 * indicate that we want COMPR4 mode - instead of doing the 2000 * usual destination + 1 for the second half we get 2001 * destination + 4. 2002 */ 2003 inst = emit(BRW_OPCODE_MOV, 2004 fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index, 2005 color.type), 2006 color); 2007 inst->saturate = c->key.clamp_fragment_color; 2008 } else { 2009 push_force_uncompressed(); 2010 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index, 2011 color.type), 2012 color); 2013 inst->saturate = c->key.clamp_fragment_color; 2014 pop_force_uncompressed(); 2015 2016 push_force_sechalf(); 2017 color.sechalf = true; 2018 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index + 4, 2019 color.type), 2020 color); 2021 inst->saturate = c->key.clamp_fragment_color; 2022 pop_force_sechalf(); 2023 color.sechalf = false; 2024 } 2025 } 2026} 2027 2028void 2029fs_visitor::emit_fb_writes() 2030{ 2031 this->current_annotation = "FB write header"; 2032 bool header_present = true; 2033 /* We can potentially have a message length of up to 15, so we have to set 2034 * base_mrf to either 0 or 1 in order to fit in m0..m15. 2035 */ 2036 int base_mrf = 1; 2037 int nr = base_mrf; 2038 int reg_width = c->dispatch_width / 8; 2039 2040 if (intel->gen >= 6 && 2041 !this->kill_emitted && 2042 c->key.nr_color_regions == 1) { 2043 header_present = false; 2044 } 2045 2046 if (header_present) { 2047 /* m2, m3 header */ 2048 nr += 2; 2049 } 2050 2051 if (c->aa_dest_stencil_reg) { 2052 push_force_uncompressed(); 2053 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++), 2054 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))); 2055 pop_force_uncompressed(); 2056 } 2057 2058 /* Reserve space for color. It'll be filled in per MRT below. */ 2059 int color_mrf = nr; 2060 nr += 4 * reg_width; 2061 2062 if (c->source_depth_to_render_target) { 2063 if (intel->gen == 6 && c->dispatch_width == 16) { 2064 /* For outputting oDepth on gen6, SIMD8 writes have to be 2065 * used. This would require 8-wide moves of each half to 2066 * message regs, kind of like pre-gen5 SIMD16 FB writes. 2067 * Just bail on doing so for now. 2068 */ 2069 fail("Missing support for simd16 depth writes on gen6\n"); 2070 } 2071 2072 if (c->computes_depth) { 2073 /* Hand over gl_FragDepth. */ 2074 assert(this->frag_depth); 2075 fs_reg depth = *(variable_storage(this->frag_depth)); 2076 2077 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), depth); 2078 } else { 2079 /* Pass through the payload depth. */ 2080 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 2081 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))); 2082 } 2083 nr += reg_width; 2084 } 2085 2086 if (c->dest_depth_reg) { 2087 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 2088 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))); 2089 nr += reg_width; 2090 } 2091 2092 for (int target = 0; target < c->key.nr_color_regions; target++) { 2093 this->current_annotation = ralloc_asprintf(this->mem_ctx, 2094 "FB write target %d", 2095 target); 2096 for (int i = 0; i < 4; i++) 2097 emit_color_write(target, i, color_mrf); 2098 2099 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 2100 inst->target = target; 2101 inst->base_mrf = base_mrf; 2102 inst->mlen = nr - base_mrf; 2103 if (target == c->key.nr_color_regions - 1) 2104 inst->eot = true; 2105 inst->header_present = header_present; 2106 } 2107 2108 if (c->key.nr_color_regions == 0) { 2109 if (c->key.alpha_test) { 2110 /* If the alpha test is enabled but there's no color buffer, 2111 * we still need to send alpha out the pipeline to our null 2112 * renderbuffer. 2113 */ 2114 emit_color_write(0, 3, color_mrf); 2115 } 2116 2117 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 2118 inst->base_mrf = base_mrf; 2119 inst->mlen = nr - base_mrf; 2120 inst->eot = true; 2121 inst->header_present = header_present; 2122 } 2123 2124 this->current_annotation = NULL; 2125} 2126 2127void 2128fs_visitor::resolve_ud_negate(fs_reg *reg) 2129{ 2130 if (reg->type != BRW_REGISTER_TYPE_UD || 2131 !reg->negate) 2132 return; 2133 2134 fs_reg temp = fs_reg(this, glsl_type::uint_type); 2135 emit(BRW_OPCODE_MOV, temp, *reg); 2136 *reg = temp; 2137} 2138 2139void 2140fs_visitor::resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg) 2141{ 2142 if (rvalue->type != glsl_type::bool_type) 2143 return; 2144 2145 fs_reg temp = fs_reg(this, glsl_type::bool_type); 2146 emit(BRW_OPCODE_AND, temp, *reg, fs_reg(1)); 2147 *reg = temp; 2148} 2149