brw_fs_visitor.cpp revision febad1779ae5cb5c85d66c2635baea62da52d2fa
1/* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24/** @file brw_fs_visitor.cpp 25 * 26 * This file supports generating the FS LIR from the GLSL IR. The LIR 27 * makes it easier to do backend-specific optimizations than doing so 28 * in the GLSL IR or in the native code. 29 */ 30extern "C" { 31 32#include <sys/types.h> 33 34#include "main/macros.h" 35#include "main/shaderobj.h" 36#include "main/uniforms.h" 37#include "program/prog_parameter.h" 38#include "program/prog_print.h" 39#include "program/prog_optimize.h" 40#include "program/register_allocate.h" 41#include "program/sampler.h" 42#include "program/hash_table.h" 43#include "brw_context.h" 44#include "brw_eu.h" 45#include "brw_wm.h" 46} 47#include "brw_shader.h" 48#include "brw_fs.h" 49#include "glsl/glsl_types.h" 50#include "glsl/ir_optimization.h" 51#include "glsl/ir_print_visitor.h" 52 53void 54fs_visitor::visit(ir_variable *ir) 55{ 56 fs_reg *reg = NULL; 57 58 if (variable_storage(ir)) 59 return; 60 61 if (ir->mode == ir_var_in) { 62 if (!strcmp(ir->name, "gl_FragCoord")) { 63 reg = emit_fragcoord_interpolation(ir); 64 } else if (!strcmp(ir->name, "gl_FrontFacing")) { 65 reg = emit_frontfacing_interpolation(ir); 66 } else { 67 reg = emit_general_interpolation(ir); 68 } 69 assert(reg); 70 hash_table_insert(this->variable_ht, reg, ir); 71 return; 72 } else if (ir->mode == ir_var_out) { 73 reg = new(this->mem_ctx) fs_reg(this, ir->type); 74 75 if (ir->location == FRAG_RESULT_COLOR) { 76 /* Writing gl_FragColor outputs to all color regions. */ 77 for (int i = 0; i < MAX2(c->key.nr_color_regions, 1); i++) { 78 this->outputs[i] = *reg; 79 } 80 } else if (ir->location == FRAG_RESULT_DEPTH) { 81 this->frag_depth = ir; 82 } else { 83 /* gl_FragData or a user-defined FS output */ 84 assert(ir->location >= FRAG_RESULT_DATA0 && 85 ir->location < FRAG_RESULT_DATA0 + BRW_MAX_DRAW_BUFFERS); 86 87 /* General color output. */ 88 for (unsigned int i = 0; i < MAX2(1, ir->type->length); i++) { 89 int output = ir->location - FRAG_RESULT_DATA0 + i; 90 this->outputs[output] = *reg; 91 this->outputs[output].reg_offset += 4 * i; 92 } 93 } 94 } else if (ir->mode == ir_var_uniform) { 95 int param_index = c->prog_data.nr_params; 96 97 if (c->dispatch_width == 16) { 98 if (!variable_storage(ir)) { 99 fail("Failed to find uniform '%s' in 16-wide\n", ir->name); 100 } 101 return; 102 } 103 104 if (!strncmp(ir->name, "gl_", 3)) { 105 setup_builtin_uniform_values(ir); 106 } else { 107 setup_uniform_values(ir->location, ir->type); 108 } 109 110 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index); 111 reg->type = brw_type_for_base_type(ir->type); 112 } 113 114 if (!reg) 115 reg = new(this->mem_ctx) fs_reg(this, ir->type); 116 117 hash_table_insert(this->variable_ht, reg, ir); 118} 119 120void 121fs_visitor::visit(ir_dereference_variable *ir) 122{ 123 fs_reg *reg = variable_storage(ir->var); 124 this->result = *reg; 125} 126 127void 128fs_visitor::visit(ir_dereference_record *ir) 129{ 130 const glsl_type *struct_type = ir->record->type; 131 132 ir->record->accept(this); 133 134 unsigned int offset = 0; 135 for (unsigned int i = 0; i < struct_type->length; i++) { 136 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0) 137 break; 138 offset += type_size(struct_type->fields.structure[i].type); 139 } 140 this->result.reg_offset += offset; 141 this->result.type = brw_type_for_base_type(ir->type); 142} 143 144void 145fs_visitor::visit(ir_dereference_array *ir) 146{ 147 ir_constant *index; 148 int element_size; 149 150 ir->array->accept(this); 151 index = ir->array_index->as_constant(); 152 153 element_size = type_size(ir->type); 154 this->result.type = brw_type_for_base_type(ir->type); 155 156 if (index) { 157 assert(this->result.file == UNIFORM || this->result.file == GRF); 158 this->result.reg_offset += index->value.i[0] * element_size; 159 } else { 160 assert(!"FINISHME: non-constant array element"); 161 } 162} 163 164/* Instruction selection: Produce a MOV.sat instead of 165 * MIN(MAX(val, 0), 1) when possible. 166 */ 167bool 168fs_visitor::try_emit_saturate(ir_expression *ir) 169{ 170 ir_rvalue *sat_val = ir->as_rvalue_to_saturate(); 171 172 if (!sat_val) 173 return false; 174 175 sat_val->accept(this); 176 fs_reg src = this->result; 177 178 this->result = fs_reg(this, ir->type); 179 fs_inst *inst = emit(BRW_OPCODE_MOV, this->result, src); 180 inst->saturate = true; 181 182 return true; 183} 184 185void 186fs_visitor::visit(ir_expression *ir) 187{ 188 unsigned int operand; 189 fs_reg op[2], temp; 190 fs_inst *inst; 191 192 assert(ir->get_num_operands() <= 2); 193 194 if (try_emit_saturate(ir)) 195 return; 196 197 for (operand = 0; operand < ir->get_num_operands(); operand++) { 198 ir->operands[operand]->accept(this); 199 if (this->result.file == BAD_FILE) { 200 ir_print_visitor v; 201 fail("Failed to get tree for expression operand:\n"); 202 ir->operands[operand]->accept(&v); 203 } 204 op[operand] = this->result; 205 206 /* Matrix expression operands should have been broken down to vector 207 * operations already. 208 */ 209 assert(!ir->operands[operand]->type->is_matrix()); 210 /* And then those vector operands should have been broken down to scalar. 211 */ 212 assert(!ir->operands[operand]->type->is_vector()); 213 } 214 215 /* Storage for our result. If our result goes into an assignment, it will 216 * just get copy-propagated out, so no worries. 217 */ 218 this->result = fs_reg(this, ir->type); 219 220 switch (ir->operation) { 221 case ir_unop_logic_not: 222 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is 223 * ones complement of the whole register, not just bit 0. 224 */ 225 emit(BRW_OPCODE_XOR, this->result, op[0], fs_reg(1)); 226 break; 227 case ir_unop_neg: 228 op[0].negate = !op[0].negate; 229 this->result = op[0]; 230 break; 231 case ir_unop_abs: 232 op[0].abs = true; 233 op[0].negate = false; 234 this->result = op[0]; 235 break; 236 case ir_unop_sign: 237 temp = fs_reg(this, ir->type); 238 239 emit(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)); 240 241 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 242 inst->conditional_mod = BRW_CONDITIONAL_G; 243 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)); 244 inst->predicated = true; 245 246 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); 247 inst->conditional_mod = BRW_CONDITIONAL_L; 248 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)); 249 inst->predicated = true; 250 251 break; 252 case ir_unop_rcp: 253 emit_math(SHADER_OPCODE_RCP, this->result, op[0]); 254 break; 255 256 case ir_unop_exp2: 257 emit_math(SHADER_OPCODE_EXP2, this->result, op[0]); 258 break; 259 case ir_unop_log2: 260 emit_math(SHADER_OPCODE_LOG2, this->result, op[0]); 261 break; 262 case ir_unop_exp: 263 case ir_unop_log: 264 assert(!"not reached: should be handled by ir_explog_to_explog2"); 265 break; 266 case ir_unop_sin: 267 case ir_unop_sin_reduced: 268 emit_math(SHADER_OPCODE_SIN, this->result, op[0]); 269 break; 270 case ir_unop_cos: 271 case ir_unop_cos_reduced: 272 emit_math(SHADER_OPCODE_COS, this->result, op[0]); 273 break; 274 275 case ir_unop_dFdx: 276 emit(FS_OPCODE_DDX, this->result, op[0]); 277 break; 278 case ir_unop_dFdy: 279 emit(FS_OPCODE_DDY, this->result, op[0]); 280 break; 281 282 case ir_binop_add: 283 emit(BRW_OPCODE_ADD, this->result, op[0], op[1]); 284 break; 285 case ir_binop_sub: 286 assert(!"not reached: should be handled by ir_sub_to_add_neg"); 287 break; 288 289 case ir_binop_mul: 290 if (ir->type->is_integer()) { 291 /* For integer multiplication, the MUL uses the low 16 bits 292 * of one of the operands (src0 on gen6, src1 on gen7). The 293 * MACH accumulates in the contribution of the upper 16 bits 294 * of that operand. 295 * 296 * FINISHME: Emit just the MUL if we know an operand is small 297 * enough. 298 */ 299 struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_D); 300 301 emit(BRW_OPCODE_MUL, acc, op[0], op[1]); 302 emit(BRW_OPCODE_MACH, reg_null_d, op[0], op[1]); 303 emit(BRW_OPCODE_MOV, this->result, fs_reg(acc)); 304 } else { 305 emit(BRW_OPCODE_MUL, this->result, op[0], op[1]); 306 } 307 break; 308 case ir_binop_div: 309 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */ 310 assert(ir->type->is_integer()); 311 emit_math(SHADER_OPCODE_INT_QUOTIENT, this->result, op[0], op[1]); 312 break; 313 case ir_binop_mod: 314 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */ 315 assert(ir->type->is_integer()); 316 emit_math(SHADER_OPCODE_INT_REMAINDER, this->result, op[0], op[1]); 317 break; 318 319 case ir_binop_less: 320 case ir_binop_greater: 321 case ir_binop_lequal: 322 case ir_binop_gequal: 323 case ir_binop_equal: 324 case ir_binop_all_equal: 325 case ir_binop_nequal: 326 case ir_binop_any_nequal: 327 temp = this->result; 328 /* original gen4 does implicit conversion before comparison. */ 329 if (intel->gen < 5) 330 temp.type = op[0].type; 331 332 resolve_ud_negate(&op[0]); 333 resolve_ud_negate(&op[1]); 334 335 inst = emit(BRW_OPCODE_CMP, temp, op[0], op[1]); 336 inst->conditional_mod = brw_conditional_for_comparison(ir->operation); 337 emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)); 338 break; 339 340 case ir_binop_logic_xor: 341 emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 342 break; 343 344 case ir_binop_logic_or: 345 emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 346 break; 347 348 case ir_binop_logic_and: 349 emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 350 break; 351 352 case ir_binop_dot: 353 case ir_unop_any: 354 assert(!"not reached: should be handled by brw_fs_channel_expressions"); 355 break; 356 357 case ir_unop_noise: 358 assert(!"not reached: should be handled by lower_noise"); 359 break; 360 361 case ir_quadop_vector: 362 assert(!"not reached: should be handled by lower_quadop_vector"); 363 break; 364 365 case ir_unop_sqrt: 366 emit_math(SHADER_OPCODE_SQRT, this->result, op[0]); 367 break; 368 369 case ir_unop_rsq: 370 emit_math(SHADER_OPCODE_RSQ, this->result, op[0]); 371 break; 372 373 case ir_unop_i2u: 374 op[0].type = BRW_REGISTER_TYPE_UD; 375 this->result = op[0]; 376 break; 377 case ir_unop_u2i: 378 op[0].type = BRW_REGISTER_TYPE_D; 379 this->result = op[0]; 380 break; 381 case ir_unop_i2f: 382 case ir_unop_u2f: 383 case ir_unop_b2f: 384 case ir_unop_b2i: 385 case ir_unop_f2i: 386 emit(BRW_OPCODE_MOV, this->result, op[0]); 387 break; 388 case ir_unop_f2b: 389 case ir_unop_i2b: 390 temp = this->result; 391 /* original gen4 does implicit conversion before comparison. */ 392 if (intel->gen < 5) 393 temp.type = op[0].type; 394 395 resolve_ud_negate(&op[0]); 396 397 inst = emit(BRW_OPCODE_CMP, temp, op[0], fs_reg(0.0f)); 398 inst->conditional_mod = BRW_CONDITIONAL_NZ; 399 inst = emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(1)); 400 break; 401 402 case ir_unop_trunc: 403 emit(BRW_OPCODE_RNDZ, this->result, op[0]); 404 break; 405 case ir_unop_ceil: 406 op[0].negate = !op[0].negate; 407 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 408 this->result.negate = true; 409 break; 410 case ir_unop_floor: 411 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); 412 break; 413 case ir_unop_fract: 414 inst = emit(BRW_OPCODE_FRC, this->result, op[0]); 415 break; 416 case ir_unop_round_even: 417 emit(BRW_OPCODE_RNDE, this->result, op[0]); 418 break; 419 420 case ir_binop_min: 421 resolve_ud_negate(&op[0]); 422 resolve_ud_negate(&op[1]); 423 424 if (intel->gen >= 6) { 425 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 426 inst->conditional_mod = BRW_CONDITIONAL_L; 427 } else { 428 /* Unalias the destination */ 429 this->result = fs_reg(this, ir->type); 430 431 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 432 inst->conditional_mod = BRW_CONDITIONAL_L; 433 434 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 435 inst->predicated = true; 436 } 437 break; 438 case ir_binop_max: 439 resolve_ud_negate(&op[0]); 440 resolve_ud_negate(&op[1]); 441 442 if (intel->gen >= 6) { 443 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 444 inst->conditional_mod = BRW_CONDITIONAL_GE; 445 } else { 446 /* Unalias the destination */ 447 this->result = fs_reg(this, ir->type); 448 449 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); 450 inst->conditional_mod = BRW_CONDITIONAL_G; 451 452 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); 453 inst->predicated = true; 454 } 455 break; 456 457 case ir_binop_pow: 458 emit_math(SHADER_OPCODE_POW, this->result, op[0], op[1]); 459 break; 460 461 case ir_unop_bit_not: 462 inst = emit(BRW_OPCODE_NOT, this->result, op[0]); 463 break; 464 case ir_binop_bit_and: 465 inst = emit(BRW_OPCODE_AND, this->result, op[0], op[1]); 466 break; 467 case ir_binop_bit_xor: 468 inst = emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); 469 break; 470 case ir_binop_bit_or: 471 inst = emit(BRW_OPCODE_OR, this->result, op[0], op[1]); 472 break; 473 474 case ir_binop_lshift: 475 inst = emit(BRW_OPCODE_SHL, this->result, op[0], op[1]); 476 break; 477 478 case ir_binop_rshift: 479 if (ir->type->base_type == GLSL_TYPE_INT) 480 inst = emit(BRW_OPCODE_ASR, this->result, op[0], op[1]); 481 else 482 inst = emit(BRW_OPCODE_SHR, this->result, op[0], op[1]); 483 break; 484 } 485} 486 487void 488fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r, 489 const glsl_type *type, bool predicated) 490{ 491 switch (type->base_type) { 492 case GLSL_TYPE_FLOAT: 493 case GLSL_TYPE_UINT: 494 case GLSL_TYPE_INT: 495 case GLSL_TYPE_BOOL: 496 for (unsigned int i = 0; i < type->components(); i++) { 497 l.type = brw_type_for_base_type(type); 498 r.type = brw_type_for_base_type(type); 499 500 if (predicated || !l.equals(&r)) { 501 fs_inst *inst = emit(BRW_OPCODE_MOV, l, r); 502 inst->predicated = predicated; 503 } 504 505 l.reg_offset++; 506 r.reg_offset++; 507 } 508 break; 509 case GLSL_TYPE_ARRAY: 510 for (unsigned int i = 0; i < type->length; i++) { 511 emit_assignment_writes(l, r, type->fields.array, predicated); 512 } 513 break; 514 515 case GLSL_TYPE_STRUCT: 516 for (unsigned int i = 0; i < type->length; i++) { 517 emit_assignment_writes(l, r, type->fields.structure[i].type, 518 predicated); 519 } 520 break; 521 522 case GLSL_TYPE_SAMPLER: 523 break; 524 525 default: 526 assert(!"not reached"); 527 break; 528 } 529} 530 531/* If the RHS processing resulted in an instruction generating a 532 * temporary value, and it would be easy to rewrite the instruction to 533 * generate its result right into the LHS instead, do so. This ends 534 * up reliably removing instructions where it can be tricky to do so 535 * later without real UD chain information. 536 */ 537bool 538fs_visitor::try_rewrite_rhs_to_dst(ir_assignment *ir, 539 fs_reg dst, 540 fs_reg src, 541 fs_inst *pre_rhs_inst, 542 fs_inst *last_rhs_inst) 543{ 544 if (pre_rhs_inst == last_rhs_inst) 545 return false; /* No instructions generated to work with. */ 546 547 /* Only attempt if we're doing a direct assignment. */ 548 if (ir->condition || 549 !(ir->lhs->type->is_scalar() || 550 (ir->lhs->type->is_vector() && 551 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1))) 552 return false; 553 554 /* Make sure the last instruction generated our source reg. */ 555 if (last_rhs_inst->predicated || 556 last_rhs_inst->force_uncompressed || 557 last_rhs_inst->force_sechalf || 558 !src.equals(&last_rhs_inst->dst)) 559 return false; 560 561 /* Success! Rewrite the instruction. */ 562 last_rhs_inst->dst = dst; 563 564 return true; 565} 566 567void 568fs_visitor::visit(ir_assignment *ir) 569{ 570 fs_reg l, r; 571 fs_inst *inst; 572 573 /* FINISHME: arrays on the lhs */ 574 ir->lhs->accept(this); 575 l = this->result; 576 577 fs_inst *pre_rhs_inst = (fs_inst *) this->instructions.get_tail(); 578 579 ir->rhs->accept(this); 580 r = this->result; 581 582 fs_inst *last_rhs_inst = (fs_inst *) this->instructions.get_tail(); 583 584 assert(l.file != BAD_FILE); 585 assert(r.file != BAD_FILE); 586 587 if (try_rewrite_rhs_to_dst(ir, l, r, pre_rhs_inst, last_rhs_inst)) 588 return; 589 590 if (ir->condition) { 591 emit_bool_to_cond_code(ir->condition); 592 } 593 594 if (ir->lhs->type->is_scalar() || 595 ir->lhs->type->is_vector()) { 596 for (int i = 0; i < ir->lhs->type->vector_elements; i++) { 597 if (ir->write_mask & (1 << i)) { 598 inst = emit(BRW_OPCODE_MOV, l, r); 599 if (ir->condition) 600 inst->predicated = true; 601 r.reg_offset++; 602 } 603 l.reg_offset++; 604 } 605 } else { 606 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL); 607 } 608} 609 610fs_inst * 611fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate, 612 int sampler) 613{ 614 int mlen; 615 int base_mrf = 1; 616 bool simd16 = false; 617 fs_reg orig_dst; 618 619 /* g0 header. */ 620 mlen = 1; 621 622 if (ir->shadow_comparitor && ir->op != ir_txd) { 623 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 624 fs_inst *inst = emit(BRW_OPCODE_MOV, 625 fs_reg(MRF, base_mrf + mlen + i), coordinate); 626 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 627 inst->saturate = true; 628 629 coordinate.reg_offset++; 630 } 631 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 632 mlen += 3; 633 634 if (ir->op == ir_tex) { 635 /* There's no plain shadow compare message, so we use shadow 636 * compare with a bias of 0.0. 637 */ 638 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)); 639 mlen++; 640 } else if (ir->op == ir_txb) { 641 ir->lod_info.bias->accept(this); 642 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 643 mlen++; 644 } else { 645 assert(ir->op == ir_txl); 646 ir->lod_info.lod->accept(this); 647 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 648 mlen++; 649 } 650 651 ir->shadow_comparitor->accept(this); 652 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 653 mlen++; 654 } else if (ir->op == ir_tex) { 655 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 656 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), 657 coordinate); 658 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 659 inst->saturate = true; 660 coordinate.reg_offset++; 661 } 662 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 663 mlen += 3; 664 } else if (ir->op == ir_txd) { 665 ir->lod_info.grad.dPdx->accept(this); 666 fs_reg dPdx = this->result; 667 668 ir->lod_info.grad.dPdy->accept(this); 669 fs_reg dPdy = this->result; 670 671 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 672 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); 673 coordinate.reg_offset++; 674 } 675 /* the slots for u and v are always present, but r is optional */ 676 mlen += MAX2(ir->coordinate->type->vector_elements, 2); 677 678 /* P = u, v, r 679 * dPdx = dudx, dvdx, drdx 680 * dPdy = dudy, dvdy, drdy 681 * 682 * 1-arg: Does not exist. 683 * 684 * 2-arg: dudx dvdx dudy dvdy 685 * dPdx.x dPdx.y dPdy.x dPdy.y 686 * m4 m5 m6 m7 687 * 688 * 3-arg: dudx dvdx drdx dudy dvdy drdy 689 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z 690 * m5 m6 m7 m8 m9 m10 691 */ 692 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 693 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 694 dPdx.reg_offset++; 695 } 696 mlen += MAX2(ir->lod_info.grad.dPdx->type->vector_elements, 2); 697 698 for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) { 699 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 700 dPdy.reg_offset++; 701 } 702 mlen += MAX2(ir->lod_info.grad.dPdy->type->vector_elements, 2); 703 } else if (ir->op == ir_txs) { 704 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */ 705 simd16 = true; 706 ir->lod_info.lod->accept(this); 707 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 708 mlen += 2; 709 } else { 710 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod 711 * instructions. We'll need to do SIMD16 here. 712 */ 713 simd16 = true; 714 assert(ir->op == ir_txb || ir->op == ir_txl || ir->op == ir_txf); 715 716 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 717 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, 718 base_mrf + mlen + i * 2, 719 coordinate.type), 720 coordinate); 721 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 722 inst->saturate = true; 723 coordinate.reg_offset++; 724 } 725 726 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to 727 * be necessary for TXF (ld), but seems wise to do for all messages. 728 */ 729 for (int i = ir->coordinate->type->vector_elements; i < 3; i++) { 730 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i * 2), fs_reg(0.0f)); 731 } 732 733 /* lod/bias appears after u/v/r. */ 734 mlen += 6; 735 736 if (ir->op == ir_txb) { 737 ir->lod_info.bias->accept(this); 738 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 739 mlen++; 740 } else { 741 ir->lod_info.lod->accept(this); 742 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, this->result.type), 743 this->result); 744 mlen++; 745 } 746 747 /* The unused upper half. */ 748 mlen++; 749 } 750 751 if (simd16) { 752 /* Now, since we're doing simd16, the return is 2 interleaved 753 * vec4s where the odd-indexed ones are junk. We'll need to move 754 * this weirdness around to the expected layout. 755 */ 756 orig_dst = dst; 757 const glsl_type *vec_type = 758 glsl_type::get_instance(ir->type->base_type, 4, 1); 759 dst = fs_reg(this, glsl_type::get_array_instance(vec_type, 2)); 760 dst.type = intel->is_g4x ? brw_type_for_base_type(ir->type) 761 : BRW_REGISTER_TYPE_F; 762 } 763 764 fs_inst *inst = NULL; 765 switch (ir->op) { 766 case ir_tex: 767 inst = emit(SHADER_OPCODE_TEX, dst); 768 break; 769 case ir_txb: 770 inst = emit(FS_OPCODE_TXB, dst); 771 break; 772 case ir_txl: 773 inst = emit(SHADER_OPCODE_TXL, dst); 774 break; 775 case ir_txd: 776 inst = emit(SHADER_OPCODE_TXD, dst); 777 break; 778 case ir_txs: 779 inst = emit(SHADER_OPCODE_TXS, dst); 780 break; 781 case ir_txf: 782 inst = emit(SHADER_OPCODE_TXF, dst); 783 break; 784 } 785 inst->base_mrf = base_mrf; 786 inst->mlen = mlen; 787 inst->header_present = true; 788 789 if (simd16) { 790 for (int i = 0; i < 4; i++) { 791 emit(BRW_OPCODE_MOV, orig_dst, dst); 792 orig_dst.reg_offset++; 793 dst.reg_offset += 2; 794 } 795 } 796 797 return inst; 798} 799 800/* gen5's sampler has slots for u, v, r, array index, then optional 801 * parameters like shadow comparitor or LOD bias. If optional 802 * parameters aren't present, those base slots are optional and don't 803 * need to be included in the message. 804 * 805 * We don't fill in the unnecessary slots regardless, which may look 806 * surprising in the disassembly. 807 */ 808fs_inst * 809fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate, 810 int sampler) 811{ 812 int mlen = 0; 813 int base_mrf = 2; 814 int reg_width = c->dispatch_width / 8; 815 bool header_present = false; 816 const int vector_elements = 817 ir->coordinate ? ir->coordinate->type->vector_elements : 0; 818 819 if (ir->offset) { 820 /* The offsets set up by the ir_texture visitor are in the 821 * m1 header, so we can't go headerless. 822 */ 823 header_present = true; 824 mlen++; 825 base_mrf--; 826 } 827 828 for (int i = 0; i < vector_elements; i++) { 829 fs_inst *inst = emit(BRW_OPCODE_MOV, 830 fs_reg(MRF, base_mrf + mlen + i * reg_width, 831 coordinate.type), 832 coordinate); 833 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 834 inst->saturate = true; 835 coordinate.reg_offset++; 836 } 837 mlen += vector_elements * reg_width; 838 839 if (ir->shadow_comparitor && ir->op != ir_txd) { 840 mlen = MAX2(mlen, header_present + 4 * reg_width); 841 842 ir->shadow_comparitor->accept(this); 843 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 844 mlen += reg_width; 845 } 846 847 fs_inst *inst = NULL; 848 switch (ir->op) { 849 case ir_tex: 850 inst = emit(SHADER_OPCODE_TEX, dst); 851 break; 852 case ir_txb: 853 ir->lod_info.bias->accept(this); 854 mlen = MAX2(mlen, header_present + 4 * reg_width); 855 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 856 mlen += reg_width; 857 858 inst = emit(FS_OPCODE_TXB, dst); 859 860 break; 861 case ir_txl: 862 ir->lod_info.lod->accept(this); 863 mlen = MAX2(mlen, header_present + 4 * reg_width); 864 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 865 mlen += reg_width; 866 867 inst = emit(SHADER_OPCODE_TXL, dst); 868 break; 869 case ir_txd: { 870 ir->lod_info.grad.dPdx->accept(this); 871 fs_reg dPdx = this->result; 872 873 ir->lod_info.grad.dPdy->accept(this); 874 fs_reg dPdy = this->result; 875 876 mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */ 877 878 /** 879 * P = u, v, r 880 * dPdx = dudx, dvdx, drdx 881 * dPdy = dudy, dvdy, drdy 882 * 883 * Load up these values: 884 * - dudx dudy dvdx dvdy drdx drdy 885 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z 886 */ 887 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) { 888 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 889 dPdx.reg_offset++; 890 mlen += reg_width; 891 892 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 893 dPdy.reg_offset++; 894 mlen += reg_width; 895 } 896 897 inst = emit(SHADER_OPCODE_TXD, dst); 898 break; 899 } 900 case ir_txs: 901 ir->lod_info.lod->accept(this); 902 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 903 mlen += reg_width; 904 inst = emit(SHADER_OPCODE_TXS, dst); 905 break; 906 case ir_txf: 907 mlen = header_present + 4 * reg_width; 908 909 ir->lod_info.lod->accept(this); 910 emit(BRW_OPCODE_MOV, 911 fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), 912 this->result); 913 inst = emit(SHADER_OPCODE_TXF, dst); 914 break; 915 } 916 inst->base_mrf = base_mrf; 917 inst->mlen = mlen; 918 inst->header_present = header_present; 919 920 if (mlen > 11) { 921 fail("Message length >11 disallowed by hardware\n"); 922 } 923 924 return inst; 925} 926 927fs_inst * 928fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate, 929 int sampler) 930{ 931 int mlen = 0; 932 int base_mrf = 2; 933 int reg_width = c->dispatch_width / 8; 934 bool header_present = false; 935 936 if (ir->offset) { 937 /* The offsets set up by the ir_texture visitor are in the 938 * m1 header, so we can't go headerless. 939 */ 940 header_present = true; 941 mlen++; 942 base_mrf--; 943 } 944 945 if (ir->shadow_comparitor && ir->op != ir_txd) { 946 ir->shadow_comparitor->accept(this); 947 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 948 mlen += reg_width; 949 } 950 951 /* Set up the LOD info */ 952 switch (ir->op) { 953 case ir_tex: 954 break; 955 case ir_txb: 956 ir->lod_info.bias->accept(this); 957 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 958 mlen += reg_width; 959 break; 960 case ir_txl: 961 ir->lod_info.lod->accept(this); 962 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); 963 mlen += reg_width; 964 break; 965 case ir_txd: { 966 if (c->dispatch_width == 16) 967 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode."); 968 969 ir->lod_info.grad.dPdx->accept(this); 970 fs_reg dPdx = this->result; 971 972 ir->lod_info.grad.dPdy->accept(this); 973 fs_reg dPdy = this->result; 974 975 /* Load dPdx and the coordinate together: 976 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z 977 */ 978 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 979 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 980 coordinate); 981 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 982 inst->saturate = true; 983 coordinate.reg_offset++; 984 mlen += reg_width; 985 986 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx); 987 dPdx.reg_offset++; 988 mlen += reg_width; 989 990 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy); 991 dPdy.reg_offset++; 992 mlen += reg_width; 993 } 994 break; 995 } 996 case ir_txs: 997 ir->lod_info.lod->accept(this); 998 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result); 999 mlen += reg_width; 1000 break; 1001 case ir_txf: 1002 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */ 1003 emit(BRW_OPCODE_MOV, 1004 fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), coordinate); 1005 coordinate.reg_offset++; 1006 mlen += reg_width; 1007 1008 ir->lod_info.lod->accept(this); 1009 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), this->result); 1010 mlen += reg_width; 1011 1012 for (int i = 1; i < ir->coordinate->type->vector_elements; i++) { 1013 emit(BRW_OPCODE_MOV, 1014 fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), coordinate); 1015 coordinate.reg_offset++; 1016 mlen += reg_width; 1017 } 1018 break; 1019 } 1020 1021 /* Set up the coordinate (except for cases where it was done above) */ 1022 if (ir->op != ir_txd && ir->op != ir_txs && ir->op != ir_txf) { 1023 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { 1024 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 1025 coordinate); 1026 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler)) 1027 inst->saturate = true; 1028 coordinate.reg_offset++; 1029 mlen += reg_width; 1030 } 1031 } 1032 1033 /* Generate the SEND */ 1034 fs_inst *inst = NULL; 1035 switch (ir->op) { 1036 case ir_tex: inst = emit(SHADER_OPCODE_TEX, dst); break; 1037 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break; 1038 case ir_txl: inst = emit(SHADER_OPCODE_TXL, dst); break; 1039 case ir_txd: inst = emit(SHADER_OPCODE_TXD, dst); break; 1040 case ir_txf: inst = emit(SHADER_OPCODE_TXF, dst); break; 1041 case ir_txs: inst = emit(SHADER_OPCODE_TXS, dst); break; 1042 } 1043 inst->base_mrf = base_mrf; 1044 inst->mlen = mlen; 1045 inst->header_present = header_present; 1046 1047 if (mlen > 11) { 1048 fail("Message length >11 disallowed by hardware\n"); 1049 } 1050 1051 return inst; 1052} 1053 1054void 1055fs_visitor::visit(ir_texture *ir) 1056{ 1057 fs_inst *inst = NULL; 1058 1059 int sampler = _mesa_get_sampler_uniform_value(ir->sampler, prog, &fp->Base); 1060 sampler = fp->Base.SamplerUnits[sampler]; 1061 1062 /* Our hardware doesn't have a sample_d_c message, so shadow compares 1063 * for textureGrad/TXD need to be emulated with instructions. 1064 */ 1065 bool hw_compare_supported = ir->op != ir_txd; 1066 if (ir->shadow_comparitor && !hw_compare_supported) { 1067 assert(c->key.compare_funcs[sampler] != GL_NONE); 1068 /* No need to even sample for GL_ALWAYS or GL_NEVER...bail early */ 1069 if (c->key.compare_funcs[sampler] == GL_ALWAYS) 1070 return swizzle_result(ir, fs_reg(1.0f), sampler); 1071 else if (c->key.compare_funcs[sampler] == GL_NEVER) 1072 return swizzle_result(ir, fs_reg(0.0f), sampler); 1073 } 1074 1075 if (ir->coordinate) 1076 ir->coordinate->accept(this); 1077 fs_reg coordinate = this->result; 1078 1079 if (ir->offset != NULL) { 1080 ir_constant *offset = ir->offset->as_constant(); 1081 assert(offset != NULL); 1082 1083 signed char offsets[3]; 1084 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) 1085 offsets[i] = (signed char) offset->value.i[i]; 1086 1087 /* Combine all three offsets into a single unsigned dword: 1088 * 1089 * bits 11:8 - U Offset (X component) 1090 * bits 7:4 - V Offset (Y component) 1091 * bits 3:0 - R Offset (Z component) 1092 */ 1093 unsigned offset_bits = 0; 1094 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) { 1095 const unsigned shift = 4 * (2 - i); 1096 offset_bits |= (offsets[i] << shift) & (0xF << shift); 1097 } 1098 1099 /* Explicitly set up the message header by copying g0 to msg reg m1. */ 1100 emit(BRW_OPCODE_MOV, fs_reg(MRF, 1, BRW_REGISTER_TYPE_UD), 1101 fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD))); 1102 1103 /* Then set the offset bits in DWord 2 of the message header. */ 1104 emit(BRW_OPCODE_MOV, 1105 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 1, 2), 1106 BRW_REGISTER_TYPE_UD)), 1107 fs_reg(brw_imm_uw(offset_bits))); 1108 } 1109 1110 /* Should be lowered by do_lower_texture_projection */ 1111 assert(!ir->projector); 1112 1113 /* The 965 requires the EU to do the normalization of GL rectangle 1114 * texture coordinates. We use the program parameter state 1115 * tracking to get the scaling factor. 1116 */ 1117 if (intel->gen < 6 && 1118 ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) { 1119 struct gl_program_parameter_list *params = c->fp->program.Base.Parameters; 1120 int tokens[STATE_LENGTH] = { 1121 STATE_INTERNAL, 1122 STATE_TEXRECT_SCALE, 1123 sampler, 1124 0, 1125 0 1126 }; 1127 1128 if (c->dispatch_width == 16) { 1129 fail("rectangle scale uniform setup not supported on 16-wide\n"); 1130 this->result = fs_reg(this, ir->type); 1131 return; 1132 } 1133 1134 c->prog_data.param_convert[c->prog_data.nr_params] = 1135 PARAM_NO_CONVERT; 1136 c->prog_data.param_convert[c->prog_data.nr_params + 1] = 1137 PARAM_NO_CONVERT; 1138 1139 fs_reg scale_x = fs_reg(UNIFORM, c->prog_data.nr_params); 1140 fs_reg scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1); 1141 GLuint index = _mesa_add_state_reference(params, 1142 (gl_state_index *)tokens); 1143 1144 this->param_index[c->prog_data.nr_params] = index; 1145 this->param_offset[c->prog_data.nr_params] = 0; 1146 c->prog_data.nr_params++; 1147 this->param_index[c->prog_data.nr_params] = index; 1148 this->param_offset[c->prog_data.nr_params] = 1; 1149 c->prog_data.nr_params++; 1150 1151 fs_reg dst = fs_reg(this, ir->coordinate->type); 1152 fs_reg src = coordinate; 1153 coordinate = dst; 1154 1155 emit(BRW_OPCODE_MUL, dst, src, scale_x); 1156 dst.reg_offset++; 1157 src.reg_offset++; 1158 emit(BRW_OPCODE_MUL, dst, src, scale_y); 1159 } 1160 1161 /* Writemasking doesn't eliminate channels on SIMD8 texture 1162 * samples, so don't worry about them. 1163 */ 1164 fs_reg dst = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 4, 1)); 1165 1166 if (intel->gen >= 7) { 1167 inst = emit_texture_gen7(ir, dst, coordinate, sampler); 1168 } else if (intel->gen >= 5) { 1169 inst = emit_texture_gen5(ir, dst, coordinate, sampler); 1170 } else { 1171 inst = emit_texture_gen4(ir, dst, coordinate, sampler); 1172 } 1173 1174 /* If there's an offset, we already set up m1. To avoid the implied move, 1175 * use the null register. Otherwise, we want an implied move from g0. 1176 */ 1177 if (ir->offset != NULL || !inst->header_present) 1178 inst->src[0] = reg_undef; 1179 else 1180 inst->src[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW)); 1181 1182 inst->sampler = sampler; 1183 1184 if (ir->shadow_comparitor) { 1185 if (hw_compare_supported) { 1186 inst->shadow_compare = true; 1187 } else { 1188 ir->shadow_comparitor->accept(this); 1189 fs_reg ref = this->result; 1190 1191 fs_reg value = dst; 1192 dst = fs_reg(this, glsl_type::vec4_type); 1193 1194 /* FINISHME: This needs to be done pre-filtering. */ 1195 1196 uint32_t conditional = 0; 1197 switch (c->key.compare_funcs[sampler]) { 1198 /* GL_ALWAYS and GL_NEVER were handled at the top of the function */ 1199 case GL_LESS: conditional = BRW_CONDITIONAL_L; break; 1200 case GL_GREATER: conditional = BRW_CONDITIONAL_G; break; 1201 case GL_LEQUAL: conditional = BRW_CONDITIONAL_LE; break; 1202 case GL_GEQUAL: conditional = BRW_CONDITIONAL_GE; break; 1203 case GL_EQUAL: conditional = BRW_CONDITIONAL_EQ; break; 1204 case GL_NOTEQUAL: conditional = BRW_CONDITIONAL_NEQ; break; 1205 default: assert(!"Should not get here: bad shadow compare function"); 1206 } 1207 1208 /* Use conditional moves to load 0 or 1 as the result */ 1209 this->current_annotation = "manual shadow comparison"; 1210 for (int i = 0; i < 4; i++) { 1211 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(0.0f)); 1212 1213 inst = emit(BRW_OPCODE_CMP, reg_null_f, ref, value); 1214 inst->conditional_mod = conditional; 1215 1216 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(1.0f)); 1217 inst->predicated = true; 1218 1219 dst.reg_offset++; 1220 value.reg_offset++; 1221 } 1222 dst.reg_offset = 0; 1223 } 1224 } 1225 1226 swizzle_result(ir, dst, sampler); 1227} 1228 1229/** 1230 * Swizzle the result of a texture result. This is necessary for 1231 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons. 1232 */ 1233void 1234fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler) 1235{ 1236 this->result = orig_val; 1237 1238 if (ir->op == ir_txs) 1239 return; 1240 1241 if (ir->type == glsl_type::float_type) { 1242 /* Ignore DEPTH_TEXTURE_MODE swizzling. */ 1243 assert(ir->sampler->type->sampler_shadow); 1244 } else if (c->key.tex_swizzles[sampler] != SWIZZLE_NOOP) { 1245 fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type); 1246 1247 for (int i = 0; i < 4; i++) { 1248 int swiz = GET_SWZ(c->key.tex_swizzles[sampler], i); 1249 fs_reg l = swizzled_result; 1250 l.reg_offset += i; 1251 1252 if (swiz == SWIZZLE_ZERO) { 1253 emit(BRW_OPCODE_MOV, l, fs_reg(0.0f)); 1254 } else if (swiz == SWIZZLE_ONE) { 1255 emit(BRW_OPCODE_MOV, l, fs_reg(1.0f)); 1256 } else { 1257 fs_reg r = orig_val; 1258 r.reg_offset += GET_SWZ(c->key.tex_swizzles[sampler], i); 1259 emit(BRW_OPCODE_MOV, l, r); 1260 } 1261 } 1262 this->result = swizzled_result; 1263 } 1264} 1265 1266void 1267fs_visitor::visit(ir_swizzle *ir) 1268{ 1269 ir->val->accept(this); 1270 fs_reg val = this->result; 1271 1272 if (ir->type->vector_elements == 1) { 1273 this->result.reg_offset += ir->mask.x; 1274 return; 1275 } 1276 1277 fs_reg result = fs_reg(this, ir->type); 1278 this->result = result; 1279 1280 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 1281 fs_reg channel = val; 1282 int swiz = 0; 1283 1284 switch (i) { 1285 case 0: 1286 swiz = ir->mask.x; 1287 break; 1288 case 1: 1289 swiz = ir->mask.y; 1290 break; 1291 case 2: 1292 swiz = ir->mask.z; 1293 break; 1294 case 3: 1295 swiz = ir->mask.w; 1296 break; 1297 } 1298 1299 channel.reg_offset += swiz; 1300 emit(BRW_OPCODE_MOV, result, channel); 1301 result.reg_offset++; 1302 } 1303} 1304 1305void 1306fs_visitor::visit(ir_discard *ir) 1307{ 1308 assert(ir->condition == NULL); /* FINISHME */ 1309 1310 emit(FS_OPCODE_DISCARD); 1311 kill_emitted = true; 1312} 1313 1314void 1315fs_visitor::visit(ir_constant *ir) 1316{ 1317 /* Set this->result to reg at the bottom of the function because some code 1318 * paths will cause this visitor to be applied to other fields. This will 1319 * cause the value stored in this->result to be modified. 1320 * 1321 * Make reg constant so that it doesn't get accidentally modified along the 1322 * way. Yes, I actually had this problem. :( 1323 */ 1324 const fs_reg reg(this, ir->type); 1325 fs_reg dst_reg = reg; 1326 1327 if (ir->type->is_array()) { 1328 const unsigned size = type_size(ir->type->fields.array); 1329 1330 for (unsigned i = 0; i < ir->type->length; i++) { 1331 ir->array_elements[i]->accept(this); 1332 fs_reg src_reg = this->result; 1333 1334 dst_reg.type = src_reg.type; 1335 for (unsigned j = 0; j < size; j++) { 1336 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1337 src_reg.reg_offset++; 1338 dst_reg.reg_offset++; 1339 } 1340 } 1341 } else if (ir->type->is_record()) { 1342 foreach_list(node, &ir->components) { 1343 ir_instruction *const field = (ir_instruction *) node; 1344 const unsigned size = type_size(field->type); 1345 1346 field->accept(this); 1347 fs_reg src_reg = this->result; 1348 1349 dst_reg.type = src_reg.type; 1350 for (unsigned j = 0; j < size; j++) { 1351 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1352 src_reg.reg_offset++; 1353 dst_reg.reg_offset++; 1354 } 1355 } 1356 } else { 1357 const unsigned size = type_size(ir->type); 1358 1359 for (unsigned i = 0; i < size; i++) { 1360 switch (ir->type->base_type) { 1361 case GLSL_TYPE_FLOAT: 1362 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i])); 1363 break; 1364 case GLSL_TYPE_UINT: 1365 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i])); 1366 break; 1367 case GLSL_TYPE_INT: 1368 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.i[i])); 1369 break; 1370 case GLSL_TYPE_BOOL: 1371 emit(BRW_OPCODE_MOV, dst_reg, fs_reg((int)ir->value.b[i])); 1372 break; 1373 default: 1374 assert(!"Non-float/uint/int/bool constant"); 1375 } 1376 dst_reg.reg_offset++; 1377 } 1378 } 1379 1380 this->result = reg; 1381} 1382 1383void 1384fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir) 1385{ 1386 ir_expression *expr = ir->as_expression(); 1387 1388 if (expr) { 1389 fs_reg op[2]; 1390 fs_inst *inst; 1391 1392 assert(expr->get_num_operands() <= 2); 1393 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1394 assert(expr->operands[i]->type->is_scalar()); 1395 1396 expr->operands[i]->accept(this); 1397 op[i] = this->result; 1398 1399 resolve_ud_negate(&op[i]); 1400 } 1401 1402 switch (expr->operation) { 1403 case ir_unop_logic_not: 1404 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1)); 1405 inst->conditional_mod = BRW_CONDITIONAL_Z; 1406 break; 1407 1408 case ir_binop_logic_xor: 1409 inst = emit(BRW_OPCODE_XOR, reg_null_d, op[0], op[1]); 1410 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1411 break; 1412 1413 case ir_binop_logic_or: 1414 inst = emit(BRW_OPCODE_OR, reg_null_d, op[0], op[1]); 1415 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1416 break; 1417 1418 case ir_binop_logic_and: 1419 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], op[1]); 1420 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1421 break; 1422 1423 case ir_unop_f2b: 1424 if (intel->gen >= 6) { 1425 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0.0f)); 1426 } else { 1427 inst = emit(BRW_OPCODE_MOV, reg_null_f, op[0]); 1428 } 1429 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1430 break; 1431 1432 case ir_unop_i2b: 1433 if (intel->gen >= 6) { 1434 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0)); 1435 } else { 1436 inst = emit(BRW_OPCODE_MOV, reg_null_d, op[0]); 1437 } 1438 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1439 break; 1440 1441 case ir_binop_greater: 1442 case ir_binop_gequal: 1443 case ir_binop_less: 1444 case ir_binop_lequal: 1445 case ir_binop_equal: 1446 case ir_binop_all_equal: 1447 case ir_binop_nequal: 1448 case ir_binop_any_nequal: 1449 inst = emit(BRW_OPCODE_CMP, reg_null_cmp, op[0], op[1]); 1450 inst->conditional_mod = 1451 brw_conditional_for_comparison(expr->operation); 1452 break; 1453 1454 default: 1455 assert(!"not reached"); 1456 fail("bad cond code\n"); 1457 break; 1458 } 1459 return; 1460 } 1461 1462 ir->accept(this); 1463 1464 if (intel->gen >= 6) { 1465 fs_inst *inst = emit(BRW_OPCODE_AND, reg_null_d, this->result, fs_reg(1)); 1466 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1467 } else { 1468 fs_inst *inst = emit(BRW_OPCODE_MOV, reg_null_d, this->result); 1469 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1470 } 1471} 1472 1473/** 1474 * Emit a gen6 IF statement with the comparison folded into the IF 1475 * instruction. 1476 */ 1477void 1478fs_visitor::emit_if_gen6(ir_if *ir) 1479{ 1480 ir_expression *expr = ir->condition->as_expression(); 1481 1482 if (expr) { 1483 fs_reg op[2]; 1484 fs_inst *inst; 1485 fs_reg temp; 1486 1487 assert(expr->get_num_operands() <= 2); 1488 for (unsigned int i = 0; i < expr->get_num_operands(); i++) { 1489 assert(expr->operands[i]->type->is_scalar()); 1490 1491 expr->operands[i]->accept(this); 1492 op[i] = this->result; 1493 } 1494 1495 switch (expr->operation) { 1496 case ir_unop_logic_not: 1497 inst = emit(BRW_OPCODE_IF, temp, op[0], fs_reg(0)); 1498 inst->conditional_mod = BRW_CONDITIONAL_Z; 1499 return; 1500 1501 case ir_binop_logic_xor: 1502 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1503 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1504 return; 1505 1506 case ir_binop_logic_or: 1507 temp = fs_reg(this, glsl_type::bool_type); 1508 emit(BRW_OPCODE_OR, temp, op[0], op[1]); 1509 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1510 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1511 return; 1512 1513 case ir_binop_logic_and: 1514 temp = fs_reg(this, glsl_type::bool_type); 1515 emit(BRW_OPCODE_AND, temp, op[0], op[1]); 1516 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); 1517 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1518 return; 1519 1520 case ir_unop_f2b: 1521 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0)); 1522 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1523 return; 1524 1525 case ir_unop_i2b: 1526 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1527 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1528 return; 1529 1530 case ir_binop_greater: 1531 case ir_binop_gequal: 1532 case ir_binop_less: 1533 case ir_binop_lequal: 1534 case ir_binop_equal: 1535 case ir_binop_all_equal: 1536 case ir_binop_nequal: 1537 case ir_binop_any_nequal: 1538 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); 1539 inst->conditional_mod = 1540 brw_conditional_for_comparison(expr->operation); 1541 return; 1542 default: 1543 assert(!"not reached"); 1544 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); 1545 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1546 fail("bad condition\n"); 1547 return; 1548 } 1549 return; 1550 } 1551 1552 ir->condition->accept(this); 1553 1554 fs_inst *inst = emit(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0)); 1555 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1556} 1557 1558void 1559fs_visitor::visit(ir_if *ir) 1560{ 1561 fs_inst *inst; 1562 1563 if (intel->gen < 6 && c->dispatch_width == 16) { 1564 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1565 } 1566 1567 /* Don't point the annotation at the if statement, because then it plus 1568 * the then and else blocks get printed. 1569 */ 1570 this->base_ir = ir->condition; 1571 1572 if (intel->gen == 6) { 1573 emit_if_gen6(ir); 1574 } else { 1575 emit_bool_to_cond_code(ir->condition); 1576 1577 inst = emit(BRW_OPCODE_IF); 1578 inst->predicated = true; 1579 } 1580 1581 foreach_list(node, &ir->then_instructions) { 1582 ir_instruction *ir = (ir_instruction *)node; 1583 this->base_ir = ir; 1584 1585 ir->accept(this); 1586 } 1587 1588 if (!ir->else_instructions.is_empty()) { 1589 emit(BRW_OPCODE_ELSE); 1590 1591 foreach_list(node, &ir->else_instructions) { 1592 ir_instruction *ir = (ir_instruction *)node; 1593 this->base_ir = ir; 1594 1595 ir->accept(this); 1596 } 1597 } 1598 1599 emit(BRW_OPCODE_ENDIF); 1600} 1601 1602void 1603fs_visitor::visit(ir_loop *ir) 1604{ 1605 fs_reg counter = reg_undef; 1606 1607 if (c->dispatch_width == 16) { 1608 fail("Can't support (non-uniform) control flow on 16-wide\n"); 1609 } 1610 1611 if (ir->counter) { 1612 this->base_ir = ir->counter; 1613 ir->counter->accept(this); 1614 counter = *(variable_storage(ir->counter)); 1615 1616 if (ir->from) { 1617 this->base_ir = ir->from; 1618 ir->from->accept(this); 1619 1620 emit(BRW_OPCODE_MOV, counter, this->result); 1621 } 1622 } 1623 1624 emit(BRW_OPCODE_DO); 1625 1626 if (ir->to) { 1627 this->base_ir = ir->to; 1628 ir->to->accept(this); 1629 1630 fs_inst *inst = emit(BRW_OPCODE_CMP, reg_null_cmp, counter, this->result); 1631 inst->conditional_mod = brw_conditional_for_comparison(ir->cmp); 1632 1633 inst = emit(BRW_OPCODE_BREAK); 1634 inst->predicated = true; 1635 } 1636 1637 foreach_list(node, &ir->body_instructions) { 1638 ir_instruction *ir = (ir_instruction *)node; 1639 1640 this->base_ir = ir; 1641 ir->accept(this); 1642 } 1643 1644 if (ir->increment) { 1645 this->base_ir = ir->increment; 1646 ir->increment->accept(this); 1647 emit(BRW_OPCODE_ADD, counter, counter, this->result); 1648 } 1649 1650 emit(BRW_OPCODE_WHILE); 1651} 1652 1653void 1654fs_visitor::visit(ir_loop_jump *ir) 1655{ 1656 switch (ir->mode) { 1657 case ir_loop_jump::jump_break: 1658 emit(BRW_OPCODE_BREAK); 1659 break; 1660 case ir_loop_jump::jump_continue: 1661 emit(BRW_OPCODE_CONTINUE); 1662 break; 1663 } 1664} 1665 1666void 1667fs_visitor::visit(ir_call *ir) 1668{ 1669 assert(!"FINISHME"); 1670} 1671 1672void 1673fs_visitor::visit(ir_return *ir) 1674{ 1675 assert(!"FINISHME"); 1676} 1677 1678void 1679fs_visitor::visit(ir_function *ir) 1680{ 1681 /* Ignore function bodies other than main() -- we shouldn't see calls to 1682 * them since they should all be inlined before we get to ir_to_mesa. 1683 */ 1684 if (strcmp(ir->name, "main") == 0) { 1685 const ir_function_signature *sig; 1686 exec_list empty; 1687 1688 sig = ir->matching_signature(&empty); 1689 1690 assert(sig); 1691 1692 foreach_list(node, &sig->body) { 1693 ir_instruction *ir = (ir_instruction *)node; 1694 this->base_ir = ir; 1695 1696 ir->accept(this); 1697 } 1698 } 1699} 1700 1701void 1702fs_visitor::visit(ir_function_signature *ir) 1703{ 1704 assert(!"not reached"); 1705 (void)ir; 1706} 1707 1708fs_inst * 1709fs_visitor::emit(fs_inst inst) 1710{ 1711 fs_inst *list_inst = new(mem_ctx) fs_inst; 1712 *list_inst = inst; 1713 1714 if (force_uncompressed_stack > 0) 1715 list_inst->force_uncompressed = true; 1716 else if (force_sechalf_stack > 0) 1717 list_inst->force_sechalf = true; 1718 1719 list_inst->annotation = this->current_annotation; 1720 list_inst->ir = this->base_ir; 1721 1722 this->instructions.push_tail(list_inst); 1723 1724 return list_inst; 1725} 1726 1727/** Emits a dummy fragment shader consisting of magenta for bringup purposes. */ 1728void 1729fs_visitor::emit_dummy_fs() 1730{ 1731 /* Everyone's favorite color. */ 1732 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2), fs_reg(1.0f)); 1733 emit(BRW_OPCODE_MOV, fs_reg(MRF, 3), fs_reg(0.0f)); 1734 emit(BRW_OPCODE_MOV, fs_reg(MRF, 4), fs_reg(1.0f)); 1735 emit(BRW_OPCODE_MOV, fs_reg(MRF, 5), fs_reg(0.0f)); 1736 1737 fs_inst *write; 1738 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0)); 1739 write->base_mrf = 2; 1740} 1741 1742/* The register location here is relative to the start of the URB 1743 * data. It will get adjusted to be a real location before 1744 * generate_code() time. 1745 */ 1746struct brw_reg 1747fs_visitor::interp_reg(int location, int channel) 1748{ 1749 int regnr = urb_setup[location] * 2 + channel / 2; 1750 int stride = (channel & 1) * 4; 1751 1752 assert(urb_setup[location] != -1); 1753 1754 return brw_vec1_grf(regnr, stride); 1755} 1756 1757/** Emits the interpolation for the varying inputs. */ 1758void 1759fs_visitor::emit_interpolation_setup_gen4() 1760{ 1761 this->current_annotation = "compute pixel centers"; 1762 this->pixel_x = fs_reg(this, glsl_type::uint_type); 1763 this->pixel_y = fs_reg(this, glsl_type::uint_type); 1764 this->pixel_x.type = BRW_REGISTER_TYPE_UW; 1765 this->pixel_y.type = BRW_REGISTER_TYPE_UW; 1766 1767 emit(FS_OPCODE_PIXEL_X, this->pixel_x); 1768 emit(FS_OPCODE_PIXEL_Y, this->pixel_y); 1769 1770 this->current_annotation = "compute pixel deltas from v0"; 1771 if (brw->has_pln) { 1772 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] = 1773 fs_reg(this, glsl_type::vec2_type); 1774 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] = 1775 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC]; 1776 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].reg_offset++; 1777 } else { 1778 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] = 1779 fs_reg(this, glsl_type::float_type); 1780 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] = 1781 fs_reg(this, glsl_type::float_type); 1782 } 1783 emit(BRW_OPCODE_ADD, this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC], 1784 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))); 1785 emit(BRW_OPCODE_ADD, this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC], 1786 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))); 1787 1788 this->current_annotation = "compute pos.w and 1/pos.w"; 1789 /* Compute wpos.w. It's always in our setup, since it's needed to 1790 * interpolate the other attributes. 1791 */ 1792 this->wpos_w = fs_reg(this, glsl_type::float_type); 1793 emit(FS_OPCODE_LINTERP, wpos_w, 1794 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC], 1795 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC], 1796 interp_reg(FRAG_ATTRIB_WPOS, 3)); 1797 /* Compute the pixel 1/W value from wpos.w. */ 1798 this->pixel_w = fs_reg(this, glsl_type::float_type); 1799 emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w); 1800 this->current_annotation = NULL; 1801} 1802 1803/** Emits the interpolation for the varying inputs. */ 1804void 1805fs_visitor::emit_interpolation_setup_gen6() 1806{ 1807 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); 1808 1809 /* If the pixel centers end up used, the setup is the same as for gen4. */ 1810 this->current_annotation = "compute pixel centers"; 1811 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type); 1812 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type); 1813 int_pixel_x.type = BRW_REGISTER_TYPE_UW; 1814 int_pixel_y.type = BRW_REGISTER_TYPE_UW; 1815 emit(BRW_OPCODE_ADD, 1816 int_pixel_x, 1817 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), 1818 fs_reg(brw_imm_v(0x10101010))); 1819 emit(BRW_OPCODE_ADD, 1820 int_pixel_y, 1821 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), 1822 fs_reg(brw_imm_v(0x11001100))); 1823 1824 /* As of gen6, we can no longer mix float and int sources. We have 1825 * to turn the integer pixel centers into floats for their actual 1826 * use. 1827 */ 1828 this->pixel_x = fs_reg(this, glsl_type::float_type); 1829 this->pixel_y = fs_reg(this, glsl_type::float_type); 1830 emit(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x); 1831 emit(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y); 1832 1833 this->current_annotation = "compute pos.w"; 1834 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0)); 1835 this->wpos_w = fs_reg(this, glsl_type::float_type); 1836 emit_math(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w); 1837 1838 for (int i = 0; i < BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT; ++i) { 1839 uint8_t reg = c->barycentric_coord_reg[i]; 1840 this->delta_x[i] = fs_reg(brw_vec8_grf(reg, 0)); 1841 this->delta_y[i] = fs_reg(brw_vec8_grf(reg + 1, 0)); 1842 } 1843 1844 this->current_annotation = NULL; 1845} 1846 1847void 1848fs_visitor::emit_color_write(int target, int index, int first_color_mrf) 1849{ 1850 int reg_width = c->dispatch_width / 8; 1851 fs_inst *inst; 1852 fs_reg color = outputs[target]; 1853 fs_reg mrf; 1854 1855 /* If there's no color data to be written, skip it. */ 1856 if (color.file == BAD_FILE) 1857 return; 1858 1859 color.reg_offset += index; 1860 1861 if (c->dispatch_width == 8 || intel->gen >= 6) { 1862 /* SIMD8 write looks like: 1863 * m + 0: r0 1864 * m + 1: r1 1865 * m + 2: g0 1866 * m + 3: g1 1867 * 1868 * gen6 SIMD16 DP write looks like: 1869 * m + 0: r0 1870 * m + 1: r1 1871 * m + 2: g0 1872 * m + 3: g1 1873 * m + 4: b0 1874 * m + 5: b1 1875 * m + 6: a0 1876 * m + 7: a1 1877 */ 1878 inst = emit(BRW_OPCODE_MOV, 1879 fs_reg(MRF, first_color_mrf + index * reg_width, color.type), 1880 color); 1881 inst->saturate = c->key.clamp_fragment_color; 1882 } else { 1883 /* pre-gen6 SIMD16 single source DP write looks like: 1884 * m + 0: r0 1885 * m + 1: g0 1886 * m + 2: b0 1887 * m + 3: a0 1888 * m + 4: r1 1889 * m + 5: g1 1890 * m + 6: b1 1891 * m + 7: a1 1892 */ 1893 if (brw->has_compr4) { 1894 /* By setting the high bit of the MRF register number, we 1895 * indicate that we want COMPR4 mode - instead of doing the 1896 * usual destination + 1 for the second half we get 1897 * destination + 4. 1898 */ 1899 inst = emit(BRW_OPCODE_MOV, 1900 fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index, 1901 color.type), 1902 color); 1903 inst->saturate = c->key.clamp_fragment_color; 1904 } else { 1905 push_force_uncompressed(); 1906 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index, 1907 color.type), 1908 color); 1909 inst->saturate = c->key.clamp_fragment_color; 1910 pop_force_uncompressed(); 1911 1912 push_force_sechalf(); 1913 color.sechalf = true; 1914 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index + 4, 1915 color.type), 1916 color); 1917 inst->saturate = c->key.clamp_fragment_color; 1918 pop_force_sechalf(); 1919 color.sechalf = false; 1920 } 1921 } 1922} 1923 1924void 1925fs_visitor::emit_fb_writes() 1926{ 1927 this->current_annotation = "FB write header"; 1928 bool header_present = true; 1929 int base_mrf = 2; 1930 int nr = base_mrf; 1931 int reg_width = c->dispatch_width / 8; 1932 1933 if (intel->gen >= 6 && 1934 !this->kill_emitted && 1935 c->key.nr_color_regions == 1) { 1936 header_present = false; 1937 } 1938 1939 if (header_present) { 1940 /* m2, m3 header */ 1941 nr += 2; 1942 } 1943 1944 if (c->aa_dest_stencil_reg) { 1945 push_force_uncompressed(); 1946 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++), 1947 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))); 1948 pop_force_uncompressed(); 1949 } 1950 1951 /* Reserve space for color. It'll be filled in per MRT below. */ 1952 int color_mrf = nr; 1953 nr += 4 * reg_width; 1954 1955 if (c->source_depth_to_render_target) { 1956 if (intel->gen == 6 && c->dispatch_width == 16) { 1957 /* For outputting oDepth on gen6, SIMD8 writes have to be 1958 * used. This would require 8-wide moves of each half to 1959 * message regs, kind of like pre-gen5 SIMD16 FB writes. 1960 * Just bail on doing so for now. 1961 */ 1962 fail("Missing support for simd16 depth writes on gen6\n"); 1963 } 1964 1965 if (c->computes_depth) { 1966 /* Hand over gl_FragDepth. */ 1967 assert(this->frag_depth); 1968 fs_reg depth = *(variable_storage(this->frag_depth)); 1969 1970 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), depth); 1971 } else { 1972 /* Pass through the payload depth. */ 1973 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1974 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))); 1975 } 1976 nr += reg_width; 1977 } 1978 1979 if (c->dest_depth_reg) { 1980 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), 1981 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))); 1982 nr += reg_width; 1983 } 1984 1985 for (int target = 0; target < c->key.nr_color_regions; target++) { 1986 this->current_annotation = ralloc_asprintf(this->mem_ctx, 1987 "FB write target %d", 1988 target); 1989 for (int i = 0; i < 4; i++) 1990 emit_color_write(target, i, color_mrf); 1991 1992 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 1993 inst->target = target; 1994 inst->base_mrf = base_mrf; 1995 inst->mlen = nr - base_mrf; 1996 if (target == c->key.nr_color_regions - 1) 1997 inst->eot = true; 1998 inst->header_present = header_present; 1999 } 2000 2001 if (c->key.nr_color_regions == 0) { 2002 if (c->key.alpha_test) { 2003 /* If the alpha test is enabled but there's no color buffer, 2004 * we still need to send alpha out the pipeline to our null 2005 * renderbuffer. 2006 */ 2007 emit_color_write(0, 3, color_mrf); 2008 } 2009 2010 fs_inst *inst = emit(FS_OPCODE_FB_WRITE); 2011 inst->base_mrf = base_mrf; 2012 inst->mlen = nr - base_mrf; 2013 inst->eot = true; 2014 inst->header_present = header_present; 2015 } 2016 2017 this->current_annotation = NULL; 2018} 2019 2020void 2021fs_visitor::resolve_ud_negate(fs_reg *reg) 2022{ 2023 if (reg->type != BRW_REGISTER_TYPE_UD || 2024 !reg->negate) 2025 return; 2026 2027 fs_reg temp = fs_reg(this, glsl_type::uint_type); 2028 emit(BRW_OPCODE_MOV, temp, *reg); 2029 *reg = temp; 2030} 2031