brw_state_upload.c revision 25d2bf3845e9a6faaef8d808c1255ec57dc71dba 
1/*
2 Copyright (C) Intel Corp.  2006.  All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28  * Authors:
29  *   Keith Whitwell <keith@tungstengraphics.com>
30  */
31
32
33
34#include "brw_context.h"
35#include "brw_state.h"
36#include "intel_batchbuffer.h"
37#include "intel_buffers.h"
38
39/* This is used to initialize brw->state.atoms[].  We could use this
40 * list directly except for a single atom, brw_constant_buffer, which
41 * has a .dirty value which changes according to the parameters of the
42 * current fragment and vertex programs, and so cannot be a static
43 * value.
44 */
45static const struct brw_tracked_state *gen4_atoms[] =
46{
47   &brw_check_fallback,
48
49   &brw_wm_input_sizes,
50   &brw_vs_prog, /* must do before GS prog, state base address. */
51   &brw_gs_prog, /* must do before state base address */
52   &brw_clip_prog, /* must do before state base address */
53   &brw_sf_prog, /* must do before state base address */
54   &brw_wm_prog, /* must do before state base address */
55
56   /* Once all the programs are done, we know how large urb entry
57    * sizes need to be and can decide if we need to change the urb
58    * layout.
59    */
60   &brw_curbe_offsets,
61   &brw_recalculate_urb_fence,
62
63   &brw_cc_vp,
64   &brw_cc_unit,
65
66   /* Surface state setup.  Must come before the VS/WM unit.  The binding
67    * table upload must be last.
68    */
69   &brw_vs_pull_constants,
70   &brw_wm_pull_constants,
71   &brw_renderbuffer_surfaces,
72   &brw_texture_surfaces,
73   &brw_vs_binding_table,
74   &brw_wm_binding_table,
75
76   &brw_samplers,
77
78   /* These set up state for brw_psp_urb_cbs */
79   &brw_wm_unit,
80   &brw_sf_vp,
81   &brw_sf_unit,
82   &brw_vs_unit,		/* always required, enabled or not */
83   &brw_clip_unit,
84   &brw_gs_unit,
85
86   /* Command packets:
87    */
88   &brw_invariant_state,
89   &brw_state_base_address,
90
91   &brw_binding_table_pointers,
92   &brw_blend_constant_color,
93
94   &brw_depthbuffer,
95
96   &brw_polygon_stipple,
97   &brw_polygon_stipple_offset,
98
99   &brw_line_stipple,
100   &brw_aa_line_parameters,
101
102   &brw_psp_urb_cbs,
103
104   &brw_drawing_rect,
105   &brw_indices,
106   &brw_index_buffer,
107   &brw_vertices,
108
109   &brw_constant_buffer
110};
111
112static const struct brw_tracked_state *gen6_atoms[] =
113{
114   &brw_check_fallback,
115
116   &brw_wm_input_sizes,
117   &brw_vs_prog, /* must do before state base address */
118   &brw_gs_prog, /* must do before state base address */
119   &brw_wm_prog, /* must do before state base address */
120
121   &gen6_clip_vp,
122   &gen6_sf_vp,
123
124   /* Command packets: */
125   &brw_invariant_state,
126
127   /* must do before binding table pointers, cc state ptrs */
128   &brw_state_base_address,
129
130   &brw_cc_vp,
131   &gen6_viewport_state,	/* must do after *_vp stages */
132
133   &gen6_urb,
134   &gen6_blend_state,		/* must do before cc unit */
135   &gen6_color_calc_state,	/* must do before cc unit */
136   &gen6_depth_stencil_state,	/* must do before cc unit */
137   &gen6_cc_state_pointers,
138
139   &gen6_vs_push_constants, /* Before vs_state */
140   &gen6_wm_push_constants, /* Before wm_state */
141
142   /* Surface state setup.  Must come before the VS/WM unit.  The binding
143    * table upload must be last.
144    */
145   &brw_vs_pull_constants,
146   &brw_vs_ubo_surfaces,
147   &brw_wm_pull_constants,
148   &brw_wm_ubo_surfaces,
149   &gen6_renderbuffer_surfaces,
150   &brw_texture_surfaces,
151   &gen6_sol_surface,
152   &brw_vs_binding_table,
153   &gen6_gs_binding_table,
154   &brw_wm_binding_table,
155
156   &brw_samplers,
157   &gen6_sampler_state,
158   &gen6_multisample_state,
159
160   &gen6_vs_state,
161   &gen6_gs_state,
162   &gen6_clip_state,
163   &gen6_sf_state,
164   &gen6_wm_state,
165
166   &gen6_scissor_state,
167
168   &gen6_binding_table_pointers,
169
170   &brw_depthbuffer,
171
172   &brw_polygon_stipple,
173   &brw_polygon_stipple_offset,
174
175   &brw_line_stipple,
176   &brw_aa_line_parameters,
177
178   &brw_drawing_rect,
179
180   &gen6_sol_indices,
181   &brw_indices,
182   &brw_index_buffer,
183   &brw_vertices,
184};
185
186const struct brw_tracked_state *gen7_atoms[] =
187{
188   &brw_check_fallback,
189
190   &brw_wm_input_sizes,
191   &brw_vs_prog,
192   &brw_wm_prog,
193
194   /* Command packets: */
195   &brw_invariant_state,
196   &gen7_push_constant_alloc,
197
198   /* must do before binding table pointers, cc state ptrs */
199   &brw_state_base_address,
200
201   &brw_cc_vp,
202   &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
203   &gen7_sf_clip_viewport,
204
205   &gen7_urb,
206   &gen6_blend_state,		/* must do before cc unit */
207   &gen6_color_calc_state,	/* must do before cc unit */
208   &gen6_depth_stencil_state,	/* must do before cc unit */
209   &gen7_blend_state_pointer,
210   &gen7_cc_state_pointer,
211   &gen7_depth_stencil_state_pointer,
212
213   &gen6_vs_push_constants, /* Before vs_state */
214   &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
215
216   /* Surface state setup.  Must come before the VS/WM unit.  The binding
217    * table upload must be last.
218    */
219   &brw_vs_pull_constants,
220   &brw_vs_ubo_surfaces,
221   &brw_wm_pull_constants,
222   &brw_wm_ubo_surfaces,
223   &gen6_renderbuffer_surfaces,
224   &brw_texture_surfaces,
225   &brw_vs_binding_table,
226   &brw_wm_binding_table,
227
228   &gen7_samplers,
229   &gen6_multisample_state,
230
231   &gen7_disable_stages,
232   &gen7_vs_state,
233   &gen7_sol_state,
234   &gen7_clip_state,
235   &gen7_sbe_state,
236   &gen7_sf_state,
237   &gen7_wm_state,
238   &gen7_ps_state,
239
240   &gen6_scissor_state,
241
242   &gen7_depthbuffer,
243
244   &brw_polygon_stipple,
245   &brw_polygon_stipple_offset,
246
247   &brw_line_stipple,
248   &brw_aa_line_parameters,
249
250   &brw_drawing_rect,
251
252   &brw_indices,
253   &brw_index_buffer,
254   &brw_vertices,
255};
256
257
258void brw_init_state( struct brw_context *brw )
259{
260   const struct brw_tracked_state **atoms;
261   int num_atoms;
262
263   brw_init_caches(brw);
264
265   if (brw->intel.gen >= 7) {
266      atoms = gen7_atoms;
267      num_atoms = ARRAY_SIZE(gen7_atoms);
268   } else if (brw->intel.gen == 6) {
269      atoms = gen6_atoms;
270      num_atoms = ARRAY_SIZE(gen6_atoms);
271   } else {
272      atoms = gen4_atoms;
273      num_atoms = ARRAY_SIZE(gen4_atoms);
274   }
275
276   brw->atoms = atoms;
277   brw->num_atoms = num_atoms;
278
279   while (num_atoms--) {
280      assert((*atoms)->dirty.mesa |
281	     (*atoms)->dirty.brw |
282	     (*atoms)->dirty.cache);
283      assert((*atoms)->emit);
284      atoms++;
285   }
286}
287
288
289void brw_destroy_state( struct brw_context *brw )
290{
291   brw_destroy_caches(brw);
292}
293
294/***********************************************************************
295 */
296
297static GLuint check_state( const struct brw_state_flags *a,
298			   const struct brw_state_flags *b )
299{
300   return ((a->mesa & b->mesa) |
301	   (a->brw & b->brw) |
302	   (a->cache & b->cache)) != 0;
303}
304
305static void accumulate_state( struct brw_state_flags *a,
306			      const struct brw_state_flags *b )
307{
308   a->mesa |= b->mesa;
309   a->brw |= b->brw;
310   a->cache |= b->cache;
311}
312
313
314static void xor_states( struct brw_state_flags *result,
315			     const struct brw_state_flags *a,
316			      const struct brw_state_flags *b )
317{
318   result->mesa = a->mesa ^ b->mesa;
319   result->brw = a->brw ^ b->brw;
320   result->cache = a->cache ^ b->cache;
321}
322
323struct dirty_bit_map {
324   uint32_t bit;
325   char *name;
326   uint32_t count;
327};
328
329#define DEFINE_BIT(name) {name, #name, 0}
330
331static struct dirty_bit_map mesa_bits[] = {
332   DEFINE_BIT(_NEW_MODELVIEW),
333   DEFINE_BIT(_NEW_PROJECTION),
334   DEFINE_BIT(_NEW_TEXTURE_MATRIX),
335   DEFINE_BIT(_NEW_COLOR),
336   DEFINE_BIT(_NEW_DEPTH),
337   DEFINE_BIT(_NEW_EVAL),
338   DEFINE_BIT(_NEW_FOG),
339   DEFINE_BIT(_NEW_HINT),
340   DEFINE_BIT(_NEW_LIGHT),
341   DEFINE_BIT(_NEW_LINE),
342   DEFINE_BIT(_NEW_PIXEL),
343   DEFINE_BIT(_NEW_POINT),
344   DEFINE_BIT(_NEW_POLYGON),
345   DEFINE_BIT(_NEW_POLYGONSTIPPLE),
346   DEFINE_BIT(_NEW_SCISSOR),
347   DEFINE_BIT(_NEW_STENCIL),
348   DEFINE_BIT(_NEW_TEXTURE),
349   DEFINE_BIT(_NEW_TRANSFORM),
350   DEFINE_BIT(_NEW_VIEWPORT),
351   DEFINE_BIT(_NEW_PACKUNPACK),
352   DEFINE_BIT(_NEW_ARRAY),
353   DEFINE_BIT(_NEW_RENDERMODE),
354   DEFINE_BIT(_NEW_BUFFERS),
355   DEFINE_BIT(_NEW_MULTISAMPLE),
356   DEFINE_BIT(_NEW_TRACK_MATRIX),
357   DEFINE_BIT(_NEW_PROGRAM),
358   DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
359   {0, 0, 0}
360};
361
362static struct dirty_bit_map brw_bits[] = {
363   DEFINE_BIT(BRW_NEW_URB_FENCE),
364   DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
365   DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
366   DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS),
367   DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
368   DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
369   DEFINE_BIT(BRW_NEW_PRIMITIVE),
370   DEFINE_BIT(BRW_NEW_CONTEXT),
371   DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS),
372   DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
373   DEFINE_BIT(BRW_NEW_PSP),
374   DEFINE_BIT(BRW_NEW_SURFACES),
375   DEFINE_BIT(BRW_NEW_INDICES),
376   DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
377   DEFINE_BIT(BRW_NEW_VERTICES),
378   DEFINE_BIT(BRW_NEW_BATCH),
379   DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
380   DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
381   DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
382   DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
383   DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
384   {0, 0, 0}
385};
386
387static struct dirty_bit_map cache_bits[] = {
388   DEFINE_BIT(CACHE_NEW_BLEND_STATE),
389   DEFINE_BIT(CACHE_NEW_CC_VP),
390   DEFINE_BIT(CACHE_NEW_CC_UNIT),
391   DEFINE_BIT(CACHE_NEW_WM_PROG),
392   DEFINE_BIT(CACHE_NEW_SAMPLER),
393   DEFINE_BIT(CACHE_NEW_WM_UNIT),
394   DEFINE_BIT(CACHE_NEW_SF_PROG),
395   DEFINE_BIT(CACHE_NEW_SF_VP),
396   DEFINE_BIT(CACHE_NEW_SF_UNIT),
397   DEFINE_BIT(CACHE_NEW_VS_UNIT),
398   DEFINE_BIT(CACHE_NEW_VS_PROG),
399   DEFINE_BIT(CACHE_NEW_GS_UNIT),
400   DEFINE_BIT(CACHE_NEW_GS_PROG),
401   DEFINE_BIT(CACHE_NEW_CLIP_VP),
402   DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
403   DEFINE_BIT(CACHE_NEW_CLIP_PROG),
404   {0, 0, 0}
405};
406
407
408static void
409brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
410{
411   int i;
412
413   for (i = 0; i < 32; i++) {
414      if (bit_map[i].bit == 0)
415	 return;
416
417      if (bit_map[i].bit & bits)
418	 bit_map[i].count++;
419   }
420}
421
422static void
423brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
424{
425   int i;
426
427   for (i = 0; i < 32; i++) {
428      if (bit_map[i].bit == 0)
429	 return;
430
431      fprintf(stderr, "0x%08x: %12d (%s)\n",
432	      bit_map[i].bit, bit_map[i].count, bit_map[i].name);
433   }
434}
435
436/***********************************************************************
437 * Emit all state:
438 */
439void brw_upload_state(struct brw_context *brw)
440{
441   struct gl_context *ctx = &brw->intel.ctx;
442   struct intel_context *intel = &brw->intel;
443   struct brw_state_flags *state = &brw->state.dirty;
444   int i;
445   static int dirty_count = 0;
446
447   state->mesa |= brw->intel.NewGLState;
448   brw->intel.NewGLState = 0;
449
450   if (brw->emit_state_always) {
451      state->mesa |= ~0;
452      state->brw |= ~0;
453      state->cache |= ~0;
454   }
455
456   if (brw->fragment_program != ctx->FragmentProgram._Current) {
457      brw->fragment_program = ctx->FragmentProgram._Current;
458      brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
459   }
460
461   if (brw->vertex_program != ctx->VertexProgram._Current) {
462      brw->vertex_program = ctx->VertexProgram._Current;
463      brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
464   }
465
466   if ((state->mesa | state->cache | state->brw) == 0)
467      return;
468
469   brw->intel.Fallback = false; /* boolean, not bitfield */
470
471   intel_check_front_buffer_rendering(intel);
472
473   if (unlikely(INTEL_DEBUG)) {
474      /* Debug version which enforces various sanity checks on the
475       * state flags which are generated and checked to help ensure
476       * state atoms are ordered correctly in the list.
477       */
478      struct brw_state_flags examined, prev;
479      memset(&examined, 0, sizeof(examined));
480      prev = *state;
481
482      for (i = 0; i < brw->num_atoms; i++) {
483	 const struct brw_tracked_state *atom = brw->atoms[i];
484	 struct brw_state_flags generated;
485
486	 if (brw->intel.Fallback)
487	    break;
488
489	 if (check_state(state, &atom->dirty)) {
490	    atom->emit(brw);
491	 }
492
493	 accumulate_state(&examined, &atom->dirty);
494
495	 /* generated = (prev ^ state)
496	  * if (examined & generated)
497	  *     fail;
498	  */
499	 xor_states(&generated, &prev, state);
500	 assert(!check_state(&examined, &generated));
501	 prev = *state;
502      }
503   }
504   else {
505      for (i = 0; i < brw->num_atoms; i++) {
506	 const struct brw_tracked_state *atom = brw->atoms[i];
507
508	 if (brw->intel.Fallback)
509	    break;
510
511	 if (check_state(state, &atom->dirty)) {
512	    atom->emit(brw);
513	 }
514      }
515   }
516
517   if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
518      brw_update_dirty_count(mesa_bits, state->mesa);
519      brw_update_dirty_count(brw_bits, state->brw);
520      brw_update_dirty_count(cache_bits, state->cache);
521      if (dirty_count++ % 1000 == 0) {
522	 brw_print_dirty_count(mesa_bits, state->mesa);
523	 brw_print_dirty_count(brw_bits, state->brw);
524	 brw_print_dirty_count(cache_bits, state->cache);
525	 fprintf(stderr, "\n");
526      }
527   }
528
529   if (!brw->intel.Fallback)
530      memset(state, 0, sizeof(*state));
531}
532