brw_vec4_emit.cpp revision 43e3a7533d5537e48cef23588131dd25d938ee4b
1/* Copyright © 2011 Intel Corporation 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice (including the next 11 * paragraph) shall be included in all copies or substantial portions of the 12 * Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 20 * IN THE SOFTWARE. 21 */ 22 23#include "brw_vec4.h" 24#include "glsl/ir_print_visitor.h" 25 26extern "C" { 27#include "brw_eu.h" 28#include "main/macros.h" 29}; 30 31using namespace brw; 32 33namespace brw { 34 35int 36vec4_visitor::setup_attributes(int payload_reg) 37{ 38 int nr_attributes; 39 int attribute_map[VERT_ATTRIB_MAX + 1]; 40 41 nr_attributes = 0; 42 for (int i = 0; i < VERT_ATTRIB_MAX; i++) { 43 if (prog_data->inputs_read & BITFIELD64_BIT(i)) { 44 attribute_map[i] = payload_reg + nr_attributes; 45 nr_attributes++; 46 } 47 } 48 49 /* VertexID is stored by the VF as the last vertex element, but we 50 * don't represent it with a flag in inputs_read, so we call it 51 * VERT_ATTRIB_MAX. 52 */ 53 if (prog_data->uses_vertexid) { 54 attribute_map[VERT_ATTRIB_MAX] = payload_reg + nr_attributes; 55 nr_attributes++; 56 } 57 58 foreach_list(node, &this->instructions) { 59 vec4_instruction *inst = (vec4_instruction *)node; 60 61 /* We have to support ATTR as a destination for GL_FIXED fixup. */ 62 if (inst->dst.file == ATTR) { 63 int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset]; 64 65 struct brw_reg reg = brw_vec8_grf(grf, 0); 66 reg.dw1.bits.writemask = inst->dst.writemask; 67 68 inst->dst.file = HW_REG; 69 inst->dst.fixed_hw_reg = reg; 70 } 71 72 for (int i = 0; i < 3; i++) { 73 if (inst->src[i].file != ATTR) 74 continue; 75 76 int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset]; 77 78 struct brw_reg reg = brw_vec8_grf(grf, 0); 79 reg.dw1.bits.swizzle = inst->src[i].swizzle; 80 reg.type = inst->src[i].type; 81 if (inst->src[i].abs) 82 reg = brw_abs(reg); 83 if (inst->src[i].negate) 84 reg = negate(reg); 85 86 inst->src[i].file = HW_REG; 87 inst->src[i].fixed_hw_reg = reg; 88 } 89 } 90 91 /* The BSpec says we always have to read at least one thing from 92 * the VF, and it appears that the hardware wedges otherwise. 93 */ 94 if (nr_attributes == 0) 95 nr_attributes = 1; 96 97 prog_data->urb_read_length = (nr_attributes + 1) / 2; 98 99 unsigned vue_entries = MAX2(nr_attributes, c->prog_data.vue_map.num_slots); 100 101 if (intel->gen == 6) 102 c->prog_data.urb_entry_size = ALIGN(vue_entries, 8) / 8; 103 else 104 c->prog_data.urb_entry_size = ALIGN(vue_entries, 4) / 4; 105 106 return payload_reg + nr_attributes; 107} 108 109int 110vec4_visitor::setup_uniforms(int reg) 111{ 112 /* The pre-gen6 VS requires that some push constants get loaded no 113 * matter what, or the GPU would hang. 114 */ 115 if (intel->gen < 6 && this->uniforms == 0) { 116 this->uniform_vector_size[this->uniforms] = 1; 117 118 for (unsigned int i = 0; i < 4; i++) { 119 unsigned int slot = this->uniforms * 4 + i; 120 static float zero = 0.0; 121 c->prog_data.param[slot] = &zero; 122 } 123 124 this->uniforms++; 125 reg++; 126 } else { 127 reg += ALIGN(uniforms, 2) / 2; 128 } 129 130 c->prog_data.nr_params = this->uniforms * 4; 131 132 c->prog_data.curb_read_length = reg - 1; 133 c->prog_data.uses_new_param_layout = true; 134 135 return reg; 136} 137 138void 139vec4_visitor::setup_payload(void) 140{ 141 int reg = 0; 142 143 /* The payload always contains important data in g0, which contains 144 * the URB handles that are passed on to the URB write at the end 145 * of the thread. So, we always start push constants at g1. 146 */ 147 reg++; 148 149 reg = setup_uniforms(reg); 150 151 reg = setup_attributes(reg); 152 153 this->first_non_payload_grf = reg; 154} 155 156struct brw_reg 157vec4_instruction::get_dst(void) 158{ 159 struct brw_reg brw_reg; 160 161 switch (dst.file) { 162 case GRF: 163 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0); 164 brw_reg = retype(brw_reg, dst.type); 165 brw_reg.dw1.bits.writemask = dst.writemask; 166 break; 167 168 case MRF: 169 brw_reg = brw_message_reg(dst.reg + dst.reg_offset); 170 brw_reg = retype(brw_reg, dst.type); 171 brw_reg.dw1.bits.writemask = dst.writemask; 172 break; 173 174 case HW_REG: 175 brw_reg = dst.fixed_hw_reg; 176 break; 177 178 case BAD_FILE: 179 brw_reg = brw_null_reg(); 180 break; 181 182 default: 183 assert(!"not reached"); 184 brw_reg = brw_null_reg(); 185 break; 186 } 187 return brw_reg; 188} 189 190struct brw_reg 191vec4_instruction::get_src(int i) 192{ 193 struct brw_reg brw_reg; 194 195 switch (src[i].file) { 196 case GRF: 197 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0); 198 brw_reg = retype(brw_reg, src[i].type); 199 brw_reg.dw1.bits.swizzle = src[i].swizzle; 200 if (src[i].abs) 201 brw_reg = brw_abs(brw_reg); 202 if (src[i].negate) 203 brw_reg = negate(brw_reg); 204 break; 205 206 case IMM: 207 switch (src[i].type) { 208 case BRW_REGISTER_TYPE_F: 209 brw_reg = brw_imm_f(src[i].imm.f); 210 break; 211 case BRW_REGISTER_TYPE_D: 212 brw_reg = brw_imm_d(src[i].imm.i); 213 break; 214 case BRW_REGISTER_TYPE_UD: 215 brw_reg = brw_imm_ud(src[i].imm.u); 216 break; 217 default: 218 assert(!"not reached"); 219 brw_reg = brw_null_reg(); 220 break; 221 } 222 break; 223 224 case UNIFORM: 225 brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2, 226 ((src[i].reg + src[i].reg_offset) % 2) * 4), 227 0, 4, 1); 228 brw_reg = retype(brw_reg, src[i].type); 229 brw_reg.dw1.bits.swizzle = src[i].swizzle; 230 if (src[i].abs) 231 brw_reg = brw_abs(brw_reg); 232 if (src[i].negate) 233 brw_reg = negate(brw_reg); 234 235 /* This should have been moved to pull constants. */ 236 assert(!src[i].reladdr); 237 break; 238 239 case HW_REG: 240 brw_reg = src[i].fixed_hw_reg; 241 break; 242 243 case BAD_FILE: 244 /* Probably unused. */ 245 brw_reg = brw_null_reg(); 246 break; 247 case ATTR: 248 default: 249 assert(!"not reached"); 250 brw_reg = brw_null_reg(); 251 break; 252 } 253 254 return brw_reg; 255} 256 257void 258vec4_visitor::generate_math1_gen4(vec4_instruction *inst, 259 struct brw_reg dst, 260 struct brw_reg src) 261{ 262 brw_math(p, 263 dst, 264 brw_math_function(inst->opcode), 265 inst->base_mrf, 266 src, 267 BRW_MATH_DATA_VECTOR, 268 BRW_MATH_PRECISION_FULL); 269} 270 271static void 272check_gen6_math_src_arg(struct brw_reg src) 273{ 274 /* Source swizzles are ignored. */ 275 assert(!src.abs); 276 assert(!src.negate); 277 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW); 278} 279 280void 281vec4_visitor::generate_math1_gen6(vec4_instruction *inst, 282 struct brw_reg dst, 283 struct brw_reg src) 284{ 285 /* Can't do writemask because math can't be align16. */ 286 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); 287 check_gen6_math_src_arg(src); 288 289 brw_set_access_mode(p, BRW_ALIGN_1); 290 brw_math(p, 291 dst, 292 brw_math_function(inst->opcode), 293 inst->base_mrf, 294 src, 295 BRW_MATH_DATA_SCALAR, 296 BRW_MATH_PRECISION_FULL); 297 brw_set_access_mode(p, BRW_ALIGN_16); 298} 299 300void 301vec4_visitor::generate_math2_gen7(vec4_instruction *inst, 302 struct brw_reg dst, 303 struct brw_reg src0, 304 struct brw_reg src1) 305{ 306 brw_math2(p, 307 dst, 308 brw_math_function(inst->opcode), 309 src0, src1); 310} 311 312void 313vec4_visitor::generate_math2_gen6(vec4_instruction *inst, 314 struct brw_reg dst, 315 struct brw_reg src0, 316 struct brw_reg src1) 317{ 318 /* Can't do writemask because math can't be align16. */ 319 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); 320 /* Source swizzles are ignored. */ 321 check_gen6_math_src_arg(src0); 322 check_gen6_math_src_arg(src1); 323 324 brw_set_access_mode(p, BRW_ALIGN_1); 325 brw_math2(p, 326 dst, 327 brw_math_function(inst->opcode), 328 src0, src1); 329 brw_set_access_mode(p, BRW_ALIGN_16); 330} 331 332void 333vec4_visitor::generate_math2_gen4(vec4_instruction *inst, 334 struct brw_reg dst, 335 struct brw_reg src0, 336 struct brw_reg src1) 337{ 338 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13 339 * "Message Payload": 340 * 341 * "Operand0[7]. For the INT DIV functions, this operand is the 342 * denominator." 343 * ... 344 * "Operand1[7]. For the INT DIV functions, this operand is the 345 * numerator." 346 */ 347 bool is_int_div = inst->opcode != SHADER_OPCODE_POW; 348 struct brw_reg &op0 = is_int_div ? src1 : src0; 349 struct brw_reg &op1 = is_int_div ? src0 : src1; 350 351 brw_push_insn_state(p); 352 brw_set_saturate(p, false); 353 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 354 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1); 355 brw_pop_insn_state(p); 356 357 brw_math(p, 358 dst, 359 brw_math_function(inst->opcode), 360 inst->base_mrf, 361 op0, 362 BRW_MATH_DATA_VECTOR, 363 BRW_MATH_PRECISION_FULL); 364} 365 366void 367vec4_visitor::generate_tex(vec4_instruction *inst, 368 struct brw_reg dst, 369 struct brw_reg src) 370{ 371 int msg_type = -1; 372 373 if (intel->gen >= 5) { 374 switch (inst->opcode) { 375 case SHADER_OPCODE_TEX: 376 case SHADER_OPCODE_TXL: 377 if (inst->shadow_compare) { 378 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE; 379 } else { 380 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD; 381 } 382 break; 383 case SHADER_OPCODE_TXD: 384 /* There is no sample_d_c message; comparisons are done manually. */ 385 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS; 386 break; 387 case SHADER_OPCODE_TXF: 388 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD; 389 break; 390 case SHADER_OPCODE_TXS: 391 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO; 392 break; 393 default: 394 assert(!"should not get here: invalid VS texture opcode"); 395 break; 396 } 397 } else { 398 switch (inst->opcode) { 399 case SHADER_OPCODE_TEX: 400 case SHADER_OPCODE_TXL: 401 if (inst->shadow_compare) { 402 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE; 403 assert(inst->mlen == 3); 404 } else { 405 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD; 406 assert(inst->mlen == 2); 407 } 408 break; 409 case SHADER_OPCODE_TXD: 410 /* There is no sample_d_c message; comparisons are done manually. */ 411 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS; 412 assert(inst->mlen == 4); 413 break; 414 case SHADER_OPCODE_TXF: 415 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD; 416 assert(inst->mlen == 2); 417 break; 418 case SHADER_OPCODE_TXS: 419 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO; 420 assert(inst->mlen == 2); 421 break; 422 default: 423 assert(!"should not get here: invalid VS texture opcode"); 424 break; 425 } 426 } 427 428 assert(msg_type != -1); 429 430 /* Load the message header if present. If there's a texture offset, we need 431 * to set it up explicitly and load the offset bitfield. Otherwise, we can 432 * use an implied move from g0 to the first message register. 433 */ 434 if (inst->texture_offset) { 435 /* Explicitly set up the message header by copying g0 to the MRF. */ 436 brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD), 437 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); 438 439 /* Then set the offset bits in DWord 2. */ 440 brw_set_access_mode(p, BRW_ALIGN_1); 441 brw_MOV(p, 442 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2), 443 BRW_REGISTER_TYPE_UD), 444 brw_imm_uw(inst->texture_offset)); 445 brw_set_access_mode(p, BRW_ALIGN_16); 446 } else if (inst->header_present) { 447 /* Set up an implied move from g0 to the MRF. */ 448 src = brw_vec8_grf(0, 0); 449 } 450 451 uint32_t return_format; 452 453 switch (dst.type) { 454 case BRW_REGISTER_TYPE_D: 455 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32; 456 break; 457 case BRW_REGISTER_TYPE_UD: 458 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32; 459 break; 460 default: 461 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32; 462 break; 463 } 464 465 brw_SAMPLE(p, 466 dst, 467 inst->base_mrf, 468 src, 469 SURF_INDEX_VS_TEXTURE(inst->sampler), 470 inst->sampler, 471 WRITEMASK_XYZW, 472 msg_type, 473 1, /* response length */ 474 inst->mlen, 475 inst->header_present, 476 BRW_SAMPLER_SIMD_MODE_SIMD4X2, 477 return_format); 478} 479 480void 481vec4_visitor::generate_urb_write(vec4_instruction *inst) 482{ 483 brw_urb_WRITE(p, 484 brw_null_reg(), /* dest */ 485 inst->base_mrf, /* starting mrf reg nr */ 486 brw_vec8_grf(0, 0), /* src */ 487 false, /* allocate */ 488 true, /* used */ 489 inst->mlen, 490 0, /* response len */ 491 inst->eot, /* eot */ 492 inst->eot, /* writes complete */ 493 inst->offset, /* urb destination offset */ 494 BRW_URB_SWIZZLE_INTERLEAVE); 495} 496 497void 498vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1, 499 struct brw_reg index) 500{ 501 int second_vertex_offset; 502 503 if (intel->gen >= 6) 504 second_vertex_offset = 1; 505 else 506 second_vertex_offset = 16; 507 508 m1 = retype(m1, BRW_REGISTER_TYPE_D); 509 510 /* Set up M1 (message payload). Only the block offsets in M1.0 and 511 * M1.4 are used, and the rest are ignored. 512 */ 513 struct brw_reg m1_0 = suboffset(vec1(m1), 0); 514 struct brw_reg m1_4 = suboffset(vec1(m1), 4); 515 struct brw_reg index_0 = suboffset(vec1(index), 0); 516 struct brw_reg index_4 = suboffset(vec1(index), 4); 517 518 brw_push_insn_state(p); 519 brw_set_mask_control(p, BRW_MASK_DISABLE); 520 brw_set_access_mode(p, BRW_ALIGN_1); 521 522 brw_MOV(p, m1_0, index_0); 523 524 brw_set_predicate_inverse(p, true); 525 if (index.file == BRW_IMMEDIATE_VALUE) { 526 index_4.dw1.ud += second_vertex_offset; 527 brw_MOV(p, m1_4, index_4); 528 } else { 529 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset)); 530 } 531 532 brw_pop_insn_state(p); 533} 534 535void 536vec4_visitor::generate_scratch_read(vec4_instruction *inst, 537 struct brw_reg dst, 538 struct brw_reg index) 539{ 540 struct brw_reg header = brw_vec8_grf(0, 0); 541 542 gen6_resolve_implied_move(p, &header, inst->base_mrf); 543 544 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1), 545 index); 546 547 uint32_t msg_type; 548 549 if (intel->gen >= 6) 550 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 551 else if (intel->gen == 5 || intel->is_g4x) 552 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 553 else 554 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 555 556 /* Each of the 8 channel enables is considered for whether each 557 * dword is written. 558 */ 559 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); 560 brw_set_dest(p, send, dst); 561 brw_set_src0(p, send, header); 562 if (intel->gen < 6) 563 send->header.destreg__conditionalmod = inst->base_mrf; 564 brw_set_dp_read_message(p, send, 565 255, /* binding table index: stateless access */ 566 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 567 msg_type, 568 BRW_DATAPORT_READ_TARGET_RENDER_CACHE, 569 2, /* mlen */ 570 1 /* rlen */); 571} 572 573void 574vec4_visitor::generate_scratch_write(vec4_instruction *inst, 575 struct brw_reg dst, 576 struct brw_reg src, 577 struct brw_reg index) 578{ 579 struct brw_reg header = brw_vec8_grf(0, 0); 580 bool write_commit; 581 582 /* If the instruction is predicated, we'll predicate the send, not 583 * the header setup. 584 */ 585 brw_set_predicate_control(p, false); 586 587 gen6_resolve_implied_move(p, &header, inst->base_mrf); 588 589 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1), 590 index); 591 592 brw_MOV(p, 593 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D), 594 retype(src, BRW_REGISTER_TYPE_D)); 595 596 uint32_t msg_type; 597 598 if (intel->gen >= 7) 599 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE; 600 else if (intel->gen == 6) 601 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE; 602 else 603 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE; 604 605 brw_set_predicate_control(p, inst->predicate); 606 607 /* Pre-gen6, we have to specify write commits to ensure ordering 608 * between reads and writes within a thread. Afterwards, that's 609 * guaranteed and write commits only matter for inter-thread 610 * synchronization. 611 */ 612 if (intel->gen >= 6) { 613 write_commit = false; 614 } else { 615 /* The visitor set up our destination register to be g0. This 616 * means that when the next read comes along, we will end up 617 * reading from g0 and causing a block on the write commit. For 618 * write-after-read, we are relying on the value of the previous 619 * read being used (and thus blocking on completion) before our 620 * write is executed. This means we have to be careful in 621 * instruction scheduling to not violate this assumption. 622 */ 623 write_commit = true; 624 } 625 626 /* Each of the 8 channel enables is considered for whether each 627 * dword is written. 628 */ 629 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); 630 brw_set_dest(p, send, dst); 631 brw_set_src0(p, send, header); 632 if (intel->gen < 6) 633 send->header.destreg__conditionalmod = inst->base_mrf; 634 brw_set_dp_write_message(p, send, 635 255, /* binding table index: stateless access */ 636 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 637 msg_type, 638 3, /* mlen */ 639 true, /* header present */ 640 false, /* not a render target write */ 641 write_commit, /* rlen */ 642 false, /* eot */ 643 write_commit); 644} 645 646void 647vec4_visitor::generate_pull_constant_load(vec4_instruction *inst, 648 struct brw_reg dst, 649 struct brw_reg index, 650 struct brw_reg offset) 651{ 652 assert(index.file == BRW_IMMEDIATE_VALUE && 653 index.type == BRW_REGISTER_TYPE_UD); 654 uint32_t surf_index = index.dw1.ud; 655 656 if (intel->gen == 7) { 657 gen6_resolve_implied_move(p, &offset, inst->base_mrf); 658 brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND); 659 brw_set_dest(p, insn, dst); 660 brw_set_src0(p, insn, offset); 661 brw_set_sampler_message(p, insn, 662 surf_index, 663 0, /* LD message ignores sampler unit */ 664 GEN5_SAMPLER_MESSAGE_SAMPLE_LD, 665 1, /* rlen */ 666 1, /* mlen */ 667 false, /* no header */ 668 BRW_SAMPLER_SIMD_MODE_SIMD4X2, 669 0); 670 return; 671 } 672 673 struct brw_reg header = brw_vec8_grf(0, 0); 674 675 gen6_resolve_implied_move(p, &header, inst->base_mrf); 676 677 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D), 678 offset); 679 680 uint32_t msg_type; 681 682 if (intel->gen >= 6) 683 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 684 else if (intel->gen == 5 || intel->is_g4x) 685 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 686 else 687 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; 688 689 /* Each of the 8 channel enables is considered for whether each 690 * dword is written. 691 */ 692 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND); 693 brw_set_dest(p, send, dst); 694 brw_set_src0(p, send, header); 695 if (intel->gen < 6) 696 send->header.destreg__conditionalmod = inst->base_mrf; 697 brw_set_dp_read_message(p, send, 698 surf_index, 699 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 700 msg_type, 701 BRW_DATAPORT_READ_TARGET_DATA_CACHE, 702 2, /* mlen */ 703 1 /* rlen */); 704} 705 706void 707vec4_visitor::generate_vs_instruction(vec4_instruction *instruction, 708 struct brw_reg dst, 709 struct brw_reg *src) 710{ 711 vec4_instruction *inst = (vec4_instruction *)instruction; 712 713 switch (inst->opcode) { 714 case SHADER_OPCODE_RCP: 715 case SHADER_OPCODE_RSQ: 716 case SHADER_OPCODE_SQRT: 717 case SHADER_OPCODE_EXP2: 718 case SHADER_OPCODE_LOG2: 719 case SHADER_OPCODE_SIN: 720 case SHADER_OPCODE_COS: 721 if (intel->gen == 6) { 722 generate_math1_gen6(inst, dst, src[0]); 723 } else { 724 /* Also works for Gen7. */ 725 generate_math1_gen4(inst, dst, src[0]); 726 } 727 break; 728 729 case SHADER_OPCODE_POW: 730 case SHADER_OPCODE_INT_QUOTIENT: 731 case SHADER_OPCODE_INT_REMAINDER: 732 if (intel->gen >= 7) { 733 generate_math2_gen7(inst, dst, src[0], src[1]); 734 } else if (intel->gen == 6) { 735 generate_math2_gen6(inst, dst, src[0], src[1]); 736 } else { 737 generate_math2_gen4(inst, dst, src[0], src[1]); 738 } 739 break; 740 741 case SHADER_OPCODE_TEX: 742 case SHADER_OPCODE_TXD: 743 case SHADER_OPCODE_TXF: 744 case SHADER_OPCODE_TXL: 745 case SHADER_OPCODE_TXS: 746 generate_tex(inst, dst, src[0]); 747 break; 748 749 case VS_OPCODE_URB_WRITE: 750 generate_urb_write(inst); 751 break; 752 753 case VS_OPCODE_SCRATCH_READ: 754 generate_scratch_read(inst, dst, src[0]); 755 break; 756 757 case VS_OPCODE_SCRATCH_WRITE: 758 generate_scratch_write(inst, dst, src[0], src[1]); 759 break; 760 761 case VS_OPCODE_PULL_CONSTANT_LOAD: 762 generate_pull_constant_load(inst, dst, src[0], src[1]); 763 break; 764 765 default: 766 if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) { 767 fail("unsupported opcode in `%s' in VS\n", 768 brw_opcodes[inst->opcode].name); 769 } else { 770 fail("Unsupported opcode %d in VS", inst->opcode); 771 } 772 } 773} 774 775bool 776vec4_visitor::run() 777{ 778 if (c->key.userclip_active && !c->key.uses_clip_distance) 779 setup_uniform_clipplane_values(); 780 781 /* Generate VS IR for main(). (the visitor only descends into 782 * functions called "main"). 783 */ 784 visit_instructions(shader->ir); 785 786 emit_urb_writes(); 787 788 /* Before any optimization, push array accesses out to scratch 789 * space where we need them to be. This pass may allocate new 790 * virtual GRFs, so we want to do it early. It also makes sure 791 * that we have reladdr computations available for CSE, since we'll 792 * often do repeated subexpressions for those. 793 */ 794 move_grf_array_access_to_scratch(); 795 move_uniform_array_access_to_pull_constants(); 796 pack_uniform_registers(); 797 move_push_constants_to_pull_constants(); 798 799 bool progress; 800 do { 801 progress = false; 802 progress = dead_code_eliminate() || progress; 803 progress = opt_copy_propagation() || progress; 804 progress = opt_algebraic() || progress; 805 progress = opt_compute_to_mrf() || progress; 806 } while (progress); 807 808 809 if (failed) 810 return false; 811 812 setup_payload(); 813 reg_allocate(); 814 815 if (failed) 816 return false; 817 818 brw_set_access_mode(p, BRW_ALIGN_16); 819 820 generate_code(); 821 822 return !failed; 823} 824 825void 826vec4_visitor::generate_code() 827{ 828 int last_native_inst = 0; 829 const char *last_annotation_string = NULL; 830 ir_instruction *last_annotation_ir = NULL; 831 832 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 833 printf("Native code for vertex shader %d:\n", prog->Name); 834 } 835 836 foreach_list(node, &this->instructions) { 837 vec4_instruction *inst = (vec4_instruction *)node; 838 struct brw_reg src[3], dst; 839 840 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 841 if (last_annotation_ir != inst->ir) { 842 last_annotation_ir = inst->ir; 843 if (last_annotation_ir) { 844 printf(" "); 845 last_annotation_ir->print(); 846 printf("\n"); 847 } 848 } 849 if (last_annotation_string != inst->annotation) { 850 last_annotation_string = inst->annotation; 851 if (last_annotation_string) 852 printf(" %s\n", last_annotation_string); 853 } 854 } 855 856 for (unsigned int i = 0; i < 3; i++) { 857 src[i] = inst->get_src(i); 858 } 859 dst = inst->get_dst(); 860 861 brw_set_conditionalmod(p, inst->conditional_mod); 862 brw_set_predicate_control(p, inst->predicate); 863 brw_set_predicate_inverse(p, inst->predicate_inverse); 864 brw_set_saturate(p, inst->saturate); 865 866 switch (inst->opcode) { 867 case BRW_OPCODE_MOV: 868 brw_MOV(p, dst, src[0]); 869 break; 870 case BRW_OPCODE_ADD: 871 brw_ADD(p, dst, src[0], src[1]); 872 break; 873 case BRW_OPCODE_MUL: 874 brw_MUL(p, dst, src[0], src[1]); 875 break; 876 case BRW_OPCODE_MACH: 877 brw_set_acc_write_control(p, 1); 878 brw_MACH(p, dst, src[0], src[1]); 879 brw_set_acc_write_control(p, 0); 880 break; 881 882 case BRW_OPCODE_FRC: 883 brw_FRC(p, dst, src[0]); 884 break; 885 case BRW_OPCODE_RNDD: 886 brw_RNDD(p, dst, src[0]); 887 break; 888 case BRW_OPCODE_RNDE: 889 brw_RNDE(p, dst, src[0]); 890 break; 891 case BRW_OPCODE_RNDZ: 892 brw_RNDZ(p, dst, src[0]); 893 break; 894 895 case BRW_OPCODE_AND: 896 brw_AND(p, dst, src[0], src[1]); 897 break; 898 case BRW_OPCODE_OR: 899 brw_OR(p, dst, src[0], src[1]); 900 break; 901 case BRW_OPCODE_XOR: 902 brw_XOR(p, dst, src[0], src[1]); 903 break; 904 case BRW_OPCODE_NOT: 905 brw_NOT(p, dst, src[0]); 906 break; 907 case BRW_OPCODE_ASR: 908 brw_ASR(p, dst, src[0], src[1]); 909 break; 910 case BRW_OPCODE_SHR: 911 brw_SHR(p, dst, src[0], src[1]); 912 break; 913 case BRW_OPCODE_SHL: 914 brw_SHL(p, dst, src[0], src[1]); 915 break; 916 917 case BRW_OPCODE_CMP: 918 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]); 919 break; 920 case BRW_OPCODE_SEL: 921 brw_SEL(p, dst, src[0], src[1]); 922 break; 923 924 case BRW_OPCODE_DP4: 925 brw_DP4(p, dst, src[0], src[1]); 926 break; 927 928 case BRW_OPCODE_DP3: 929 brw_DP3(p, dst, src[0], src[1]); 930 break; 931 932 case BRW_OPCODE_DP2: 933 brw_DP2(p, dst, src[0], src[1]); 934 break; 935 936 case BRW_OPCODE_IF: 937 if (inst->src[0].file != BAD_FILE) { 938 /* The instruction has an embedded compare (only allowed on gen6) */ 939 assert(intel->gen == 6); 940 gen6_IF(p, inst->conditional_mod, src[0], src[1]); 941 } else { 942 struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8); 943 brw_inst->header.predicate_control = inst->predicate; 944 } 945 break; 946 947 case BRW_OPCODE_ELSE: 948 brw_ELSE(p); 949 break; 950 case BRW_OPCODE_ENDIF: 951 brw_ENDIF(p); 952 break; 953 954 case BRW_OPCODE_DO: 955 brw_DO(p, BRW_EXECUTE_8); 956 break; 957 958 case BRW_OPCODE_BREAK: 959 brw_BREAK(p); 960 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 961 break; 962 case BRW_OPCODE_CONTINUE: 963 /* FINISHME: We need to write the loop instruction support still. */ 964 if (intel->gen >= 6) 965 gen6_CONT(p); 966 else 967 brw_CONT(p); 968 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 969 break; 970 971 case BRW_OPCODE_WHILE: 972 brw_WHILE(p); 973 break; 974 975 default: 976 generate_vs_instruction(inst, dst, src); 977 break; 978 } 979 980 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 981 for (unsigned int i = last_native_inst; i < p->nr_insn; i++) { 982 if (0) { 983 printf("0x%08x 0x%08x 0x%08x 0x%08x ", 984 ((uint32_t *)&p->store[i])[3], 985 ((uint32_t *)&p->store[i])[2], 986 ((uint32_t *)&p->store[i])[1], 987 ((uint32_t *)&p->store[i])[0]); 988 } 989 brw_disasm(stdout, &p->store[i], intel->gen); 990 } 991 } 992 993 last_native_inst = p->nr_insn; 994 } 995 996 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 997 printf("\n"); 998 } 999 1000 brw_set_uip_jip(p); 1001 1002 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS 1003 * emit issues, it doesn't get the jump distances into the output, 1004 * which is often something we want to debug. So this is here in 1005 * case you're doing that. 1006 */ 1007 if (0) { 1008 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 1009 for (unsigned int i = 0; i < p->nr_insn; i++) { 1010 printf("0x%08x 0x%08x 0x%08x 0x%08x ", 1011 ((uint32_t *)&p->store[i])[3], 1012 ((uint32_t *)&p->store[i])[2], 1013 ((uint32_t *)&p->store[i])[1], 1014 ((uint32_t *)&p->store[i])[0]); 1015 brw_disasm(stdout, &p->store[i], intel->gen); 1016 } 1017 } 1018 } 1019} 1020 1021extern "C" { 1022 1023bool 1024brw_vs_emit(struct gl_shader_program *prog, struct brw_vs_compile *c) 1025{ 1026 struct intel_context *intel = &c->func.brw->intel; 1027 bool start_busy = false; 1028 float start_time = 0; 1029 1030 if (!prog) 1031 return false; 1032 1033 if (unlikely(INTEL_DEBUG & DEBUG_PERF)) { 1034 start_busy = (intel->batch.last_bo && 1035 drm_intel_bo_busy(intel->batch.last_bo)); 1036 start_time = get_time(); 1037 } 1038 1039 struct brw_shader *shader = 1040 (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX]; 1041 if (!shader) 1042 return false; 1043 1044 if (unlikely(INTEL_DEBUG & DEBUG_VS)) { 1045 printf("GLSL IR for native vertex shader %d:\n", prog->Name); 1046 _mesa_print_ir(shader->ir, NULL); 1047 printf("\n\n"); 1048 } 1049 1050 if (unlikely(INTEL_DEBUG & DEBUG_PERF)) { 1051 if (shader->compiled_once) { 1052 perf_debug("Recompiling vertex shader for program %d\n", prog->Name); 1053 } 1054 if (start_busy && !drm_intel_bo_busy(intel->batch.last_bo)) { 1055 perf_debug("VS compile took %.03f ms and stalled the GPU\n", 1056 (get_time() - start_time) * 1000); 1057 } 1058 } 1059 1060 vec4_visitor v(c, prog, shader); 1061 if (!v.run()) { 1062 prog->LinkStatus = false; 1063 ralloc_strcat(&prog->InfoLog, v.fail_msg); 1064 return false; 1065 } 1066 1067 shader->compiled_once = true; 1068 1069 return true; 1070} 1071 1072} /* extern "C" */ 1073 1074} /* namespace brw */ 1075