brw_wm_surface_state.c revision 28fab4295e9631ca91c5ebdf26d1bee23011d57e
1/* 2 Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 4 develop this 3D driver. 5 6 Permission is hereby granted, free of charge, to any person obtaining 7 a copy of this software and associated documentation files (the 8 "Software"), to deal in the Software without restriction, including 9 without limitation the rights to use, copy, modify, merge, publish, 10 distribute, sublicense, and/or sell copies of the Software, and to 11 permit persons to whom the Software is furnished to do so, subject to 12 the following conditions: 13 14 The above copyright notice and this permission notice (including the 15 next paragraph) shall be included in all copies or substantial 16 portions of the Software. 17 18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 26 **********************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 33#include "main/mtypes.h" 34#include "main/samplerobj.h" 35#include "program/prog_parameter.h" 36 37#include "intel_mipmap_tree.h" 38#include "intel_batchbuffer.h" 39#include "intel_tex.h" 40#include "intel_fbo.h" 41#include "intel_buffer_objects.h" 42 43#include "brw_context.h" 44#include "brw_state.h" 45#include "brw_defines.h" 46#include "brw_wm.h" 47 48GLuint 49translate_tex_target(GLenum target) 50{ 51 switch (target) { 52 case GL_TEXTURE_1D: 53 case GL_TEXTURE_1D_ARRAY_EXT: 54 return BRW_SURFACE_1D; 55 56 case GL_TEXTURE_RECTANGLE_NV: 57 return BRW_SURFACE_2D; 58 59 case GL_TEXTURE_2D: 60 case GL_TEXTURE_2D_ARRAY_EXT: 61 case GL_TEXTURE_EXTERNAL_OES: 62 return BRW_SURFACE_2D; 63 64 case GL_TEXTURE_3D: 65 return BRW_SURFACE_3D; 66 67 case GL_TEXTURE_CUBE_MAP: 68 return BRW_SURFACE_CUBE; 69 70 default: 71 assert(0); 72 return 0; 73 } 74} 75 76struct surface_format_info { 77 bool exists; 78 int sampling; 79 int filtering; 80 int shadow_compare; 81 int chroma_key; 82 int render_target; 83 int alpha_blend; 84 int input_vb; 85 int streamed_output_vb; 86 int color_processing; 87}; 88 89/* This macro allows us to write the table almost as it appears in the PRM, 90 * while restructuring it to turn it into the C code we want. 91 */ 92#define SF(sampl, filt, shad, ck, rt, ab, vb, so, color, sf) \ 93 [sf] = { true, sampl, filt, shad, ck, rt, ab, vb, so, color }, 94 95#define Y 0 96#define x 999 97/** 98 * This is the table of support for surface (texture, renderbuffer, and vertex 99 * buffer, but not depthbuffer) formats across the various hardware generations. 100 * 101 * The table is formatted to match the documentation, except that the docs have 102 * this ridiculous mapping of Y[*+~^#&] for "supported on DevWhatever". To put 103 * it in our table, here's the mapping: 104 * 105 * Y*: 45 106 * Y+: 45 (g45/gm45) 107 * Y~: 50 (gen5) 108 * Y^: 60 (gen6) 109 * Y#: 70 (gen7) 110 * 111 * See page 88 of the Sandybridge PRM VOL4_Part1 PDF. 112 */ 113const struct surface_format_info surface_formats[] = { 114/* smpl filt shad CK RT AB VB SO color */ 115 SF( Y, 50, x, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_FLOAT) 116 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_SINT) 117 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_UINT) 118 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_UNORM) 119 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_SNORM) 120 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64_FLOAT) 121 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32G32B32X32_FLOAT) 122 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_SSCALED) 123 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_USCALED) 124 SF( Y, 50, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_FLOAT) 125 SF( Y, x, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_SINT) 126 SF( Y, x, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_UINT) 127 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_UNORM) 128 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_SNORM) 129 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_SSCALED) 130 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_USCALED) 131 SF( Y, Y, x, x, Y, 45, Y, x, 60, BRW_SURFACEFORMAT_R16G16B16A16_UNORM) 132 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SNORM) 133 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SINT) 134 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_UINT) 135 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_FLOAT) 136 SF( Y, 50, x, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32G32_FLOAT) 137 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32_SINT) 138 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32_UINT) 139 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS) 140 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT) 141 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32A32_FLOAT) 142 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_UNORM) 143 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_SNORM) 144 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64_FLOAT) 145 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16X16_UNORM) 146 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16X16_FLOAT) 147 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A32X32_FLOAT) 148 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32X32_FLOAT) 149 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I32X32_FLOAT) 150 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SSCALED) 151 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_USCALED) 152 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_SSCALED) 153 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_USCALED) 154 SF( Y, Y, x, Y, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_B8G8R8A8_UNORM) 155 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB) 156/* smpl filt shad CK RT AB VB SO color */ 157 SF( Y, Y, x, x, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM) 158 SF( Y, Y, x, x, x, x, x, x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB) 159 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R10G10B10A2_UINT) 160 SF( Y, Y, x, x, x, Y, Y, x, x, BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM) 161 SF( Y, Y, x, x, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM) 162 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB) 163 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SNORM) 164 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SINT) 165 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_UINT) 166 SF( Y, Y, x, x, Y, 45, Y, x, x, BRW_SURFACEFORMAT_R16G16_UNORM) 167 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16G16_SNORM) 168 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_SINT) 169 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_UINT) 170 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16G16_FLOAT) 171 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM) 172 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB) 173 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R11G11B10_FLOAT) 174 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32_SINT) 175 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32_UINT) 176 SF( Y, 50, Y, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32_FLOAT) 177 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS) 178 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT) 179 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16A16_UNORM) 180 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I24X8_UNORM) 181 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L24X8_UNORM) 182 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A24X8_UNORM) 183 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I32_FLOAT) 184 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32_FLOAT) 185 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A32_FLOAT) 186 SF( Y, Y, x, Y, x, x, x, x, 60, BRW_SURFACEFORMAT_B8G8R8X8_UNORM) 187 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB) 188 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM) 189 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB) 190 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP) 191 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B10G10R10X2_UNORM) 192 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16A16_FLOAT) 193 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_UNORM) 194 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_SNORM) 195/* smpl filt shad CK RT AB VB SO color */ 196 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R10G10B10X2_USCALED) 197 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SSCALED) 198 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_USCALED) 199 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_SSCALED) 200 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_USCALED) 201 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_SSCALED) 202 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_USCALED) 203 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G6R5_UNORM) 204 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB) 205 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM) 206 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB) 207 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM) 208 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB) 209 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R8G8_UNORM) 210 SF( Y, Y, x, Y, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8G8_SNORM) 211 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_SINT) 212 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_UINT) 213 SF( Y, Y, Y, x, Y, 45, Y, x, 70, BRW_SURFACEFORMAT_R16_UNORM) 214 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16_SNORM) 215 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16_SINT) 216 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16_UINT) 217 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16_FLOAT) 218 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I16_UNORM) 219 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16_UNORM) 220 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A16_UNORM) 221 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_UNORM) 222 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I16_FLOAT) 223 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16_FLOAT) 224 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A16_FLOAT) 225 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_UNORM_SRGB) 226 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM) 227 SF( x, x, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM) 228 SF( x, x, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB) 229 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_SSCALED) 230 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_USCALED) 231/* smpl filt shad CK RT AB VB SO color */ 232 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16_SSCALED) 233 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16_USCALED) 234 SF( Y, Y, x, 45, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R8_UNORM) 235 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8_SNORM) 236 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8_SINT) 237 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8_UINT) 238 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_A8_UNORM) 239 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I8_UNORM) 240 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_L8_UNORM) 241 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P4A4_UNORM) 242 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A4P4_UNORM) 243 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8_SSCALED) 244 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8_USCALED) 245 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8_UNORM_SRGB) 246 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_DXT1_RGB_SRGB) 247 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R1_UINT) 248 SF( Y, Y, x, Y, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_NORMAL) 249 SF( Y, Y, x, Y, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUVY) 250 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC1_UNORM) 251 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC2_UNORM) 252 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC3_UNORM) 253 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC4_UNORM) 254 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC5_UNORM) 255 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC1_UNORM_SRGB) 256 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC2_UNORM_SRGB) 257 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC3_UNORM_SRGB) 258 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_MONO8) 259 SF( Y, Y, x, x, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUV) 260 SF( Y, Y, x, x, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPY) 261 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_DXT1_RGB) 262/* smpl filt shad CK RT AB VB SO color */ 263 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_FXT1) 264 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_UNORM) 265 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_SNORM) 266 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_SSCALED) 267 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_USCALED) 268 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64B64A64_FLOAT) 269 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64B64_FLOAT) 270 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC4_SNORM) 271 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC5_SNORM) 272 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_UNORM) 273 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_SNORM) 274 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_SSCALED) 275 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_USCALED) 276}; 277#undef x 278#undef Y 279 280uint32_t 281brw_format_for_mesa_format(gl_format mesa_format) 282{ 283 /* This table is ordered according to the enum ordering in formats.h. We do 284 * expect that enum to be extended without our explicit initialization 285 * staying in sync, so we initialize to 0 even though 286 * BRW_SURFACEFORMAT_R32G32B32A32_FLOAT happens to also be 0. 287 */ 288 static const uint32_t table[MESA_FORMAT_COUNT] = 289 { 290 [MESA_FORMAT_RGBA8888] = 0, 291 [MESA_FORMAT_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_UNORM, 292 [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM, 293 [MESA_FORMAT_ARGB8888_REV] = 0, 294 [MESA_FORMAT_RGBX8888] = 0, 295 [MESA_FORMAT_RGBX8888_REV] = BRW_SURFACEFORMAT_R8G8B8X8_UNORM, 296 [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM, 297 [MESA_FORMAT_XRGB8888_REV] = 0, 298 [MESA_FORMAT_RGB888] = 0, 299 [MESA_FORMAT_BGR888] = 0, 300 [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM, 301 [MESA_FORMAT_RGB565_REV] = 0, 302 [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM, 303 [MESA_FORMAT_ARGB4444_REV] = 0, 304 [MESA_FORMAT_RGBA5551] = 0, 305 [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM, 306 [MESA_FORMAT_ARGB1555_REV] = 0, 307 [MESA_FORMAT_AL44] = 0, 308 [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM, 309 [MESA_FORMAT_AL88_REV] = 0, 310 [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM, 311 [MESA_FORMAT_AL1616_REV] = 0, 312 [MESA_FORMAT_RGB332] = 0, 313 [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM, 314 [MESA_FORMAT_A16] = BRW_SURFACEFORMAT_A16_UNORM, 315 [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM, 316 [MESA_FORMAT_L16] = BRW_SURFACEFORMAT_L16_UNORM, 317 [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM, 318 [MESA_FORMAT_I16] = BRW_SURFACEFORMAT_I16_UNORM, 319 [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL, 320 [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY, 321 [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM, 322 [MESA_FORMAT_GR88] = BRW_SURFACEFORMAT_R8G8_UNORM, 323 [MESA_FORMAT_RG88] = 0, 324 [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM, 325 [MESA_FORMAT_RG1616] = BRW_SURFACEFORMAT_R16G16_UNORM, 326 [MESA_FORMAT_RG1616_REV] = 0, 327 [MESA_FORMAT_ARGB2101010] = BRW_SURFACEFORMAT_B10G10R10A2_UNORM, 328 [MESA_FORMAT_ABGR2101010_UINT] = BRW_SURFACEFORMAT_R10G10B10A2_UINT, 329 [MESA_FORMAT_Z24_S8] = 0, 330 [MESA_FORMAT_S8_Z24] = 0, 331 [MESA_FORMAT_Z16] = 0, 332 [MESA_FORMAT_X8_Z24] = 0, 333 [MESA_FORMAT_Z24_X8] = 0, 334 [MESA_FORMAT_Z32] = 0, 335 [MESA_FORMAT_S8] = 0, 336 337 [MESA_FORMAT_SRGB8] = 0, 338 [MESA_FORMAT_SRGBA8] = 0, 339 [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB, 340 [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB, 341 [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB, 342 [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB, 343 [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB, 344 [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB, 345 [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB, 346 347 [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1, 348 [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1, 349 [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB, 350 [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM, 351 [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM, 352 [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM, 353 354 [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT, 355 [MESA_FORMAT_RGBA_FLOAT16] = BRW_SURFACEFORMAT_R16G16B16A16_FLOAT, 356 [MESA_FORMAT_RGB_FLOAT32] = 0, 357 [MESA_FORMAT_RGB_FLOAT16] = 0, 358 [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT, 359 [MESA_FORMAT_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_A16_FLOAT, 360 [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT, 361 [MESA_FORMAT_LUMINANCE_FLOAT16] = BRW_SURFACEFORMAT_L16_FLOAT, 362 [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT, 363 [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_L16A16_FLOAT, 364 [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT, 365 [MESA_FORMAT_INTENSITY_FLOAT16] = BRW_SURFACEFORMAT_I16_FLOAT, 366 [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT, 367 [MESA_FORMAT_R_FLOAT16] = BRW_SURFACEFORMAT_R16_FLOAT, 368 [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT, 369 [MESA_FORMAT_RG_FLOAT16] = BRW_SURFACEFORMAT_R16G16_FLOAT, 370 371 [MESA_FORMAT_ALPHA_UINT8] = 0, 372 [MESA_FORMAT_ALPHA_UINT16] = 0, 373 [MESA_FORMAT_ALPHA_UINT32] = 0, 374 [MESA_FORMAT_ALPHA_INT8] = 0, 375 [MESA_FORMAT_ALPHA_INT16] = 0, 376 [MESA_FORMAT_ALPHA_INT32] = 0, 377 378 [MESA_FORMAT_INTENSITY_UINT8] = 0, 379 [MESA_FORMAT_INTENSITY_UINT16] = 0, 380 [MESA_FORMAT_INTENSITY_UINT32] = 0, 381 [MESA_FORMAT_INTENSITY_INT8] = 0, 382 [MESA_FORMAT_INTENSITY_INT16] = 0, 383 [MESA_FORMAT_INTENSITY_INT32] = 0, 384 385 [MESA_FORMAT_LUMINANCE_UINT8] = 0, 386 [MESA_FORMAT_LUMINANCE_UINT16] = 0, 387 [MESA_FORMAT_LUMINANCE_UINT32] = 0, 388 [MESA_FORMAT_LUMINANCE_INT8] = 0, 389 [MESA_FORMAT_LUMINANCE_INT16] = 0, 390 [MESA_FORMAT_LUMINANCE_INT32] = 0, 391 392 [MESA_FORMAT_LUMINANCE_ALPHA_UINT8] = 0, 393 [MESA_FORMAT_LUMINANCE_ALPHA_UINT16] = 0, 394 [MESA_FORMAT_LUMINANCE_ALPHA_UINT32] = 0, 395 [MESA_FORMAT_LUMINANCE_ALPHA_INT8] = 0, 396 [MESA_FORMAT_LUMINANCE_ALPHA_INT16] = 0, 397 [MESA_FORMAT_LUMINANCE_ALPHA_INT32] = 0, 398 399 [MESA_FORMAT_R_INT8] = BRW_SURFACEFORMAT_R8_SINT, 400 [MESA_FORMAT_RG_INT8] = BRW_SURFACEFORMAT_R8G8_SINT, 401 [MESA_FORMAT_RGB_INT8] = 0, 402 [MESA_FORMAT_RGBA_INT8] = BRW_SURFACEFORMAT_R8G8B8A8_SINT, 403 [MESA_FORMAT_R_INT16] = BRW_SURFACEFORMAT_R16_SINT, 404 [MESA_FORMAT_RG_INT16] = BRW_SURFACEFORMAT_R16G16_SINT, 405 [MESA_FORMAT_RGB_INT16] = 0, 406 [MESA_FORMAT_RGBA_INT16] = BRW_SURFACEFORMAT_R16G16B16A16_SINT, 407 [MESA_FORMAT_R_INT32] = BRW_SURFACEFORMAT_R32_SINT, 408 [MESA_FORMAT_RG_INT32] = BRW_SURFACEFORMAT_R32G32_SINT, 409 [MESA_FORMAT_RGB_INT32] = BRW_SURFACEFORMAT_R32G32B32_SINT, 410 [MESA_FORMAT_RGBA_INT32] = BRW_SURFACEFORMAT_R32G32B32A32_SINT, 411 412 [MESA_FORMAT_R_UINT8] = BRW_SURFACEFORMAT_R8_UINT, 413 [MESA_FORMAT_RG_UINT8] = BRW_SURFACEFORMAT_R8G8_UINT, 414 [MESA_FORMAT_RGB_UINT8] = 0, 415 [MESA_FORMAT_RGBA_UINT8] = BRW_SURFACEFORMAT_R8G8B8A8_UINT, 416 [MESA_FORMAT_R_UINT16] = BRW_SURFACEFORMAT_R16_UINT, 417 [MESA_FORMAT_RG_UINT16] = BRW_SURFACEFORMAT_R16G16_UINT, 418 [MESA_FORMAT_RGB_UINT16] = 0, 419 [MESA_FORMAT_RGBA_UINT16] = BRW_SURFACEFORMAT_R16G16B16A16_UINT, 420 [MESA_FORMAT_R_UINT32] = BRW_SURFACEFORMAT_R32_UINT, 421 [MESA_FORMAT_RG_UINT32] = BRW_SURFACEFORMAT_R32G32_UINT, 422 [MESA_FORMAT_RGB_UINT32] = BRW_SURFACEFORMAT_R32G32B32_UINT, 423 [MESA_FORMAT_RGBA_UINT32] = BRW_SURFACEFORMAT_R32G32B32A32_UINT, 424 425 [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM, 426 [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM, 427 [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM, 428 [MESA_FORMAT_SIGNED_RGBX8888] = 0, 429 [MESA_FORMAT_SIGNED_RGBA8888] = 0, 430 [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM, 431 [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM, 432 [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM, 433 [MESA_FORMAT_SIGNED_RGB_16] = 0, 434 [MESA_FORMAT_SIGNED_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_SNORM, 435 [MESA_FORMAT_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_UNORM, 436 437 [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM, 438 [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM, 439 [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM, 440 [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM, 441 442 [MESA_FORMAT_L_LATC1] = 0, 443 [MESA_FORMAT_SIGNED_L_LATC1] = 0, 444 [MESA_FORMAT_LA_LATC2] = 0, 445 [MESA_FORMAT_SIGNED_LA_LATC2] = 0, 446 447 [MESA_FORMAT_SIGNED_A8] = 0, 448 [MESA_FORMAT_SIGNED_L8] = 0, 449 [MESA_FORMAT_SIGNED_AL88] = 0, 450 [MESA_FORMAT_SIGNED_I8] = 0, 451 [MESA_FORMAT_SIGNED_A16] = 0, 452 [MESA_FORMAT_SIGNED_L16] = 0, 453 [MESA_FORMAT_SIGNED_AL1616] = 0, 454 [MESA_FORMAT_SIGNED_I16] = 0, 455 456 [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP, 457 [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT, 458 459 [MESA_FORMAT_Z32_FLOAT] = 0, 460 [MESA_FORMAT_Z32_FLOAT_X24S8] = 0, 461 }; 462 assert(mesa_format < MESA_FORMAT_COUNT); 463 return table[mesa_format]; 464} 465 466void 467brw_init_surface_formats(struct brw_context *brw) 468{ 469 struct intel_context *intel = &brw->intel; 470 struct gl_context *ctx = &intel->ctx; 471 int gen; 472 gl_format format; 473 474 gen = intel->gen * 10; 475 if (intel->is_g4x) 476 gen += 5; 477 478 for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) { 479 uint32_t texture, render; 480 const struct surface_format_info *rinfo, *tinfo; 481 bool is_integer = _mesa_is_format_integer_color(format); 482 483 render = texture = brw_format_for_mesa_format(format); 484 tinfo = &surface_formats[texture]; 485 486 /* The value of BRW_SURFACEFORMAT_R32G32B32A32_FLOAT is 0, so don't skip 487 * it. 488 */ 489 if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32) 490 continue; 491 492 if (gen >= tinfo->sampling && (gen >= tinfo->filtering || is_integer)) 493 ctx->TextureFormatSupported[format] = true; 494 495 /* Re-map some render target formats to make them supported when they 496 * wouldn't be using their format for texturing. 497 */ 498 switch (render) { 499 /* For these formats, we just need to read/write the first 500 * channel into R, which is to say that we just treat them as 501 * GL_RED. 502 */ 503 case BRW_SURFACEFORMAT_I32_FLOAT: 504 case BRW_SURFACEFORMAT_L32_FLOAT: 505 render = BRW_SURFACEFORMAT_R32_FLOAT; 506 break; 507 case BRW_SURFACEFORMAT_I16_FLOAT: 508 case BRW_SURFACEFORMAT_L16_FLOAT: 509 render = BRW_SURFACEFORMAT_R16_FLOAT; 510 break; 511 case BRW_SURFACEFORMAT_B8G8R8X8_UNORM: 512 /* XRGB is handled as ARGB because the chips in this family 513 * cannot render to XRGB targets. This means that we have to 514 * mask writes to alpha (ala glColorMask) and reconfigure the 515 * alpha blending hardware to use GL_ONE (or GL_ZERO) for 516 * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is 517 * used. 518 */ 519 render = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; 520 break; 521 } 522 523 rinfo = &surface_formats[render]; 524 525 /* Note that GL_EXT_texture_integer says that blending doesn't occur for 526 * integer, so we don't need hardware support for blending on it. Other 527 * than that, GL in general requires alpha blending for render targets, 528 * even though we don't support it for some formats. 529 */ 530 if (gen >= rinfo->render_target && 531 (gen >= rinfo->alpha_blend || is_integer)) { 532 brw->render_target_format[format] = render; 533 brw->format_supported_as_render_target[format] = true; 534 } 535 } 536 537 /* We will check this table for FBO completeness, but the surface format 538 * table above only covered color rendering. 539 */ 540 brw->format_supported_as_render_target[MESA_FORMAT_S8_Z24] = true; 541 brw->format_supported_as_render_target[MESA_FORMAT_X8_Z24] = true; 542 brw->format_supported_as_render_target[MESA_FORMAT_S8] = true; 543 brw->format_supported_as_render_target[MESA_FORMAT_Z16] = true; 544 brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT] = true; 545 brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT_X24S8] = true; 546 547 /* We remap depth formats to a supported texturing format in 548 * translate_tex_format(). 549 */ 550 ctx->TextureFormatSupported[MESA_FORMAT_S8_Z24] = true; 551 ctx->TextureFormatSupported[MESA_FORMAT_X8_Z24] = true; 552 ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT] = true; 553 ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT_X24S8] = true; 554 ctx->TextureFormatSupported[MESA_FORMAT_Z16] = true; 555 556 /* On hardware that lacks support for ETC1, we map ETC1 to RGBX 557 * during glCompressedTexImage2D(). See intel_mipmap_tree::wraps_etc1. 558 */ 559 ctx->TextureFormatSupported[MESA_FORMAT_ETC1_RGB8] = true; 560} 561 562bool 563brw_render_target_supported(struct intel_context *intel, 564 struct gl_renderbuffer *rb) 565{ 566 struct brw_context *brw = brw_context(&intel->ctx); 567 gl_format format = rb->Format; 568 569 /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means 570 * we would consider them renderable even though we don't have surface 571 * support for their alpha behavior and don't have the blending unit 572 * available to fake it like we do for XRGB8888. Force them to being 573 * unsupported. 574 */ 575 if ((rb->_BaseFormat != GL_RGBA && 576 rb->_BaseFormat != GL_RG && 577 rb->_BaseFormat != GL_RED) && _mesa_is_format_integer_color(format)) 578 return false; 579 580 /* Under some conditions, MSAA is not supported for formats whose width is 581 * more than 64 bits. 582 */ 583 if (rb->NumSamples > 0 && _mesa_get_format_bytes(format) > 8) { 584 /* Gen6: MSAA on >64 bit formats is unsupported. */ 585 if (intel->gen <= 6) 586 return false; 587 588 /* Gen7: 8x MSAA on >64 bit formats is unsupported. */ 589 if (rb->NumSamples >= 8) 590 return false; 591 } 592 593 return brw->format_supported_as_render_target[format]; 594} 595 596GLuint 597translate_tex_format(gl_format mesa_format, 598 GLenum internal_format, 599 GLenum depth_mode, 600 GLenum srgb_decode) 601{ 602 if (srgb_decode == GL_SKIP_DECODE_EXT) 603 mesa_format = _mesa_get_srgb_format_linear(mesa_format); 604 605 switch( mesa_format ) { 606 607 case MESA_FORMAT_Z16: 608 return BRW_SURFACEFORMAT_I16_UNORM; 609 610 case MESA_FORMAT_S8_Z24: 611 case MESA_FORMAT_X8_Z24: 612 return BRW_SURFACEFORMAT_I24X8_UNORM; 613 614 case MESA_FORMAT_Z32_FLOAT: 615 return BRW_SURFACEFORMAT_I32_FLOAT; 616 617 case MESA_FORMAT_Z32_FLOAT_X24S8: 618 return BRW_SURFACEFORMAT_R32G32_FLOAT; 619 620 case MESA_FORMAT_RGBA_FLOAT32: 621 /* The value of this BRW_SURFACEFORMAT is 0, which tricks the 622 * assertion below. 623 */ 624 return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT; 625 626 default: 627 assert(brw_format_for_mesa_format(mesa_format) != 0); 628 return brw_format_for_mesa_format(mesa_format); 629 } 630} 631 632uint32_t 633brw_get_surface_tiling_bits(uint32_t tiling) 634{ 635 switch (tiling) { 636 case I915_TILING_X: 637 return BRW_SURFACE_TILED; 638 case I915_TILING_Y: 639 return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y; 640 default: 641 return 0; 642 } 643} 644 645 646uint32_t 647brw_get_surface_num_multisamples(unsigned num_samples) 648{ 649 if (num_samples > 1) 650 return BRW_SURFACE_MULTISAMPLECOUNT_4; 651 else 652 return BRW_SURFACE_MULTISAMPLECOUNT_1; 653} 654 655 656static void 657brw_update_buffer_texture_surface(struct gl_context *ctx, 658 unsigned unit, 659 uint32_t *binding_table, 660 unsigned surf_index) 661{ 662 struct brw_context *brw = brw_context(ctx); 663 struct intel_context *intel = &brw->intel; 664 struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current; 665 uint32_t *surf; 666 struct intel_buffer_object *intel_obj = 667 intel_buffer_object(tObj->BufferObject); 668 drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL; 669 gl_format format = tObj->_BufferObjectFormat; 670 uint32_t brw_format = brw_format_for_mesa_format(format); 671 int texel_size = _mesa_get_format_bytes(format); 672 673 if (brw_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) { 674 _mesa_problem(NULL, "bad format %s for texture buffer\n", 675 _mesa_get_format_name(format)); 676 } 677 678 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 679 6 * 4, 32, &binding_table[surf_index]); 680 681 surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT | 682 (brw_format_for_mesa_format(format) << BRW_SURFACE_FORMAT_SHIFT)); 683 684 if (intel->gen >= 6) 685 surf[0] |= BRW_SURFACE_RC_READ_WRITE; 686 687 if (bo) { 688 surf[1] = bo->offset; /* reloc */ 689 690 /* Emit relocation to surface contents. */ 691 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 692 binding_table[surf_index] + 4, 693 bo, 0, I915_GEM_DOMAIN_SAMPLER, 0); 694 695 int w = intel_obj->Base.Size / texel_size; 696 surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT | 697 ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT); 698 surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT | 699 (texel_size - 1) << BRW_SURFACE_PITCH_SHIFT); 700 } else { 701 surf[1] = 0; 702 surf[2] = 0; 703 surf[3] = 0; 704 } 705 706 surf[4] = 0; 707 surf[5] = 0; 708} 709 710static void 711brw_update_texture_surface(struct gl_context *ctx, 712 unsigned unit, 713 uint32_t *binding_table, 714 unsigned surf_index) 715{ 716 struct brw_context *brw = brw_context(ctx); 717 struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current; 718 struct intel_texture_object *intelObj = intel_texture_object(tObj); 719 struct intel_mipmap_tree *mt = intelObj->mt; 720 struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel]; 721 struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit); 722 uint32_t *surf; 723 int width, height, depth; 724 725 if (tObj->Target == GL_TEXTURE_BUFFER) { 726 brw_update_buffer_texture_surface(ctx, unit, binding_table, surf_index); 727 return; 728 } 729 730 intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth); 731 732 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 733 6 * 4, 32, &binding_table[surf_index]); 734 735 surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT | 736 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT | 737 BRW_SURFACE_CUBEFACE_ENABLES | 738 (translate_tex_format(mt->format, 739 firstImage->InternalFormat, 740 tObj->DepthMode, 741 sampler->sRGBDecode) << 742 BRW_SURFACE_FORMAT_SHIFT)); 743 744 surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */ 745 746 surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT | 747 (width - 1) << BRW_SURFACE_WIDTH_SHIFT | 748 (height - 1) << BRW_SURFACE_HEIGHT_SHIFT); 749 750 surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) | 751 (depth - 1) << BRW_SURFACE_DEPTH_SHIFT | 752 ((intelObj->mt->region->pitch * intelObj->mt->cpp) - 1) << 753 BRW_SURFACE_PITCH_SHIFT); 754 755 surf[4] = 0; 756 757 surf[5] = (mt->align_h == 4) ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0; 758 759 /* Emit relocation to surface contents */ 760 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 761 binding_table[surf_index] + 4, 762 intelObj->mt->region->bo, 763 intelObj->mt->offset, 764 I915_GEM_DOMAIN_SAMPLER, 0); 765} 766 767/** 768 * Create the constant buffer surface. Vertex/fragment shader constants will be 769 * read from this buffer with Data Port Read instructions/messages. 770 */ 771void 772brw_create_constant_surface(struct brw_context *brw, 773 drm_intel_bo *bo, 774 uint32_t offset, 775 int width, 776 uint32_t *out_offset) 777{ 778 struct intel_context *intel = &brw->intel; 779 const GLint w = width - 1; 780 uint32_t *surf; 781 782 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 783 6 * 4, 32, out_offset); 784 785 surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT | 786 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT | 787 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT); 788 789 if (intel->gen >= 6) 790 surf[0] |= BRW_SURFACE_RC_READ_WRITE; 791 792 surf[1] = bo->offset + offset; /* reloc */ 793 794 surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT | 795 ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT); 796 797 surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT | 798 (16 - 1) << BRW_SURFACE_PITCH_SHIFT); /* ignored */ 799 800 surf[4] = 0; 801 surf[5] = 0; 802 803 /* Emit relocation to surface contents. Section 5.1.1 of the gen4 804 * bspec ("Data Cache") says that the data cache does not exist as 805 * a separate cache and is just the sampler cache. 806 */ 807 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 808 *out_offset + 4, 809 bo, offset, 810 I915_GEM_DOMAIN_SAMPLER, 0); 811} 812 813/** 814 * Set up a binding table entry for use by stream output logic (transform 815 * feedback). 816 * 817 * buffer_size_minus_1 must me less than BRW_MAX_NUM_BUFFER_ENTRIES. 818 */ 819void 820brw_update_sol_surface(struct brw_context *brw, 821 struct gl_buffer_object *buffer_obj, 822 uint32_t *out_offset, unsigned num_vector_components, 823 unsigned stride_dwords, unsigned offset_dwords) 824{ 825 struct intel_context *intel = &brw->intel; 826 struct intel_buffer_object *intel_bo = intel_buffer_object(buffer_obj); 827 drm_intel_bo *bo = 828 intel_bufferobj_buffer(intel, intel_bo, INTEL_WRITE_PART); 829 uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, 830 out_offset); 831 uint32_t pitch_minus_1 = 4*stride_dwords - 1; 832 uint32_t offset_bytes = 4 * offset_dwords; 833 size_t size_dwords = buffer_obj->Size / 4; 834 uint32_t buffer_size_minus_1, width, height, depth, surface_format; 835 836 /* FIXME: can we rely on core Mesa to ensure that the buffer isn't 837 * too big to map using a single binding table entry? 838 */ 839 assert((size_dwords - offset_dwords) / stride_dwords 840 <= BRW_MAX_NUM_BUFFER_ENTRIES); 841 842 if (size_dwords > offset_dwords + num_vector_components) { 843 /* There is room for at least 1 transform feedback output in the buffer. 844 * Compute the number of additional transform feedback outputs the 845 * buffer has room for. 846 */ 847 buffer_size_minus_1 = 848 (size_dwords - offset_dwords - num_vector_components) / stride_dwords; 849 } else { 850 /* There isn't even room for a single transform feedback output in the 851 * buffer. We can't configure the binding table entry to prevent output 852 * entirely; we'll have to rely on the geometry shader to detect 853 * overflow. But to minimize the damage in case of a bug, set up the 854 * binding table entry to just allow a single output. 855 */ 856 buffer_size_minus_1 = 0; 857 } 858 width = buffer_size_minus_1 & 0x7f; 859 height = (buffer_size_minus_1 & 0xfff80) >> 7; 860 depth = (buffer_size_minus_1 & 0x7f00000) >> 20; 861 862 switch (num_vector_components) { 863 case 1: 864 surface_format = BRW_SURFACEFORMAT_R32_FLOAT; 865 break; 866 case 2: 867 surface_format = BRW_SURFACEFORMAT_R32G32_FLOAT; 868 break; 869 case 3: 870 surface_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT; 871 break; 872 case 4: 873 surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT; 874 break; 875 default: 876 assert(!"Invalid vector size for transform feedback output"); 877 surface_format = BRW_SURFACEFORMAT_R32_FLOAT; 878 break; 879 } 880 881 surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT | 882 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT | 883 surface_format << BRW_SURFACE_FORMAT_SHIFT | 884 BRW_SURFACE_RC_READ_WRITE; 885 surf[1] = bo->offset + offset_bytes; /* reloc */ 886 surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT | 887 height << BRW_SURFACE_HEIGHT_SHIFT); 888 surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT | 889 pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT); 890 surf[4] = 0; 891 surf[5] = 0; 892 893 /* Emit relocation to surface contents. */ 894 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 895 *out_offset + 4, 896 bo, offset_bytes, 897 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); 898} 899 900/* Creates a new WM constant buffer reflecting the current fragment program's 901 * constants, if needed by the fragment program. 902 * 903 * Otherwise, constants go through the CURBEs using the brw_constant_buffer 904 * state atom. 905 */ 906static void 907brw_upload_wm_pull_constants(struct brw_context *brw) 908{ 909 struct gl_context *ctx = &brw->intel.ctx; 910 struct intel_context *intel = &brw->intel; 911 /* BRW_NEW_FRAGMENT_PROGRAM */ 912 struct brw_fragment_program *fp = 913 (struct brw_fragment_program *) brw->fragment_program; 914 struct gl_program_parameter_list *params = fp->program.Base.Parameters; 915 const int size = brw->wm.prog_data->nr_pull_params * sizeof(float); 916 const int surf_index = SURF_INDEX_FRAG_CONST_BUFFER; 917 float *constants; 918 unsigned int i; 919 920 _mesa_load_state_parameters(ctx, params); 921 922 /* CACHE_NEW_WM_PROG */ 923 if (brw->wm.prog_data->nr_pull_params == 0) { 924 if (brw->wm.const_bo) { 925 drm_intel_bo_unreference(brw->wm.const_bo); 926 brw->wm.const_bo = NULL; 927 brw->wm.surf_offset[surf_index] = 0; 928 brw->state.dirty.brw |= BRW_NEW_SURFACES; 929 } 930 return; 931 } 932 933 drm_intel_bo_unreference(brw->wm.const_bo); 934 brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo", 935 size, 64); 936 937 /* _NEW_PROGRAM_CONSTANTS */ 938 drm_intel_gem_bo_map_gtt(brw->wm.const_bo); 939 constants = brw->wm.const_bo->virtual; 940 for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) { 941 constants[i] = *brw->wm.prog_data->pull_param[i]; 942 } 943 drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo); 944 945 intel->vtbl.create_constant_surface(brw, brw->wm.const_bo, 0, 946 params->NumParameters, 947 &brw->wm.surf_offset[surf_index]); 948 949 brw->state.dirty.brw |= BRW_NEW_SURFACES; 950} 951 952const struct brw_tracked_state brw_wm_pull_constants = { 953 .dirty = { 954 .mesa = (_NEW_PROGRAM_CONSTANTS), 955 .brw = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM), 956 .cache = CACHE_NEW_WM_PROG, 957 }, 958 .emit = brw_upload_wm_pull_constants, 959}; 960 961static void 962brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit) 963{ 964 /* From the Sandy bridge PRM, Vol4 Part1 p71 (Surface Type: Programming 965 * Notes): 966 * 967 * A null surface will be used in instances where an actual surface is 968 * not bound. When a write message is generated to a null surface, no 969 * actual surface is written to. When a read message (including any 970 * sampling engine message) is generated to a null surface, the result 971 * is all zeros. Note that a null surface type is allowed to be used 972 * with all messages, even if it is not specificially indicated as 973 * supported. All of the remaining fields in surface state are ignored 974 * for null surfaces, with the following exceptions: 975 * 976 * - [DevSNB+]: Width, Height, Depth, and LOD fields must match the 977 * depth buffer’s corresponding state for all render target surfaces, 978 * including null. 979 * 980 * - Surface Format must be R8G8B8A8_UNORM. 981 */ 982 struct intel_context *intel = &brw->intel; 983 struct gl_context *ctx = &intel->ctx; 984 uint32_t *surf; 985 unsigned surface_type = BRW_SURFACE_NULL; 986 drm_intel_bo *bo = NULL; 987 unsigned pitch_minus_1 = 0; 988 uint32_t multisampling_state = 0; 989 990 /* _NEW_BUFFERS */ 991 const struct gl_framebuffer *fb = ctx->DrawBuffer; 992 993 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 994 6 * 4, 32, &brw->wm.surf_offset[unit]); 995 996 if (fb->Visual.samples > 1) { 997 /* On Gen6, null render targets seem to cause GPU hangs when 998 * multisampling. So work around this problem by rendering into dummy 999 * color buffer. 1000 * 1001 * To decrease the amount of memory needed by the workaround buffer, we 1002 * set its pitch to 128 bytes (the width of a Y tile). This means that 1003 * the amount of memory needed for the workaround buffer is 1004 * (width_in_tiles + height_in_tiles - 1) tiles. 1005 * 1006 * Note that since the workaround buffer will be interpreted by the 1007 * hardware as an interleaved multisampled buffer, we need to compute 1008 * width_in_tiles and height_in_tiles by dividing the width and height 1009 * by 16 rather than the normal Y-tile size of 32. 1010 */ 1011 unsigned width_in_tiles = ALIGN(fb->Width, 16) / 16; 1012 unsigned height_in_tiles = ALIGN(fb->Height, 16) / 16; 1013 unsigned size_needed = (width_in_tiles + height_in_tiles - 1) * 4096; 1014 brw_get_scratch_bo(intel, &brw->wm.multisampled_null_render_target_bo, 1015 size_needed); 1016 bo = brw->wm.multisampled_null_render_target_bo; 1017 surface_type = BRW_SURFACE_2D; 1018 pitch_minus_1 = 127; 1019 multisampling_state = 1020 brw_get_surface_num_multisamples(fb->Visual.samples); 1021 } 1022 1023 surf[0] = (surface_type << BRW_SURFACE_TYPE_SHIFT | 1024 BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT); 1025 if (intel->gen < 6) { 1026 surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT | 1027 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT | 1028 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT | 1029 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT); 1030 } 1031 surf[1] = bo ? bo->offset : 0; 1032 surf[2] = ((fb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT | 1033 (fb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT); 1034 1035 /* From Sandy bridge PRM, Vol4 Part1 p82 (Tiled Surface: Programming 1036 * Notes): 1037 * 1038 * If Surface Type is SURFTYPE_NULL, this field must be TRUE 1039 */ 1040 surf[3] = (BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y | 1041 pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT); 1042 surf[4] = multisampling_state; 1043 surf[5] = 0; 1044 1045 if (bo) { 1046 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 1047 brw->wm.surf_offset[unit] + 4, 1048 bo, 0, 1049 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); 1050 } 1051} 1052 1053/** 1054 * Sets up a surface state structure to point at the given region. 1055 * While it is only used for the front/back buffer currently, it should be 1056 * usable for further buffers when doing ARB_draw_buffer support. 1057 */ 1058static void 1059brw_update_renderbuffer_surface(struct brw_context *brw, 1060 struct gl_renderbuffer *rb, 1061 unsigned int unit) 1062{ 1063 struct intel_context *intel = &brw->intel; 1064 struct gl_context *ctx = &intel->ctx; 1065 struct intel_renderbuffer *irb = intel_renderbuffer(rb); 1066 struct intel_mipmap_tree *mt = irb->mt; 1067 struct intel_region *region; 1068 uint32_t *surf; 1069 uint32_t tile_x, tile_y; 1070 uint32_t format = 0; 1071 gl_format rb_format = intel_rb_format(irb); 1072 1073 if (irb->tex_image && !brw->has_surface_tile_offset) { 1074 intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y); 1075 1076 if (tile_x != 0 || tile_y != 0) { 1077 /* Original gen4 hardware couldn't draw to a non-tile-aligned 1078 * destination in a miptree unless you actually setup your renderbuffer 1079 * as a miptree and used the fragile lod/array_index/etc. controls to 1080 * select the image. So, instead, we just make a new single-level 1081 * miptree and render into that. 1082 */ 1083 struct intel_context *intel = intel_context(ctx); 1084 struct intel_texture_image *intel_image = 1085 intel_texture_image(irb->tex_image); 1086 struct intel_mipmap_tree *new_mt; 1087 int width, height, depth; 1088 1089 intel_miptree_get_dimensions_for_image(irb->tex_image, &width, &height, &depth); 1090 1091 new_mt = intel_miptree_create(intel, irb->tex_image->TexObject->Target, 1092 intel_image->base.Base.TexFormat, 1093 intel_image->base.Base.Level, 1094 intel_image->base.Base.Level, 1095 width, height, depth, 1096 true, 1097 0 /* num_samples */, 1098 INTEL_MSAA_LAYOUT_NONE); 1099 1100 intel_miptree_copy_teximage(intel, intel_image, new_mt); 1101 intel_miptree_reference(&irb->mt, intel_image->mt); 1102 intel_renderbuffer_set_draw_offset(irb); 1103 intel_miptree_release(&new_mt); 1104 1105 mt = irb->mt; 1106 } 1107 } 1108 1109 region = irb->mt->region; 1110 1111 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 1112 6 * 4, 32, &brw->wm.surf_offset[unit]); 1113 1114 switch (rb_format) { 1115 case MESA_FORMAT_SARGB8: 1116 /* _NEW_BUFFERS 1117 * 1118 * Without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB surfaces to the 1119 * blend/update as sRGB. 1120 */ 1121 if (ctx->Color.sRGBEnabled) 1122 format = brw_format_for_mesa_format(rb_format); 1123 else 1124 format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; 1125 break; 1126 default: 1127 format = brw->render_target_format[rb_format]; 1128 if (unlikely(!brw->format_supported_as_render_target[rb_format])) { 1129 _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n", 1130 __FUNCTION__, _mesa_get_format_name(rb_format)); 1131 } 1132 break; 1133 } 1134 1135 surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT | 1136 format << BRW_SURFACE_FORMAT_SHIFT); 1137 1138 /* reloc */ 1139 surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) + 1140 region->bo->offset); 1141 1142 surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT | 1143 (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT); 1144 1145 surf[3] = (brw_get_surface_tiling_bits(region->tiling) | 1146 ((region->pitch * region->cpp) - 1) << BRW_SURFACE_PITCH_SHIFT); 1147 1148 surf[4] = brw_get_surface_num_multisamples(mt->num_samples); 1149 1150 assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0)); 1151 /* Note that the low bits of these fields are missing, so 1152 * there's the possibility of getting in trouble. 1153 */ 1154 assert(tile_x % 4 == 0); 1155 assert(tile_y % 2 == 0); 1156 surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT | 1157 (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT | 1158 (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0)); 1159 1160 if (intel->gen < 6) { 1161 /* _NEW_COLOR */ 1162 if (!ctx->Color.ColorLogicOpEnabled && 1163 (ctx->Color.BlendEnabled & (1 << unit))) 1164 surf[0] |= BRW_SURFACE_BLEND_ENABLED; 1165 1166 if (!ctx->Color.ColorMask[unit][0]) 1167 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT; 1168 if (!ctx->Color.ColorMask[unit][1]) 1169 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT; 1170 if (!ctx->Color.ColorMask[unit][2]) 1171 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT; 1172 1173 /* As mentioned above, disable writes to the alpha component when the 1174 * renderbuffer is XRGB. 1175 */ 1176 if (ctx->DrawBuffer->Visual.alphaBits == 0 || 1177 !ctx->Color.ColorMask[unit][3]) { 1178 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT; 1179 } 1180 } 1181 1182 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 1183 brw->wm.surf_offset[unit] + 4, 1184 region->bo, 1185 surf[1] - region->bo->offset, 1186 I915_GEM_DOMAIN_RENDER, 1187 I915_GEM_DOMAIN_RENDER); 1188} 1189 1190/** 1191 * Construct SURFACE_STATE objects for renderbuffers/draw buffers. 1192 */ 1193static void 1194brw_update_renderbuffer_surfaces(struct brw_context *brw) 1195{ 1196 struct intel_context *intel = &brw->intel; 1197 struct gl_context *ctx = &brw->intel.ctx; 1198 GLuint i; 1199 1200 /* _NEW_BUFFERS | _NEW_COLOR */ 1201 /* Update surfaces for drawing buffers */ 1202 if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) { 1203 for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) { 1204 if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) { 1205 intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], i); 1206 } else { 1207 intel->vtbl.update_null_renderbuffer_surface(brw, i); 1208 } 1209 } 1210 } else { 1211 intel->vtbl.update_null_renderbuffer_surface(brw, 0); 1212 } 1213 brw->state.dirty.brw |= BRW_NEW_SURFACES; 1214} 1215 1216const struct brw_tracked_state brw_renderbuffer_surfaces = { 1217 .dirty = { 1218 .mesa = (_NEW_COLOR | 1219 _NEW_BUFFERS), 1220 .brw = BRW_NEW_BATCH, 1221 .cache = 0 1222 }, 1223 .emit = brw_update_renderbuffer_surfaces, 1224}; 1225 1226const struct brw_tracked_state gen6_renderbuffer_surfaces = { 1227 .dirty = { 1228 .mesa = _NEW_BUFFERS, 1229 .brw = BRW_NEW_BATCH, 1230 .cache = 0 1231 }, 1232 .emit = brw_update_renderbuffer_surfaces, 1233}; 1234 1235/** 1236 * Construct SURFACE_STATE objects for enabled textures. 1237 */ 1238static void 1239brw_update_texture_surfaces(struct brw_context *brw) 1240{ 1241 struct gl_context *ctx = &brw->intel.ctx; 1242 1243 for (unsigned i = 0; i < BRW_MAX_TEX_UNIT; i++) { 1244 const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i]; 1245 const GLuint surf = SURF_INDEX_TEXTURE(i); 1246 1247 /* _NEW_TEXTURE */ 1248 if (texUnit->_ReallyEnabled) { 1249 brw->intel.vtbl.update_texture_surface(ctx, i, brw->wm.surf_offset, surf); 1250 } else { 1251 brw->wm.surf_offset[surf] = 0; 1252 } 1253 1254 /* For now, just mirror the texture setup to the VS slots. */ 1255 brw->vs.surf_offset[SURF_INDEX_VS_TEXTURE(i)] = 1256 brw->wm.surf_offset[surf]; 1257 } 1258 1259 brw->state.dirty.brw |= BRW_NEW_SURFACES; 1260} 1261 1262const struct brw_tracked_state brw_texture_surfaces = { 1263 .dirty = { 1264 .mesa = _NEW_TEXTURE, 1265 .brw = BRW_NEW_BATCH, 1266 .cache = 0 1267 }, 1268 .emit = brw_update_texture_surfaces, 1269}; 1270 1271void 1272brw_upload_ubo_surfaces(struct brw_context *brw, 1273 struct gl_shader *shader, 1274 uint32_t *surf_offsets) 1275{ 1276 struct gl_context *ctx = &brw->intel.ctx; 1277 struct intel_context *intel = &brw->intel; 1278 1279 if (!shader) 1280 return; 1281 1282 for (int i = 0; i < shader->NumUniformBlocks; i++) { 1283 struct gl_uniform_buffer_binding *binding; 1284 struct intel_buffer_object *intel_bo; 1285 1286 binding = &ctx->UniformBufferBindings[shader->UniformBlocks[i].Binding]; 1287 intel_bo = intel_buffer_object(binding->BufferObject); 1288 drm_intel_bo *bo = intel_bufferobj_buffer(intel, intel_bo, INTEL_READ); 1289 1290 /* Because behavior for referencing outside of the binding's size in the 1291 * glBindBufferRange case is undefined, we can just bind the whole buffer 1292 * glBindBufferBase wants and be a correct implementation. 1293 */ 1294 int size = bo->size - binding->Offset; 1295 size = ALIGN(size, 16) / 16; /* The interface takes a number of vec4s */ 1296 1297 intel->vtbl.create_constant_surface(brw, bo, binding->Offset, 1298 size, 1299 &surf_offsets[i]); 1300 } 1301 1302 if (shader->NumUniformBlocks) 1303 brw->state.dirty.brw |= BRW_NEW_SURFACES; 1304} 1305 1306static void 1307brw_upload_wm_ubo_surfaces(struct brw_context *brw) 1308{ 1309 struct gl_context *ctx = &brw->intel.ctx; 1310 /* _NEW_PROGRAM */ 1311 struct gl_shader_program *prog = ctx->Shader._CurrentFragmentProgram; 1312 1313 if (!prog) 1314 return; 1315 1316 brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT], 1317 &brw->wm.surf_offset[SURF_INDEX_WM_UBO(0)]); 1318} 1319 1320const struct brw_tracked_state brw_wm_ubo_surfaces = { 1321 .dirty = { 1322 .mesa = (_NEW_PROGRAM | 1323 _NEW_BUFFER_OBJECT), 1324 .brw = BRW_NEW_BATCH, 1325 .cache = 0, 1326 }, 1327 .emit = brw_upload_wm_ubo_surfaces, 1328}; 1329 1330/** 1331 * Constructs the binding table for the WM surface state, which maps unit 1332 * numbers to surface state objects. 1333 */ 1334static void 1335brw_upload_wm_binding_table(struct brw_context *brw) 1336{ 1337 uint32_t *bind; 1338 int i; 1339 1340 /* Might want to calculate nr_surfaces first, to avoid taking up so much 1341 * space for the binding table. 1342 */ 1343 bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE, 1344 sizeof(uint32_t) * BRW_MAX_WM_SURFACES, 1345 32, &brw->wm.bind_bo_offset); 1346 1347 /* BRW_NEW_SURFACES */ 1348 for (i = 0; i < BRW_MAX_WM_SURFACES; i++) { 1349 bind[i] = brw->wm.surf_offset[i]; 1350 } 1351 1352 brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE; 1353} 1354 1355const struct brw_tracked_state brw_wm_binding_table = { 1356 .dirty = { 1357 .mesa = 0, 1358 .brw = (BRW_NEW_BATCH | 1359 BRW_NEW_SURFACES), 1360 .cache = 0 1361 }, 1362 .emit = brw_upload_wm_binding_table, 1363}; 1364 1365void 1366gen4_init_vtable_surface_functions(struct brw_context *brw) 1367{ 1368 struct intel_context *intel = &brw->intel; 1369 1370 intel->vtbl.update_texture_surface = brw_update_texture_surface; 1371 intel->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface; 1372 intel->vtbl.update_null_renderbuffer_surface = 1373 brw_update_null_renderbuffer_surface; 1374 intel->vtbl.create_constant_surface = brw_create_constant_surface; 1375} 1376