brw_wm_surface_state.c revision b3900ed5ad9bd5df112490dd2b5d2c17d6124067
1/* 2 Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 4 develop this 3D driver. 5 6 Permission is hereby granted, free of charge, to any person obtaining 7 a copy of this software and associated documentation files (the 8 "Software"), to deal in the Software without restriction, including 9 without limitation the rights to use, copy, modify, merge, publish, 10 distribute, sublicense, and/or sell copies of the Software, and to 11 permit persons to whom the Software is furnished to do so, subject to 12 the following conditions: 13 14 The above copyright notice and this permission notice (including the 15 next paragraph) shall be included in all copies or substantial 16 portions of the Software. 17 18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 26 **********************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 33#include "main/mtypes.h" 34#include "main/samplerobj.h" 35#include "program/prog_parameter.h" 36 37#include "intel_mipmap_tree.h" 38#include "intel_batchbuffer.h" 39#include "intel_tex.h" 40#include "intel_fbo.h" 41#include "intel_buffer_objects.h" 42 43#include "brw_context.h" 44#include "brw_state.h" 45#include "brw_defines.h" 46#include "brw_wm.h" 47 48GLuint 49translate_tex_target(GLenum target) 50{ 51 switch (target) { 52 case GL_TEXTURE_1D: 53 case GL_TEXTURE_1D_ARRAY_EXT: 54 return BRW_SURFACE_1D; 55 56 case GL_TEXTURE_RECTANGLE_NV: 57 return BRW_SURFACE_2D; 58 59 case GL_TEXTURE_2D: 60 case GL_TEXTURE_2D_ARRAY_EXT: 61 case GL_TEXTURE_EXTERNAL_OES: 62 return BRW_SURFACE_2D; 63 64 case GL_TEXTURE_3D: 65 return BRW_SURFACE_3D; 66 67 case GL_TEXTURE_CUBE_MAP: 68 return BRW_SURFACE_CUBE; 69 70 default: 71 assert(0); 72 return 0; 73 } 74} 75 76struct surface_format_info { 77 bool exists; 78 int sampling; 79 int filtering; 80 int shadow_compare; 81 int chroma_key; 82 int render_target; 83 int alpha_blend; 84 int input_vb; 85 int streamed_output_vb; 86 int color_processing; 87}; 88 89/* This macro allows us to write the table almost as it appears in the PRM, 90 * while restructuring it to turn it into the C code we want. 91 */ 92#define SF(sampl, filt, shad, ck, rt, ab, vb, so, color, sf) \ 93 [sf] = { true, sampl, filt, shad, ck, rt, ab, vb, so, color }, 94 95#define Y 0 96#define x 999 97/** 98 * This is the table of support for surface (texture, renderbuffer, and vertex 99 * buffer, but not depthbuffer) formats across the various hardware generations. 100 * 101 * The table is formatted to match the documentation, except that the docs have 102 * this ridiculous mapping of Y[*+~^#&] for "supported on DevWhatever". To put 103 * it in our table, here's the mapping: 104 * 105 * Y*: 45 106 * Y+: 45 (g45/gm45) 107 * Y~: 50 (gen5) 108 * Y^: 60 (gen6) 109 * Y#: 70 (gen7) 110 * 111 * See page 88 of the Sandybridge PRM VOL4_Part1 PDF. 112 */ 113const struct surface_format_info surface_formats[] = { 114/* smpl filt shad CK RT AB VB SO color */ 115 SF( Y, 50, x, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_FLOAT) 116 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_SINT) 117 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_UINT) 118 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_UNORM) 119 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_SNORM) 120 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64_FLOAT) 121 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32G32B32X32_FLOAT) 122 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_SSCALED) 123 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_USCALED) 124 SF( Y, 50, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_FLOAT) 125 SF( Y, x, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_SINT) 126 SF( Y, x, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_UINT) 127 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_UNORM) 128 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_SNORM) 129 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_SSCALED) 130 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_USCALED) 131 SF( Y, Y, x, x, Y, 45, Y, x, 60, BRW_SURFACEFORMAT_R16G16B16A16_UNORM) 132 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SNORM) 133 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SINT) 134 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_UINT) 135 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_FLOAT) 136 SF( Y, 50, x, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32G32_FLOAT) 137 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32_SINT) 138 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32_UINT) 139 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS) 140 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT) 141 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32A32_FLOAT) 142 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_UNORM) 143 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_SNORM) 144 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64_FLOAT) 145 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16X16_UNORM) 146 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16X16_FLOAT) 147 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A32X32_FLOAT) 148 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32X32_FLOAT) 149 SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I32X32_FLOAT) 150 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SSCALED) 151 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_USCALED) 152 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_SSCALED) 153 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_USCALED) 154 SF( Y, Y, x, Y, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_B8G8R8A8_UNORM) 155 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB) 156/* smpl filt shad CK RT AB VB SO color */ 157 SF( Y, Y, x, x, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM) 158 SF( Y, Y, x, x, x, x, x, x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB) 159 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R10G10B10A2_UINT) 160 SF( Y, Y, x, x, x, Y, Y, x, x, BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM) 161 SF( Y, Y, x, x, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM) 162 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB) 163 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SNORM) 164 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SINT) 165 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_UINT) 166 SF( Y, Y, x, x, Y, 45, Y, x, x, BRW_SURFACEFORMAT_R16G16_UNORM) 167 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16G16_SNORM) 168 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_SINT) 169 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_UINT) 170 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16G16_FLOAT) 171 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM) 172 SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB) 173 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R11G11B10_FLOAT) 174 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32_SINT) 175 SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32_UINT) 176 SF( Y, 50, Y, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32_FLOAT) 177 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS) 178 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT) 179 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16A16_UNORM) 180 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I24X8_UNORM) 181 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L24X8_UNORM) 182 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A24X8_UNORM) 183 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I32_FLOAT) 184 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32_FLOAT) 185 SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A32_FLOAT) 186 SF( Y, Y, x, Y, x, x, x, x, 60, BRW_SURFACEFORMAT_B8G8R8X8_UNORM) 187 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB) 188 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM) 189 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB) 190 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP) 191 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B10G10R10X2_UNORM) 192 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16A16_FLOAT) 193 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_UNORM) 194 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_SNORM) 195/* smpl filt shad CK RT AB VB SO color */ 196 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R10G10B10X2_USCALED) 197 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SSCALED) 198 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_USCALED) 199 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_SSCALED) 200 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_USCALED) 201 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_SSCALED) 202 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_USCALED) 203 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G6R5_UNORM) 204 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB) 205 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM) 206 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB) 207 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM) 208 SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB) 209 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R8G8_UNORM) 210 SF( Y, Y, x, Y, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8G8_SNORM) 211 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_SINT) 212 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_UINT) 213 SF( Y, Y, Y, x, Y, 45, Y, x, 70, BRW_SURFACEFORMAT_R16_UNORM) 214 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16_SNORM) 215 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16_SINT) 216 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16_UINT) 217 SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16_FLOAT) 218 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I16_UNORM) 219 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16_UNORM) 220 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A16_UNORM) 221 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_UNORM) 222 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I16_FLOAT) 223 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16_FLOAT) 224 SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A16_FLOAT) 225 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_UNORM_SRGB) 226 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM) 227 SF( x, x, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM) 228 SF( x, x, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB) 229 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_SSCALED) 230 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_USCALED) 231/* smpl filt shad CK RT AB VB SO color */ 232 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16_SSCALED) 233 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16_USCALED) 234 SF( Y, Y, x, 45, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R8_UNORM) 235 SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8_SNORM) 236 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8_SINT) 237 SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8_UINT) 238 SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_A8_UNORM) 239 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I8_UNORM) 240 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_L8_UNORM) 241 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P4A4_UNORM) 242 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A4P4_UNORM) 243 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8_SSCALED) 244 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8_USCALED) 245 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8_UNORM_SRGB) 246 SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_DXT1_RGB_SRGB) 247 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R1_UINT) 248 SF( Y, Y, x, Y, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_NORMAL) 249 SF( Y, Y, x, Y, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUVY) 250 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC1_UNORM) 251 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC2_UNORM) 252 SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC3_UNORM) 253 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC4_UNORM) 254 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC5_UNORM) 255 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC1_UNORM_SRGB) 256 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC2_UNORM_SRGB) 257 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC3_UNORM_SRGB) 258 SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_MONO8) 259 SF( Y, Y, x, x, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUV) 260 SF( Y, Y, x, x, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPY) 261 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_DXT1_RGB) 262/* smpl filt shad CK RT AB VB SO color */ 263 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_FXT1) 264 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_UNORM) 265 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_SNORM) 266 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_SSCALED) 267 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_USCALED) 268 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64B64A64_FLOAT) 269 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64B64_FLOAT) 270 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC4_SNORM) 271 SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC5_SNORM) 272 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_UNORM) 273 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_SNORM) 274 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_SSCALED) 275 SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_USCALED) 276}; 277#undef x 278#undef Y 279 280uint32_t 281brw_format_for_mesa_format(gl_format mesa_format) 282{ 283 /* This table is ordered according to the enum ordering in formats.h. We do 284 * expect that enum to be extended without our explicit initialization 285 * staying in sync, so we initialize to 0 even though 286 * BRW_SURFACEFORMAT_R32G32B32A32_FLOAT happens to also be 0. 287 */ 288 static const uint32_t table[MESA_FORMAT_COUNT] = 289 { 290 [MESA_FORMAT_RGBA8888] = 0, 291 [MESA_FORMAT_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_UNORM, 292 [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM, 293 [MESA_FORMAT_ARGB8888_REV] = 0, 294 [MESA_FORMAT_RGBX8888] = 0, 295 [MESA_FORMAT_RGBX8888_REV] = BRW_SURFACEFORMAT_R8G8B8X8_UNORM, 296 [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM, 297 [MESA_FORMAT_XRGB8888_REV] = 0, 298 [MESA_FORMAT_RGB888] = 0, 299 [MESA_FORMAT_BGR888] = 0, 300 [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM, 301 [MESA_FORMAT_RGB565_REV] = 0, 302 [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM, 303 [MESA_FORMAT_ARGB4444_REV] = 0, 304 [MESA_FORMAT_RGBA5551] = 0, 305 [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM, 306 [MESA_FORMAT_ARGB1555_REV] = 0, 307 [MESA_FORMAT_AL44] = 0, 308 [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM, 309 [MESA_FORMAT_AL88_REV] = 0, 310 [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM, 311 [MESA_FORMAT_AL1616_REV] = 0, 312 [MESA_FORMAT_RGB332] = 0, 313 [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM, 314 [MESA_FORMAT_A16] = BRW_SURFACEFORMAT_A16_UNORM, 315 [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM, 316 [MESA_FORMAT_L16] = BRW_SURFACEFORMAT_L16_UNORM, 317 [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM, 318 [MESA_FORMAT_I16] = BRW_SURFACEFORMAT_I16_UNORM, 319 [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL, 320 [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY, 321 [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM, 322 [MESA_FORMAT_GR88] = BRW_SURFACEFORMAT_R8G8_UNORM, 323 [MESA_FORMAT_RG88] = 0, 324 [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM, 325 [MESA_FORMAT_RG1616] = BRW_SURFACEFORMAT_R16G16_UNORM, 326 [MESA_FORMAT_RG1616_REV] = 0, 327 [MESA_FORMAT_ARGB2101010] = BRW_SURFACEFORMAT_B10G10R10A2_UNORM, 328 [MESA_FORMAT_ABGR2101010_UINT] = BRW_SURFACEFORMAT_R10G10B10A2_UINT, 329 [MESA_FORMAT_Z24_S8] = 0, 330 [MESA_FORMAT_S8_Z24] = 0, 331 [MESA_FORMAT_Z16] = 0, 332 [MESA_FORMAT_X8_Z24] = 0, 333 [MESA_FORMAT_Z24_X8] = 0, 334 [MESA_FORMAT_Z32] = 0, 335 [MESA_FORMAT_S8] = 0, 336 337 [MESA_FORMAT_SRGB8] = 0, 338 [MESA_FORMAT_SRGBA8] = 0, 339 [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB, 340 [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB, 341 [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB, 342 [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB, 343 [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB, 344 [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB, 345 [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB, 346 347 [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1, 348 [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1, 349 [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB, 350 [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM, 351 [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM, 352 [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM, 353 354 [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT, 355 [MESA_FORMAT_RGBA_FLOAT16] = BRW_SURFACEFORMAT_R16G16B16A16_FLOAT, 356 [MESA_FORMAT_RGB_FLOAT32] = 0, 357 [MESA_FORMAT_RGB_FLOAT16] = 0, 358 [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT, 359 [MESA_FORMAT_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_A16_FLOAT, 360 [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT, 361 [MESA_FORMAT_LUMINANCE_FLOAT16] = BRW_SURFACEFORMAT_L16_FLOAT, 362 [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT, 363 [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_L16A16_FLOAT, 364 [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT, 365 [MESA_FORMAT_INTENSITY_FLOAT16] = BRW_SURFACEFORMAT_I16_FLOAT, 366 [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT, 367 [MESA_FORMAT_R_FLOAT16] = BRW_SURFACEFORMAT_R16_FLOAT, 368 [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT, 369 [MESA_FORMAT_RG_FLOAT16] = BRW_SURFACEFORMAT_R16G16_FLOAT, 370 371 [MESA_FORMAT_ALPHA_UINT8] = 0, 372 [MESA_FORMAT_ALPHA_UINT16] = 0, 373 [MESA_FORMAT_ALPHA_UINT32] = 0, 374 [MESA_FORMAT_ALPHA_INT8] = 0, 375 [MESA_FORMAT_ALPHA_INT16] = 0, 376 [MESA_FORMAT_ALPHA_INT32] = 0, 377 378 [MESA_FORMAT_INTENSITY_UINT8] = 0, 379 [MESA_FORMAT_INTENSITY_UINT16] = 0, 380 [MESA_FORMAT_INTENSITY_UINT32] = 0, 381 [MESA_FORMAT_INTENSITY_INT8] = 0, 382 [MESA_FORMAT_INTENSITY_INT16] = 0, 383 [MESA_FORMAT_INTENSITY_INT32] = 0, 384 385 [MESA_FORMAT_LUMINANCE_UINT8] = 0, 386 [MESA_FORMAT_LUMINANCE_UINT16] = 0, 387 [MESA_FORMAT_LUMINANCE_UINT32] = 0, 388 [MESA_FORMAT_LUMINANCE_INT8] = 0, 389 [MESA_FORMAT_LUMINANCE_INT16] = 0, 390 [MESA_FORMAT_LUMINANCE_INT32] = 0, 391 392 [MESA_FORMAT_LUMINANCE_ALPHA_UINT8] = 0, 393 [MESA_FORMAT_LUMINANCE_ALPHA_UINT16] = 0, 394 [MESA_FORMAT_LUMINANCE_ALPHA_UINT32] = 0, 395 [MESA_FORMAT_LUMINANCE_ALPHA_INT8] = 0, 396 [MESA_FORMAT_LUMINANCE_ALPHA_INT16] = 0, 397 [MESA_FORMAT_LUMINANCE_ALPHA_INT32] = 0, 398 399 [MESA_FORMAT_R_INT8] = BRW_SURFACEFORMAT_R8_SINT, 400 [MESA_FORMAT_RG_INT8] = BRW_SURFACEFORMAT_R8G8_SINT, 401 [MESA_FORMAT_RGB_INT8] = 0, 402 [MESA_FORMAT_RGBA_INT8] = BRW_SURFACEFORMAT_R8G8B8A8_SINT, 403 [MESA_FORMAT_R_INT16] = BRW_SURFACEFORMAT_R16_SINT, 404 [MESA_FORMAT_RG_INT16] = BRW_SURFACEFORMAT_R16G16_SINT, 405 [MESA_FORMAT_RGB_INT16] = 0, 406 [MESA_FORMAT_RGBA_INT16] = BRW_SURFACEFORMAT_R16G16B16A16_SINT, 407 [MESA_FORMAT_R_INT32] = BRW_SURFACEFORMAT_R32_SINT, 408 [MESA_FORMAT_RG_INT32] = BRW_SURFACEFORMAT_R32G32_SINT, 409 [MESA_FORMAT_RGB_INT32] = BRW_SURFACEFORMAT_R32G32B32_SINT, 410 [MESA_FORMAT_RGBA_INT32] = BRW_SURFACEFORMAT_R32G32B32A32_SINT, 411 412 [MESA_FORMAT_R_UINT8] = BRW_SURFACEFORMAT_R8_UINT, 413 [MESA_FORMAT_RG_UINT8] = BRW_SURFACEFORMAT_R8G8_UINT, 414 [MESA_FORMAT_RGB_UINT8] = 0, 415 [MESA_FORMAT_RGBA_UINT8] = BRW_SURFACEFORMAT_R8G8B8A8_UINT, 416 [MESA_FORMAT_R_UINT16] = BRW_SURFACEFORMAT_R16_UINT, 417 [MESA_FORMAT_RG_UINT16] = BRW_SURFACEFORMAT_R16G16_UINT, 418 [MESA_FORMAT_RGB_UINT16] = 0, 419 [MESA_FORMAT_RGBA_UINT16] = BRW_SURFACEFORMAT_R16G16B16A16_UINT, 420 [MESA_FORMAT_R_UINT32] = BRW_SURFACEFORMAT_R32_UINT, 421 [MESA_FORMAT_RG_UINT32] = BRW_SURFACEFORMAT_R32G32_UINT, 422 [MESA_FORMAT_RGB_UINT32] = BRW_SURFACEFORMAT_R32G32B32_UINT, 423 [MESA_FORMAT_RGBA_UINT32] = BRW_SURFACEFORMAT_R32G32B32A32_UINT, 424 425 [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM, 426 [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM, 427 [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM, 428 [MESA_FORMAT_SIGNED_RGBX8888] = 0, 429 [MESA_FORMAT_SIGNED_RGBA8888] = 0, 430 [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM, 431 [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM, 432 [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM, 433 [MESA_FORMAT_SIGNED_RGB_16] = 0, 434 [MESA_FORMAT_SIGNED_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_SNORM, 435 [MESA_FORMAT_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_UNORM, 436 437 [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM, 438 [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM, 439 [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM, 440 [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM, 441 442 [MESA_FORMAT_L_LATC1] = 0, 443 [MESA_FORMAT_SIGNED_L_LATC1] = 0, 444 [MESA_FORMAT_LA_LATC2] = 0, 445 [MESA_FORMAT_SIGNED_LA_LATC2] = 0, 446 447 [MESA_FORMAT_SIGNED_A8] = 0, 448 [MESA_FORMAT_SIGNED_L8] = 0, 449 [MESA_FORMAT_SIGNED_AL88] = 0, 450 [MESA_FORMAT_SIGNED_I8] = 0, 451 [MESA_FORMAT_SIGNED_A16] = 0, 452 [MESA_FORMAT_SIGNED_L16] = 0, 453 [MESA_FORMAT_SIGNED_AL1616] = 0, 454 [MESA_FORMAT_SIGNED_I16] = 0, 455 456 [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP, 457 [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT, 458 459 [MESA_FORMAT_Z32_FLOAT] = 0, 460 [MESA_FORMAT_Z32_FLOAT_X24S8] = 0, 461 }; 462 assert(mesa_format < MESA_FORMAT_COUNT); 463 return table[mesa_format]; 464} 465 466void 467brw_init_surface_formats(struct brw_context *brw) 468{ 469 struct intel_context *intel = &brw->intel; 470 struct gl_context *ctx = &intel->ctx; 471 int gen; 472 gl_format format; 473 474 gen = intel->gen * 10; 475 if (intel->is_g4x) 476 gen += 5; 477 478 for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) { 479 uint32_t texture, render; 480 const struct surface_format_info *rinfo, *tinfo; 481 bool is_integer = _mesa_is_format_integer_color(format); 482 483 render = texture = brw_format_for_mesa_format(format); 484 tinfo = &surface_formats[texture]; 485 486 /* The value of BRW_SURFACEFORMAT_R32G32B32A32_FLOAT is 0, so don't skip 487 * it. 488 */ 489 if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32) 490 continue; 491 492 if (gen >= tinfo->sampling && (gen >= tinfo->filtering || is_integer)) 493 ctx->TextureFormatSupported[format] = true; 494 495 /* Re-map some render target formats to make them supported when they 496 * wouldn't be using their format for texturing. 497 */ 498 switch (render) { 499 /* For these formats, we just need to read/write the first 500 * channel into R, which is to say that we just treat them as 501 * GL_RED. 502 */ 503 case BRW_SURFACEFORMAT_I32_FLOAT: 504 case BRW_SURFACEFORMAT_L32_FLOAT: 505 render = BRW_SURFACEFORMAT_R32_FLOAT; 506 break; 507 case BRW_SURFACEFORMAT_I16_FLOAT: 508 case BRW_SURFACEFORMAT_L16_FLOAT: 509 render = BRW_SURFACEFORMAT_R16_FLOAT; 510 break; 511 case BRW_SURFACEFORMAT_B8G8R8X8_UNORM: 512 /* XRGB is handled as ARGB because the chips in this family 513 * cannot render to XRGB targets. This means that we have to 514 * mask writes to alpha (ala glColorMask) and reconfigure the 515 * alpha blending hardware to use GL_ONE (or GL_ZERO) for 516 * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is 517 * used. 518 */ 519 render = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; 520 break; 521 } 522 523 rinfo = &surface_formats[render]; 524 525 /* Note that GL_EXT_texture_integer says that blending doesn't occur for 526 * integer, so we don't need hardware support for blending on it. Other 527 * than that, GL in general requires alpha blending for render targets, 528 * even though we don't support it for some formats. 529 */ 530 if (gen >= rinfo->render_target && 531 (gen >= rinfo->alpha_blend || is_integer)) { 532 brw->render_target_format[format] = render; 533 brw->format_supported_as_render_target[format] = true; 534 } 535 } 536 537 /* We will check this table for FBO completeness, but the surface format 538 * table above only covered color rendering. 539 */ 540 brw->format_supported_as_render_target[MESA_FORMAT_S8_Z24] = true; 541 brw->format_supported_as_render_target[MESA_FORMAT_X8_Z24] = true; 542 brw->format_supported_as_render_target[MESA_FORMAT_S8] = true; 543 brw->format_supported_as_render_target[MESA_FORMAT_Z16] = true; 544 brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT] = true; 545 brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT_X24S8] = true; 546 547 /* We remap depth formats to a supported texturing format in 548 * translate_tex_format(). 549 */ 550 ctx->TextureFormatSupported[MESA_FORMAT_S8_Z24] = true; 551 ctx->TextureFormatSupported[MESA_FORMAT_X8_Z24] = true; 552 ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT] = true; 553 ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT_X24S8] = true; 554 ctx->TextureFormatSupported[MESA_FORMAT_Z16] = true; 555 556 /* On hardware that lacks support for ETC1, we map ETC1 to RGBX 557 * during glCompressedTexImage2D(). See intel_mipmap_tree::wraps_etc1. 558 */ 559 ctx->TextureFormatSupported[MESA_FORMAT_ETC1_RGB8] = true; 560} 561 562bool 563brw_render_target_supported(struct intel_context *intel, 564 struct gl_renderbuffer *rb) 565{ 566 struct brw_context *brw = brw_context(&intel->ctx); 567 gl_format format = rb->Format; 568 569 /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means 570 * we would consider them renderable even though we don't have surface 571 * support for their alpha behavior and don't have the blending unit 572 * available to fake it like we do for XRGB8888. Force them to being 573 * unsupported. 574 */ 575 if ((rb->_BaseFormat != GL_RGBA && 576 rb->_BaseFormat != GL_RG && 577 rb->_BaseFormat != GL_RED) && _mesa_is_format_integer_color(format)) 578 return false; 579 580 /* Under some conditions, MSAA is not supported for formats whose width is 581 * more than 64 bits. 582 */ 583 if (rb->NumSamples > 0 && _mesa_get_format_bytes(format) > 8) { 584 /* Gen6: MSAA on >64 bit formats is unsupported. */ 585 if (intel->gen <= 6) 586 return false; 587 588 /* Gen7: 8x MSAA on >64 bit formats is unsupported. */ 589 if (rb->NumSamples >= 8) 590 return false; 591 } 592 593 return brw->format_supported_as_render_target[format]; 594} 595 596GLuint 597translate_tex_format(gl_format mesa_format, 598 GLenum internal_format, 599 GLenum depth_mode, 600 GLenum srgb_decode) 601{ 602 if (srgb_decode == GL_SKIP_DECODE_EXT) 603 mesa_format = _mesa_get_srgb_format_linear(mesa_format); 604 605 switch( mesa_format ) { 606 607 case MESA_FORMAT_Z16: 608 return BRW_SURFACEFORMAT_I16_UNORM; 609 610 case MESA_FORMAT_S8_Z24: 611 case MESA_FORMAT_X8_Z24: 612 return BRW_SURFACEFORMAT_I24X8_UNORM; 613 614 case MESA_FORMAT_Z32_FLOAT: 615 return BRW_SURFACEFORMAT_I32_FLOAT; 616 617 case MESA_FORMAT_Z32_FLOAT_X24S8: 618 return BRW_SURFACEFORMAT_R32G32_FLOAT; 619 620 case MESA_FORMAT_RGBA_FLOAT32: 621 /* The value of this BRW_SURFACEFORMAT is 0, which tricks the 622 * assertion below. 623 */ 624 return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT; 625 626 default: 627 assert(brw_format_for_mesa_format(mesa_format) != 0); 628 return brw_format_for_mesa_format(mesa_format); 629 } 630} 631 632uint32_t 633brw_get_surface_tiling_bits(uint32_t tiling) 634{ 635 switch (tiling) { 636 case I915_TILING_X: 637 return BRW_SURFACE_TILED; 638 case I915_TILING_Y: 639 return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y; 640 default: 641 return 0; 642 } 643} 644 645 646uint32_t 647brw_get_surface_num_multisamples(unsigned num_samples) 648{ 649 if (num_samples > 1) 650 return BRW_SURFACE_MULTISAMPLECOUNT_4; 651 else 652 return BRW_SURFACE_MULTISAMPLECOUNT_1; 653} 654 655 656static void 657brw_update_buffer_texture_surface(struct gl_context *ctx, GLuint unit) 658{ 659 struct brw_context *brw = brw_context(ctx); 660 struct intel_context *intel = &brw->intel; 661 struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current; 662 const GLuint surf_index = SURF_INDEX_TEXTURE(unit); 663 uint32_t *surf; 664 struct intel_buffer_object *intel_obj = 665 intel_buffer_object(tObj->BufferObject); 666 drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL; 667 gl_format format = tObj->_BufferObjectFormat; 668 uint32_t brw_format = brw_format_for_mesa_format(format); 669 int texel_size = _mesa_get_format_bytes(format); 670 671 if (brw_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) { 672 _mesa_problem(NULL, "bad format %s for texture buffer\n", 673 _mesa_get_format_name(format)); 674 } 675 676 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 677 6 * 4, 32, &brw->wm.surf_offset[surf_index]); 678 679 surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT | 680 (brw_format_for_mesa_format(format) << BRW_SURFACE_FORMAT_SHIFT)); 681 682 if (intel->gen >= 6) 683 surf[0] |= BRW_SURFACE_RC_READ_WRITE; 684 685 if (bo) { 686 surf[1] = bo->offset; /* reloc */ 687 688 /* Emit relocation to surface contents. */ 689 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 690 brw->wm.surf_offset[surf_index] + 4, 691 bo, 0, I915_GEM_DOMAIN_SAMPLER, 0); 692 693 int w = intel_obj->Base.Size / texel_size; 694 surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT | 695 ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT); 696 surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT | 697 (texel_size - 1) << BRW_SURFACE_PITCH_SHIFT); 698 } else { 699 surf[1] = 0; 700 surf[2] = 0; 701 surf[3] = 0; 702 } 703 704 surf[4] = 0; 705 surf[5] = 0; 706} 707 708static void 709brw_update_texture_surface( struct gl_context *ctx, GLuint unit ) 710{ 711 struct brw_context *brw = brw_context(ctx); 712 struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current; 713 struct intel_texture_object *intelObj = intel_texture_object(tObj); 714 struct intel_mipmap_tree *mt = intelObj->mt; 715 struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel]; 716 struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit); 717 const GLuint surf_index = SURF_INDEX_TEXTURE(unit); 718 uint32_t *surf; 719 int width, height, depth; 720 721 if (tObj->Target == GL_TEXTURE_BUFFER) { 722 brw_update_buffer_texture_surface(ctx, unit); 723 return; 724 } 725 726 intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth); 727 728 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 729 6 * 4, 32, &brw->wm.surf_offset[surf_index]); 730 731 surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT | 732 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT | 733 BRW_SURFACE_CUBEFACE_ENABLES | 734 (translate_tex_format(mt->format, 735 firstImage->InternalFormat, 736 tObj->DepthMode, 737 sampler->sRGBDecode) << 738 BRW_SURFACE_FORMAT_SHIFT)); 739 740 surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */ 741 742 surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT | 743 (width - 1) << BRW_SURFACE_WIDTH_SHIFT | 744 (height - 1) << BRW_SURFACE_HEIGHT_SHIFT); 745 746 surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) | 747 (depth - 1) << BRW_SURFACE_DEPTH_SHIFT | 748 ((intelObj->mt->region->pitch * intelObj->mt->cpp) - 1) << 749 BRW_SURFACE_PITCH_SHIFT); 750 751 surf[4] = 0; 752 753 surf[5] = (mt->align_h == 4) ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0; 754 755 /* Emit relocation to surface contents */ 756 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 757 brw->wm.surf_offset[surf_index] + 4, 758 intelObj->mt->region->bo, 759 intelObj->mt->offset, 760 I915_GEM_DOMAIN_SAMPLER, 0); 761} 762 763/** 764 * Create the constant buffer surface. Vertex/fragment shader constants will be 765 * read from this buffer with Data Port Read instructions/messages. 766 */ 767void 768brw_create_constant_surface(struct brw_context *brw, 769 drm_intel_bo *bo, 770 uint32_t offset, 771 int width, 772 uint32_t *out_offset) 773{ 774 struct intel_context *intel = &brw->intel; 775 const GLint w = width - 1; 776 uint32_t *surf; 777 778 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 779 6 * 4, 32, out_offset); 780 781 surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT | 782 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT | 783 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT); 784 785 if (intel->gen >= 6) 786 surf[0] |= BRW_SURFACE_RC_READ_WRITE; 787 788 surf[1] = bo->offset + offset; /* reloc */ 789 790 surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT | 791 ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT); 792 793 surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT | 794 (16 - 1) << BRW_SURFACE_PITCH_SHIFT); /* ignored */ 795 796 surf[4] = 0; 797 surf[5] = 0; 798 799 /* Emit relocation to surface contents. Section 5.1.1 of the gen4 800 * bspec ("Data Cache") says that the data cache does not exist as 801 * a separate cache and is just the sampler cache. 802 */ 803 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 804 *out_offset + 4, 805 bo, offset, 806 I915_GEM_DOMAIN_SAMPLER, 0); 807} 808 809/** 810 * Set up a binding table entry for use by stream output logic (transform 811 * feedback). 812 * 813 * buffer_size_minus_1 must me less than BRW_MAX_NUM_BUFFER_ENTRIES. 814 */ 815void 816brw_update_sol_surface(struct brw_context *brw, 817 struct gl_buffer_object *buffer_obj, 818 uint32_t *out_offset, unsigned num_vector_components, 819 unsigned stride_dwords, unsigned offset_dwords) 820{ 821 struct intel_context *intel = &brw->intel; 822 struct intel_buffer_object *intel_bo = intel_buffer_object(buffer_obj); 823 drm_intel_bo *bo = 824 intel_bufferobj_buffer(intel, intel_bo, INTEL_WRITE_PART); 825 uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, 826 out_offset); 827 uint32_t pitch_minus_1 = 4*stride_dwords - 1; 828 uint32_t offset_bytes = 4 * offset_dwords; 829 size_t size_dwords = buffer_obj->Size / 4; 830 uint32_t buffer_size_minus_1, width, height, depth, surface_format; 831 832 /* FIXME: can we rely on core Mesa to ensure that the buffer isn't 833 * too big to map using a single binding table entry? 834 */ 835 assert((size_dwords - offset_dwords) / stride_dwords 836 <= BRW_MAX_NUM_BUFFER_ENTRIES); 837 838 if (size_dwords > offset_dwords + num_vector_components) { 839 /* There is room for at least 1 transform feedback output in the buffer. 840 * Compute the number of additional transform feedback outputs the 841 * buffer has room for. 842 */ 843 buffer_size_minus_1 = 844 (size_dwords - offset_dwords - num_vector_components) / stride_dwords; 845 } else { 846 /* There isn't even room for a single transform feedback output in the 847 * buffer. We can't configure the binding table entry to prevent output 848 * entirely; we'll have to rely on the geometry shader to detect 849 * overflow. But to minimize the damage in case of a bug, set up the 850 * binding table entry to just allow a single output. 851 */ 852 buffer_size_minus_1 = 0; 853 } 854 width = buffer_size_minus_1 & 0x7f; 855 height = (buffer_size_minus_1 & 0xfff80) >> 7; 856 depth = (buffer_size_minus_1 & 0x7f00000) >> 20; 857 858 switch (num_vector_components) { 859 case 1: 860 surface_format = BRW_SURFACEFORMAT_R32_FLOAT; 861 break; 862 case 2: 863 surface_format = BRW_SURFACEFORMAT_R32G32_FLOAT; 864 break; 865 case 3: 866 surface_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT; 867 break; 868 case 4: 869 surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT; 870 break; 871 default: 872 assert(!"Invalid vector size for transform feedback output"); 873 surface_format = BRW_SURFACEFORMAT_R32_FLOAT; 874 break; 875 } 876 877 surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT | 878 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT | 879 surface_format << BRW_SURFACE_FORMAT_SHIFT | 880 BRW_SURFACE_RC_READ_WRITE; 881 surf[1] = bo->offset + offset_bytes; /* reloc */ 882 surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT | 883 height << BRW_SURFACE_HEIGHT_SHIFT); 884 surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT | 885 pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT); 886 surf[4] = 0; 887 surf[5] = 0; 888 889 /* Emit relocation to surface contents. */ 890 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 891 *out_offset + 4, 892 bo, offset_bytes, 893 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); 894} 895 896/* Creates a new WM constant buffer reflecting the current fragment program's 897 * constants, if needed by the fragment program. 898 * 899 * Otherwise, constants go through the CURBEs using the brw_constant_buffer 900 * state atom. 901 */ 902static void 903brw_upload_wm_pull_constants(struct brw_context *brw) 904{ 905 struct gl_context *ctx = &brw->intel.ctx; 906 struct intel_context *intel = &brw->intel; 907 /* BRW_NEW_FRAGMENT_PROGRAM */ 908 struct brw_fragment_program *fp = 909 (struct brw_fragment_program *) brw->fragment_program; 910 struct gl_program_parameter_list *params = fp->program.Base.Parameters; 911 const int size = brw->wm.prog_data->nr_pull_params * sizeof(float); 912 const int surf_index = SURF_INDEX_FRAG_CONST_BUFFER; 913 float *constants; 914 unsigned int i; 915 916 _mesa_load_state_parameters(ctx, params); 917 918 /* CACHE_NEW_WM_PROG */ 919 if (brw->wm.prog_data->nr_pull_params == 0) { 920 if (brw->wm.const_bo) { 921 drm_intel_bo_unreference(brw->wm.const_bo); 922 brw->wm.const_bo = NULL; 923 brw->wm.surf_offset[surf_index] = 0; 924 brw->state.dirty.brw |= BRW_NEW_SURFACES; 925 } 926 return; 927 } 928 929 drm_intel_bo_unreference(brw->wm.const_bo); 930 brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo", 931 size, 64); 932 933 /* _NEW_PROGRAM_CONSTANTS */ 934 drm_intel_gem_bo_map_gtt(brw->wm.const_bo); 935 constants = brw->wm.const_bo->virtual; 936 for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) { 937 constants[i] = *brw->wm.prog_data->pull_param[i]; 938 } 939 drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo); 940 941 intel->vtbl.create_constant_surface(brw, brw->wm.const_bo, 0, 942 params->NumParameters, 943 &brw->wm.surf_offset[surf_index]); 944 945 brw->state.dirty.brw |= BRW_NEW_SURFACES; 946} 947 948const struct brw_tracked_state brw_wm_pull_constants = { 949 .dirty = { 950 .mesa = (_NEW_PROGRAM_CONSTANTS), 951 .brw = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM), 952 .cache = CACHE_NEW_WM_PROG, 953 }, 954 .emit = brw_upload_wm_pull_constants, 955}; 956 957static void 958brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit) 959{ 960 /* From the Sandy bridge PRM, Vol4 Part1 p71 (Surface Type: Programming 961 * Notes): 962 * 963 * A null surface will be used in instances where an actual surface is 964 * not bound. When a write message is generated to a null surface, no 965 * actual surface is written to. When a read message (including any 966 * sampling engine message) is generated to a null surface, the result 967 * is all zeros. Note that a null surface type is allowed to be used 968 * with all messages, even if it is not specificially indicated as 969 * supported. All of the remaining fields in surface state are ignored 970 * for null surfaces, with the following exceptions: 971 * 972 * - [DevSNB+]: Width, Height, Depth, and LOD fields must match the 973 * depth buffer’s corresponding state for all render target surfaces, 974 * including null. 975 * 976 * - Surface Format must be R8G8B8A8_UNORM. 977 */ 978 struct intel_context *intel = &brw->intel; 979 struct gl_context *ctx = &intel->ctx; 980 uint32_t *surf; 981 unsigned surface_type = BRW_SURFACE_NULL; 982 drm_intel_bo *bo = NULL; 983 unsigned pitch_minus_1 = 0; 984 uint32_t multisampling_state = 0; 985 986 /* _NEW_BUFFERS */ 987 const struct gl_framebuffer *fb = ctx->DrawBuffer; 988 989 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 990 6 * 4, 32, &brw->wm.surf_offset[unit]); 991 992 if (fb->Visual.samples > 1) { 993 /* On Gen6, null render targets seem to cause GPU hangs when 994 * multisampling. So work around this problem by rendering into dummy 995 * color buffer. 996 * 997 * To decrease the amount of memory needed by the workaround buffer, we 998 * set its pitch to 128 bytes (the width of a Y tile). This means that 999 * the amount of memory needed for the workaround buffer is 1000 * (width_in_tiles + height_in_tiles - 1) tiles. 1001 * 1002 * Note that since the workaround buffer will be interpreted by the 1003 * hardware as an interleaved multisampled buffer, we need to compute 1004 * width_in_tiles and height_in_tiles by dividing the width and height 1005 * by 16 rather than the normal Y-tile size of 32. 1006 */ 1007 unsigned width_in_tiles = ALIGN(fb->Width, 16) / 16; 1008 unsigned height_in_tiles = ALIGN(fb->Height, 16) / 16; 1009 unsigned size_needed = (width_in_tiles + height_in_tiles - 1) * 4096; 1010 brw_get_scratch_bo(intel, &brw->wm.multisampled_null_render_target_bo, 1011 size_needed); 1012 bo = brw->wm.multisampled_null_render_target_bo; 1013 surface_type = BRW_SURFACE_2D; 1014 pitch_minus_1 = 127; 1015 multisampling_state = 1016 brw_get_surface_num_multisamples(fb->Visual.samples); 1017 } 1018 1019 surf[0] = (surface_type << BRW_SURFACE_TYPE_SHIFT | 1020 BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT); 1021 if (intel->gen < 6) { 1022 surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT | 1023 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT | 1024 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT | 1025 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT); 1026 } 1027 surf[1] = bo ? bo->offset : 0; 1028 surf[2] = ((fb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT | 1029 (fb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT); 1030 1031 /* From Sandy bridge PRM, Vol4 Part1 p82 (Tiled Surface: Programming 1032 * Notes): 1033 * 1034 * If Surface Type is SURFTYPE_NULL, this field must be TRUE 1035 */ 1036 surf[3] = (BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y | 1037 pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT); 1038 surf[4] = multisampling_state; 1039 surf[5] = 0; 1040 1041 if (bo) { 1042 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 1043 brw->wm.surf_offset[unit] + 4, 1044 bo, 0, 1045 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); 1046 } 1047} 1048 1049/** 1050 * Sets up a surface state structure to point at the given region. 1051 * While it is only used for the front/back buffer currently, it should be 1052 * usable for further buffers when doing ARB_draw_buffer support. 1053 */ 1054static void 1055brw_update_renderbuffer_surface(struct brw_context *brw, 1056 struct gl_renderbuffer *rb, 1057 unsigned int unit) 1058{ 1059 struct intel_context *intel = &brw->intel; 1060 struct gl_context *ctx = &intel->ctx; 1061 struct intel_renderbuffer *irb = intel_renderbuffer(rb); 1062 struct intel_mipmap_tree *mt = irb->mt; 1063 struct intel_region *region; 1064 uint32_t *surf; 1065 uint32_t tile_x, tile_y; 1066 uint32_t format = 0; 1067 gl_format rb_format = intel_rb_format(irb); 1068 1069 if (irb->tex_image && !brw->has_surface_tile_offset) { 1070 intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y); 1071 1072 if (tile_x != 0 || tile_y != 0) { 1073 /* Original gen4 hardware couldn't draw to a non-tile-aligned 1074 * destination in a miptree unless you actually setup your renderbuffer 1075 * as a miptree and used the fragile lod/array_index/etc. controls to 1076 * select the image. So, instead, we just make a new single-level 1077 * miptree and render into that. 1078 */ 1079 struct intel_context *intel = intel_context(ctx); 1080 struct intel_texture_image *intel_image = 1081 intel_texture_image(irb->tex_image); 1082 struct intel_mipmap_tree *new_mt; 1083 int width, height, depth; 1084 1085 intel_miptree_get_dimensions_for_image(irb->tex_image, &width, &height, &depth); 1086 1087 new_mt = intel_miptree_create(intel, irb->tex_image->TexObject->Target, 1088 intel_image->base.Base.TexFormat, 1089 intel_image->base.Base.Level, 1090 intel_image->base.Base.Level, 1091 width, height, depth, 1092 true, 1093 0 /* num_samples */, 1094 INTEL_MSAA_LAYOUT_NONE); 1095 1096 intel_miptree_copy_teximage(intel, intel_image, new_mt); 1097 intel_miptree_reference(&irb->mt, intel_image->mt); 1098 intel_renderbuffer_set_draw_offset(irb); 1099 intel_miptree_release(&new_mt); 1100 1101 mt = irb->mt; 1102 } 1103 } 1104 1105 region = irb->mt->region; 1106 1107 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 1108 6 * 4, 32, &brw->wm.surf_offset[unit]); 1109 1110 switch (rb_format) { 1111 case MESA_FORMAT_SARGB8: 1112 /* _NEW_BUFFERS 1113 * 1114 * Without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB surfaces to the 1115 * blend/update as sRGB. 1116 */ 1117 if (ctx->Color.sRGBEnabled) 1118 format = brw_format_for_mesa_format(rb_format); 1119 else 1120 format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; 1121 break; 1122 default: 1123 format = brw->render_target_format[rb_format]; 1124 if (unlikely(!brw->format_supported_as_render_target[rb_format])) { 1125 _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n", 1126 __FUNCTION__, _mesa_get_format_name(rb_format)); 1127 } 1128 break; 1129 } 1130 1131 surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT | 1132 format << BRW_SURFACE_FORMAT_SHIFT); 1133 1134 /* reloc */ 1135 surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) + 1136 region->bo->offset); 1137 1138 surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT | 1139 (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT); 1140 1141 surf[3] = (brw_get_surface_tiling_bits(region->tiling) | 1142 ((region->pitch * region->cpp) - 1) << BRW_SURFACE_PITCH_SHIFT); 1143 1144 surf[4] = brw_get_surface_num_multisamples(mt->num_samples); 1145 1146 assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0)); 1147 /* Note that the low bits of these fields are missing, so 1148 * there's the possibility of getting in trouble. 1149 */ 1150 assert(tile_x % 4 == 0); 1151 assert(tile_y % 2 == 0); 1152 surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT | 1153 (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT | 1154 (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0)); 1155 1156 if (intel->gen < 6) { 1157 /* _NEW_COLOR */ 1158 if (!ctx->Color.ColorLogicOpEnabled && 1159 (ctx->Color.BlendEnabled & (1 << unit))) 1160 surf[0] |= BRW_SURFACE_BLEND_ENABLED; 1161 1162 if (!ctx->Color.ColorMask[unit][0]) 1163 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT; 1164 if (!ctx->Color.ColorMask[unit][1]) 1165 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT; 1166 if (!ctx->Color.ColorMask[unit][2]) 1167 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT; 1168 1169 /* As mentioned above, disable writes to the alpha component when the 1170 * renderbuffer is XRGB. 1171 */ 1172 if (ctx->DrawBuffer->Visual.alphaBits == 0 || 1173 !ctx->Color.ColorMask[unit][3]) { 1174 surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT; 1175 } 1176 } 1177 1178 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 1179 brw->wm.surf_offset[unit] + 4, 1180 region->bo, 1181 surf[1] - region->bo->offset, 1182 I915_GEM_DOMAIN_RENDER, 1183 I915_GEM_DOMAIN_RENDER); 1184} 1185 1186/** 1187 * Construct SURFACE_STATE objects for renderbuffers/draw buffers. 1188 */ 1189static void 1190brw_update_renderbuffer_surfaces(struct brw_context *brw) 1191{ 1192 struct intel_context *intel = &brw->intel; 1193 struct gl_context *ctx = &brw->intel.ctx; 1194 GLuint i; 1195 1196 /* _NEW_BUFFERS | _NEW_COLOR */ 1197 /* Update surfaces for drawing buffers */ 1198 if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) { 1199 for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) { 1200 if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) { 1201 intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], i); 1202 } else { 1203 intel->vtbl.update_null_renderbuffer_surface(brw, i); 1204 } 1205 } 1206 } else { 1207 intel->vtbl.update_null_renderbuffer_surface(brw, 0); 1208 } 1209 brw->state.dirty.brw |= BRW_NEW_SURFACES; 1210} 1211 1212const struct brw_tracked_state brw_renderbuffer_surfaces = { 1213 .dirty = { 1214 .mesa = (_NEW_COLOR | 1215 _NEW_BUFFERS), 1216 .brw = BRW_NEW_BATCH, 1217 .cache = 0 1218 }, 1219 .emit = brw_update_renderbuffer_surfaces, 1220}; 1221 1222const struct brw_tracked_state gen6_renderbuffer_surfaces = { 1223 .dirty = { 1224 .mesa = _NEW_BUFFERS, 1225 .brw = BRW_NEW_BATCH, 1226 .cache = 0 1227 }, 1228 .emit = brw_update_renderbuffer_surfaces, 1229}; 1230 1231/** 1232 * Construct SURFACE_STATE objects for enabled textures. 1233 */ 1234static void 1235brw_update_texture_surfaces(struct brw_context *brw) 1236{ 1237 struct gl_context *ctx = &brw->intel.ctx; 1238 1239 for (unsigned i = 0; i < BRW_MAX_TEX_UNIT; i++) { 1240 const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i]; 1241 const GLuint surf = SURF_INDEX_TEXTURE(i); 1242 1243 /* _NEW_TEXTURE */ 1244 if (texUnit->_ReallyEnabled) { 1245 brw->intel.vtbl.update_texture_surface(ctx, i); 1246 } else { 1247 brw->wm.surf_offset[surf] = 0; 1248 } 1249 1250 /* For now, just mirror the texture setup to the VS slots. */ 1251 brw->vs.surf_offset[SURF_INDEX_VS_TEXTURE(i)] = 1252 brw->wm.surf_offset[surf]; 1253 } 1254 1255 brw->state.dirty.brw |= BRW_NEW_SURFACES; 1256} 1257 1258const struct brw_tracked_state brw_texture_surfaces = { 1259 .dirty = { 1260 .mesa = _NEW_TEXTURE, 1261 .brw = BRW_NEW_BATCH, 1262 .cache = 0 1263 }, 1264 .emit = brw_update_texture_surfaces, 1265}; 1266 1267void 1268brw_upload_ubo_surfaces(struct brw_context *brw, 1269 struct gl_shader *shader, 1270 uint32_t *surf_offsets) 1271{ 1272 struct gl_context *ctx = &brw->intel.ctx; 1273 struct intel_context *intel = &brw->intel; 1274 1275 if (!shader) 1276 return; 1277 1278 for (int i = 0; i < shader->NumUniformBlocks; i++) { 1279 struct gl_uniform_buffer_binding *binding; 1280 struct intel_buffer_object *intel_bo; 1281 1282 binding = &ctx->UniformBufferBindings[shader->UniformBlocks[i].Binding]; 1283 intel_bo = intel_buffer_object(binding->BufferObject); 1284 drm_intel_bo *bo = intel_bufferobj_buffer(intel, intel_bo, INTEL_READ); 1285 1286 /* Because behavior for referencing outside of the binding's size in the 1287 * glBindBufferRange case is undefined, we can just bind the whole buffer 1288 * glBindBufferBase wants and be a correct implementation. 1289 */ 1290 int size = bo->size - binding->Offset; 1291 size = ALIGN(size, 16) / 16; /* The interface takes a number of vec4s */ 1292 1293 intel->vtbl.create_constant_surface(brw, bo, binding->Offset, 1294 size, 1295 &surf_offsets[i]); 1296 } 1297 1298 if (shader->NumUniformBlocks) 1299 brw->state.dirty.brw |= BRW_NEW_SURFACES; 1300} 1301 1302static void 1303brw_upload_wm_ubo_surfaces(struct brw_context *brw) 1304{ 1305 struct gl_context *ctx = &brw->intel.ctx; 1306 /* _NEW_PROGRAM */ 1307 struct gl_shader_program *prog = ctx->Shader._CurrentFragmentProgram; 1308 1309 if (!prog) 1310 return; 1311 1312 brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT], 1313 &brw->wm.surf_offset[SURF_INDEX_WM_UBO(0)]); 1314} 1315 1316const struct brw_tracked_state brw_wm_ubo_surfaces = { 1317 .dirty = { 1318 .mesa = (_NEW_PROGRAM | 1319 _NEW_BUFFER_OBJECT), 1320 .brw = BRW_NEW_BATCH, 1321 .cache = 0, 1322 }, 1323 .emit = brw_upload_wm_ubo_surfaces, 1324}; 1325 1326/** 1327 * Constructs the binding table for the WM surface state, which maps unit 1328 * numbers to surface state objects. 1329 */ 1330static void 1331brw_upload_wm_binding_table(struct brw_context *brw) 1332{ 1333 uint32_t *bind; 1334 int i; 1335 1336 /* Might want to calculate nr_surfaces first, to avoid taking up so much 1337 * space for the binding table. 1338 */ 1339 bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE, 1340 sizeof(uint32_t) * BRW_MAX_WM_SURFACES, 1341 32, &brw->wm.bind_bo_offset); 1342 1343 /* BRW_NEW_SURFACES */ 1344 for (i = 0; i < BRW_MAX_WM_SURFACES; i++) { 1345 bind[i] = brw->wm.surf_offset[i]; 1346 } 1347 1348 brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE; 1349} 1350 1351const struct brw_tracked_state brw_wm_binding_table = { 1352 .dirty = { 1353 .mesa = 0, 1354 .brw = (BRW_NEW_BATCH | 1355 BRW_NEW_SURFACES), 1356 .cache = 0 1357 }, 1358 .emit = brw_upload_wm_binding_table, 1359}; 1360 1361void 1362gen4_init_vtable_surface_functions(struct brw_context *brw) 1363{ 1364 struct intel_context *intel = &brw->intel; 1365 1366 intel->vtbl.update_texture_surface = brw_update_texture_surface; 1367 intel->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface; 1368 intel->vtbl.update_null_renderbuffer_surface = 1369 brw_update_null_renderbuffer_surface; 1370 intel->vtbl.create_constant_surface = brw_create_constant_surface; 1371} 1372