gen7_blorp.cpp revision cb9765ca94b5a73eaafe0468ed40052dce55fdc8
1/* 2 * Copyright © 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#include <assert.h> 25 26#include "intel_batchbuffer.h" 27#include "intel_fbo.h" 28#include "intel_mipmap_tree.h" 29 30#include "brw_context.h" 31#include "brw_defines.h" 32#include "brw_state.h" 33 34#include "brw_blorp.h" 35#include "gen7_blorp.h" 36 37 38/* 3DSTATE_URB_VS 39 * 3DSTATE_URB_HS 40 * 3DSTATE_URB_DS 41 * 3DSTATE_URB_GS 42 * 43 * If the 3DSTATE_URB_VS is emitted, than the others must be also. From the 44 * BSpec, Volume 2a "3D Pipeline Overview", Section 1.7.1 3DSTATE_URB_VS: 45 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be 46 * programmed in order for the programming of this state to be 47 * valid. 48 */ 49static void 50gen7_blorp_emit_urb_config(struct brw_context *brw, 51 const brw_blorp_params *params) 52{ 53 /* The minimum valid value is 32. See 3DSTATE_URB_VS, 54 * Dword 1.15:0 "VS Number of URB Entries". 55 */ 56 int num_vs_entries = 32; 57 int vs_size = 2; 58 int vs_start = 2; /* skip over push constants */ 59 60 gen7_emit_urb_state(brw, num_vs_entries, vs_size, vs_start); 61} 62 63 64/* 3DSTATE_BLEND_STATE_POINTERS */ 65static void 66gen7_blorp_emit_blend_state_pointer(struct brw_context *brw, 67 const brw_blorp_params *params, 68 uint32_t cc_blend_state_offset) 69{ 70 struct intel_context *intel = &brw->intel; 71 72 BEGIN_BATCH(2); 73 OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2)); 74 OUT_BATCH(cc_blend_state_offset | 1); 75 ADVANCE_BATCH(); 76} 77 78 79/* 3DSTATE_CC_STATE_POINTERS */ 80static void 81gen7_blorp_emit_cc_state_pointer(struct brw_context *brw, 82 const brw_blorp_params *params, 83 uint32_t cc_state_offset) 84{ 85 struct intel_context *intel = &brw->intel; 86 87 BEGIN_BATCH(2); 88 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2)); 89 OUT_BATCH(cc_state_offset | 1); 90 ADVANCE_BATCH(); 91} 92 93static void 94gen7_blorp_emit_cc_viewport(struct brw_context *brw, 95 const brw_blorp_params *params) 96{ 97 struct intel_context *intel = &brw->intel; 98 struct brw_cc_viewport *ccv; 99 uint32_t cc_vp_offset; 100 101 ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE, 102 sizeof(*ccv), 32, 103 &cc_vp_offset); 104 ccv->min_depth = 0.0; 105 ccv->max_depth = 1.0; 106 107 BEGIN_BATCH(2); 108 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2)); 109 OUT_BATCH(cc_vp_offset); 110 ADVANCE_BATCH(); 111} 112 113 114/* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS 115 * 116 * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress. 117 */ 118static void 119gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw, 120 const brw_blorp_params *params, 121 uint32_t depthstencil_offset) 122{ 123 struct intel_context *intel = &brw->intel; 124 125 BEGIN_BATCH(2); 126 OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2)); 127 OUT_BATCH(depthstencil_offset | 1); 128 ADVANCE_BATCH(); 129} 130 131 132/* SURFACE_STATE for renderbuffer or texture surface (see 133 * brw_update_renderbuffer_surface and brw_update_texture_surface) 134 */ 135static uint32_t 136gen7_blorp_emit_surface_state(struct brw_context *brw, 137 const brw_blorp_params *params, 138 const brw_blorp_surface_info *surface, 139 uint32_t read_domains, uint32_t write_domain, 140 bool is_render_target) 141{ 142 struct intel_context *intel = &brw->intel; 143 144 uint32_t wm_surf_offset; 145 uint32_t width, height; 146 surface->get_miplevel_dims(&width, &height); 147 /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_UMS for 148 * color surfaces, width and height are measured in pixels; we don't need 149 * to divide them by 2 as we do for Gen6 (see 150 * gen6_blorp_emit_surface_state). 151 */ 152 if (surface->map_stencil_as_y_tiled) { 153 width *= 2; 154 height /= 2; 155 } 156 struct intel_region *region = surface->mt->region; 157 158 struct gen7_surface_state *surf = (struct gen7_surface_state *) 159 brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, sizeof(*surf), 32, 160 &wm_surf_offset); 161 memset(surf, 0, sizeof(*surf)); 162 163 if (surface->mt->align_h == 4) 164 surf->ss0.vertical_alignment = 1; 165 if (surface->mt->align_w == 8) 166 surf->ss0.horizontal_alignment = 1; 167 168 surf->ss0.surface_format = surface->brw_surfaceformat; 169 surf->ss0.surface_type = BRW_SURFACE_2D; 170 surf->ss0.surface_array_spacing = surface->array_spacing_lod0 ? 171 GEN7_SURFACE_ARYSPC_LOD0 : GEN7_SURFACE_ARYSPC_FULL; 172 173 /* reloc */ 174 surf->ss1.base_addr = region->bo->offset; /* No tile offsets needed */ 175 176 surf->ss2.width = width - 1; 177 surf->ss2.height = height - 1; 178 179 uint32_t tiling = surface->map_stencil_as_y_tiled 180 ? I915_TILING_Y : region->tiling; 181 gen7_set_surface_tiling(surf, tiling); 182 183 uint32_t pitch_bytes = region->pitch * region->cpp; 184 if (surface->map_stencil_as_y_tiled) 185 pitch_bytes *= 2; 186 surf->ss3.pitch = pitch_bytes - 1; 187 188 gen7_set_surface_msaa(surf, surface->num_samples, surface->msaa_layout); 189 if (surface->msaa_layout == INTEL_MSAA_LAYOUT_CMS) { 190 gen7_set_surface_mcs_info(brw, surf, wm_surf_offset, 191 surface->mt->mcs_mt, is_render_target); 192 } 193 194 if (intel->is_haswell) { 195 surf->ss7.shader_channel_select_r = HSW_SCS_RED; 196 surf->ss7.shader_channel_select_g = HSW_SCS_GREEN; 197 surf->ss7.shader_channel_select_b = HSW_SCS_BLUE; 198 surf->ss7.shader_channel_select_a = HSW_SCS_ALPHA; 199 } 200 201 /* Emit relocation to surface contents */ 202 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 203 wm_surf_offset + 204 offsetof(struct gen7_surface_state, ss1), 205 region->bo, 206 surf->ss1.base_addr - region->bo->offset, 207 read_domains, write_domain); 208 209 gen7_check_surface_setup(surf, is_render_target); 210 211 return wm_surf_offset; 212} 213 214 215/** 216 * SAMPLER_STATE. See gen7_update_sampler_state(). 217 */ 218static uint32_t 219gen7_blorp_emit_sampler_state(struct brw_context *brw, 220 const brw_blorp_params *params) 221{ 222 uint32_t sampler_offset; 223 224 struct gen7_sampler_state *sampler = (struct gen7_sampler_state *) 225 brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE, 226 sizeof(struct gen7_sampler_state), 227 32, &sampler_offset); 228 memset(sampler, 0, sizeof(*sampler)); 229 230 sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR; 231 sampler->ss0.mip_filter = BRW_MIPFILTER_NONE; 232 sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR; 233 234 sampler->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP; 235 sampler->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP; 236 sampler->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP; 237 238 // sampler->ss0.min_mag_neq = 1; 239 240 /* Set LOD bias: 241 */ 242 sampler->ss0.lod_bias = 0; 243 244 sampler->ss0.lod_preclamp = 1; /* OpenGL mode */ 245 sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */ 246 247 /* Set BaseMipLevel, MaxLOD, MinLOD: 248 * 249 * XXX: I don't think that using firstLevel, lastLevel works, 250 * because we always setup the surface state as if firstLevel == 251 * level zero. Probably have to subtract firstLevel from each of 252 * these: 253 */ 254 sampler->ss0.base_level = U_FIXED(0, 1); 255 256 sampler->ss1.max_lod = U_FIXED(0, 8); 257 sampler->ss1.min_lod = U_FIXED(0, 8); 258 259 sampler->ss3.non_normalized_coord = 1; 260 261 sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN | 262 BRW_ADDRESS_ROUNDING_ENABLE_V_MIN | 263 BRW_ADDRESS_ROUNDING_ENABLE_R_MIN; 264 sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG | 265 BRW_ADDRESS_ROUNDING_ENABLE_V_MAG | 266 BRW_ADDRESS_ROUNDING_ENABLE_R_MAG; 267 268 return sampler_offset; 269} 270 271 272/* 3DSTATE_HS 273 * 274 * Disable the hull shader. 275 */ 276static void 277gen7_blorp_emit_hs_disable(struct brw_context *brw, 278 const brw_blorp_params *params) 279{ 280 struct intel_context *intel = &brw->intel; 281 282 BEGIN_BATCH(7); 283 OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2)); 284 OUT_BATCH(0); 285 OUT_BATCH(0); 286 OUT_BATCH(0); 287 OUT_BATCH(0); 288 OUT_BATCH(0); 289 OUT_BATCH(0); 290 ADVANCE_BATCH(); 291} 292 293 294/* 3DSTATE_TE 295 * 296 * Disable the tesselation engine. 297 */ 298static void 299gen7_blorp_emit_te_disable(struct brw_context *brw, 300 const brw_blorp_params *params) 301{ 302 struct intel_context *intel = &brw->intel; 303 304 BEGIN_BATCH(4); 305 OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2)); 306 OUT_BATCH(0); 307 OUT_BATCH(0); 308 OUT_BATCH(0); 309 ADVANCE_BATCH(); 310} 311 312 313/* 3DSTATE_DS 314 * 315 * Disable the domain shader. 316 */ 317static void 318gen7_blorp_emit_ds_disable(struct brw_context *brw, 319 const brw_blorp_params *params) 320{ 321 struct intel_context *intel = &brw->intel; 322 323 BEGIN_BATCH(6); 324 OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2)); 325 OUT_BATCH(0); 326 OUT_BATCH(0); 327 OUT_BATCH(0); 328 OUT_BATCH(0); 329 OUT_BATCH(0); 330 ADVANCE_BATCH(); 331} 332 333 334/* 3DSTATE_STREAMOUT 335 * 336 * Disable streamout. 337 */ 338static void 339gen7_blorp_emit_streamout_disable(struct brw_context *brw, 340 const brw_blorp_params *params) 341{ 342 struct intel_context *intel = &brw->intel; 343 344 BEGIN_BATCH(3); 345 OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2)); 346 OUT_BATCH(0); 347 OUT_BATCH(0); 348 ADVANCE_BATCH(); 349} 350 351 352static void 353gen7_blorp_emit_sf_config(struct brw_context *brw, 354 const brw_blorp_params *params) 355{ 356 struct intel_context *intel = &brw->intel; 357 358 /* 3DSTATE_SF 359 * 360 * Disable ViewportTransformEnable (dw1.1) 361 * 362 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D 363 * Primitives Overview": 364 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the 365 * use of screen- space coordinates). 366 * 367 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5) 368 * and BackFaceFillMode (dw1.4:3) to SOLID(0). 369 * 370 * From the Sandy Bridge PRM, Volume 2, Part 1, Section 371 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode: 372 * SOLID: Any triangle or rectangle object found to be front-facing 373 * is rendered as a solid object. This setting is required when 374 * (rendering rectangle (RECTLIST) objects. 375 */ 376 { 377 BEGIN_BATCH(7); 378 OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2)); 379 OUT_BATCH(params->depth_format << 380 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT); 381 OUT_BATCH(params->num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0); 382 OUT_BATCH(0); 383 OUT_BATCH(0); 384 OUT_BATCH(0); 385 OUT_BATCH(0); 386 ADVANCE_BATCH(); 387 } 388 389 /* 3DSTATE_SBE */ 390 { 391 BEGIN_BATCH(14); 392 OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2)); 393 OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */ 394 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT | 395 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT); 396 for (int i = 0; i < 12; ++i) 397 OUT_BATCH(0); 398 ADVANCE_BATCH(); 399 } 400} 401 402 403/** 404 * Disable thread dispatch (dw5.19) and enable the HiZ op. 405 */ 406static void 407gen7_blorp_emit_wm_config(struct brw_context *brw, 408 const brw_blorp_params *params, 409 brw_blorp_prog_data *prog_data) 410{ 411 struct intel_context *intel = &brw->intel; 412 413 uint32_t dw1 = 0, dw2 = 0; 414 415 switch (params->hiz_op) { 416 case GEN6_HIZ_OP_DEPTH_CLEAR: 417 dw1 |= GEN7_WM_DEPTH_CLEAR; 418 break; 419 case GEN6_HIZ_OP_DEPTH_RESOLVE: 420 dw1 |= GEN7_WM_DEPTH_RESOLVE; 421 break; 422 case GEN6_HIZ_OP_HIZ_RESOLVE: 423 dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE; 424 break; 425 case GEN6_HIZ_OP_NONE: 426 break; 427 default: 428 assert(0); 429 break; 430 } 431 dw1 |= GEN7_WM_STATISTICS_ENABLE; 432 dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0; 433 dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5; 434 dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */ 435 if (params->use_wm_prog) { 436 dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */ 437 dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */ 438 } 439 440 if (params->num_samples > 1) { 441 dw1 |= GEN7_WM_MSRAST_ON_PATTERN; 442 if (prog_data && prog_data->persample_msaa_dispatch) 443 dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE; 444 else 445 dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL; 446 } else { 447 dw1 |= GEN7_WM_MSRAST_OFF_PIXEL; 448 dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE; 449 } 450 451 BEGIN_BATCH(3); 452 OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2)); 453 OUT_BATCH(dw1); 454 OUT_BATCH(dw2); 455 ADVANCE_BATCH(); 456} 457 458 459/** 460 * 3DSTATE_PS 461 * 462 * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite 463 * that, thread dispatch info must still be specified. 464 * - Maximum Number of Threads (dw4.24:31) must be nonzero, as the BSpec 465 * states that the valid range for this field is [0x3, 0x2f]. 466 * - A dispatch mode must be given; that is, at least one of the 467 * "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was 468 * discovered through simulator error messages. 469 */ 470static void 471gen7_blorp_emit_ps_config(struct brw_context *brw, 472 const brw_blorp_params *params, 473 uint32_t prog_offset, 474 brw_blorp_prog_data *prog_data) 475{ 476 struct intel_context *intel = &brw->intel; 477 uint32_t dw2, dw4, dw5; 478 const int max_threads_shift = brw->intel.is_haswell ? 479 HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT; 480 481 dw2 = dw4 = dw5 = 0; 482 dw4 |= (brw->max_wm_threads - 1) << max_threads_shift; 483 484 /* If there's a WM program, we need to do 16-pixel dispatch since that's 485 * what the program is compiled for. If there isn't, then it shouldn't 486 * matter because no program is actually being run. However, the hardware 487 * gets angry if we don't enable at least one dispatch mode, so just enable 488 * 16-pixel dispatch unconditionally. 489 */ 490 dw4 |= GEN7_PS_16_DISPATCH_ENABLE; 491 492 if (intel->is_haswell) 493 dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */ 494 if (params->use_wm_prog) { 495 dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */ 496 dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE; 497 dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0; 498 } 499 500 BEGIN_BATCH(8); 501 OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2)); 502 OUT_BATCH(params->use_wm_prog ? prog_offset : 0); 503 OUT_BATCH(dw2); 504 OUT_BATCH(0); 505 OUT_BATCH(dw4); 506 OUT_BATCH(dw5); 507 OUT_BATCH(0); 508 OUT_BATCH(0); 509 ADVANCE_BATCH(); 510} 511 512 513static void 514gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw, 515 const brw_blorp_params *params, 516 uint32_t wm_bind_bo_offset) 517{ 518 struct intel_context *intel = &brw->intel; 519 520 BEGIN_BATCH(2); 521 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2)); 522 OUT_BATCH(wm_bind_bo_offset); 523 ADVANCE_BATCH(); 524} 525 526 527static void 528gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw, 529 const brw_blorp_params *params, 530 uint32_t sampler_offset) 531{ 532 struct intel_context *intel = &brw->intel; 533 534 BEGIN_BATCH(2); 535 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2)); 536 OUT_BATCH(sampler_offset); 537 ADVANCE_BATCH(); 538} 539 540 541static void 542gen7_blorp_emit_constant_ps(struct brw_context *brw, 543 const brw_blorp_params *params, 544 uint32_t wm_push_const_offset) 545{ 546 struct intel_context *intel = &brw->intel; 547 548 /* Make sure the push constants fill an exact integer number of 549 * registers. 550 */ 551 assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0); 552 553 /* There must be at least one register worth of push constant data. */ 554 assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0); 555 556 /* Enable push constant buffer 0. */ 557 BEGIN_BATCH(7); 558 OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | 559 (7 - 2)); 560 OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS); 561 OUT_BATCH(0); 562 OUT_BATCH(wm_push_const_offset); 563 OUT_BATCH(0); 564 OUT_BATCH(0); 565 OUT_BATCH(0); 566 ADVANCE_BATCH(); 567} 568 569 570static void 571gen7_blorp_emit_depth_stencil_config(struct brw_context *brw, 572 const brw_blorp_params *params) 573{ 574 struct intel_context *intel = &brw->intel; 575 uint32_t draw_x, draw_y; 576 uint32_t tile_mask_x, tile_mask_y; 577 578 if (params->depth.mt) { 579 params->depth.get_draw_offsets(&draw_x, &draw_y); 580 gen6_blorp_compute_tile_masks(params, &tile_mask_x, &tile_mask_y); 581 } 582 583 /* 3DSTATE_DEPTH_BUFFER */ 584 { 585 uint32_t width, height; 586 params->depth.get_miplevel_dims(&width, &height); 587 588 uint32_t tile_x = draw_x & tile_mask_x; 589 uint32_t tile_y = draw_y & tile_mask_y; 590 uint32_t offset = 591 intel_region_get_aligned_offset(params->depth.mt->region, 592 draw_x & ~tile_mask_x, 593 draw_y & ~tile_mask_y); 594 595 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327 596 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth 597 * Coordinate Offset X/Y": 598 * 599 * "The 3 LSBs of both offsets must be zero to ensure correct 600 * alignment" 601 * 602 * We have no guarantee that tile_x and tile_y are correctly aligned, 603 * since they are determined by the mipmap layout, which is only aligned 604 * to multiples of 4. 605 * 606 * So, to avoid hanging the GPU, just smash the low order 3 bits of 607 * tile_x and tile_y to 0. This is a temporary workaround until we come 608 * up with a better solution. 609 */ 610 tile_x &= ~7; 611 tile_y &= ~7; 612 613 intel_emit_depth_stall_flushes(intel); 614 615 BEGIN_BATCH(7); 616 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); 617 uint32_t pitch_bytes = 618 params->depth.mt->region->pitch * params->depth.mt->region->cpp; 619 OUT_BATCH((pitch_bytes - 1) | 620 params->depth_format << 18 | 621 1 << 22 | /* hiz enable */ 622 1 << 28 | /* depth write */ 623 BRW_SURFACE_2D << 29); 624 OUT_RELOC(params->depth.mt->region->bo, 625 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 626 offset); 627 OUT_BATCH((width + tile_x - 1) << 4 | 628 (height + tile_y - 1) << 18); 629 OUT_BATCH(0); 630 OUT_BATCH(tile_x | 631 tile_y << 16); 632 OUT_BATCH(0); 633 ADVANCE_BATCH(); 634 } 635 636 /* 3DSTATE_HIER_DEPTH_BUFFER */ 637 { 638 struct intel_region *hiz_region = params->depth.mt->hiz_mt->region; 639 uint32_t hiz_offset = 640 intel_region_get_aligned_offset(hiz_region, 641 draw_x & ~tile_mask_x, 642 (draw_y & ~tile_mask_y) / 2); 643 644 BEGIN_BATCH(3); 645 OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); 646 OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1); 647 OUT_RELOC(hiz_region->bo, 648 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 649 hiz_offset); 650 ADVANCE_BATCH(); 651 } 652 653 /* 3DSTATE_STENCIL_BUFFER */ 654 { 655 BEGIN_BATCH(3); 656 OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2)); 657 OUT_BATCH(0); 658 OUT_BATCH(0); 659 ADVANCE_BATCH(); 660 } 661} 662 663 664static void 665gen7_blorp_emit_depth_disable(struct brw_context *brw, 666 const brw_blorp_params *params) 667{ 668 struct intel_context *intel = &brw->intel; 669 670 BEGIN_BATCH(7); 671 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); 672 OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29)); 673 OUT_BATCH(0); 674 OUT_BATCH(0); 675 OUT_BATCH(0); 676 OUT_BATCH(0); 677 OUT_BATCH(0); 678 ADVANCE_BATCH(); 679} 680 681 682/* 3DSTATE_CLEAR_PARAMS 683 * 684 * From the BSpec, Volume 2a.11 Windower, Section 1.5.6.3.2 685 * 3DSTATE_CLEAR_PARAMS: 686 * [DevIVB] 3DSTATE_CLEAR_PARAMS must always be programmed in the along 687 * with the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER, 688 * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER). 689 */ 690static void 691gen7_blorp_emit_clear_params(struct brw_context *brw, 692 const brw_blorp_params *params) 693{ 694 struct intel_context *intel = &brw->intel; 695 696 BEGIN_BATCH(3); 697 OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2)); 698 OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0); 699 OUT_BATCH(GEN7_DEPTH_CLEAR_VALID); 700 ADVANCE_BATCH(); 701} 702 703 704/* 3DPRIMITIVE */ 705static void 706gen7_blorp_emit_primitive(struct brw_context *brw, 707 const brw_blorp_params *params) 708{ 709 struct intel_context *intel = &brw->intel; 710 711 BEGIN_BATCH(7); 712 OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2)); 713 OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL | 714 _3DPRIM_RECTLIST); 715 OUT_BATCH(3); /* vertex count per instance */ 716 OUT_BATCH(0); 717 OUT_BATCH(1); /* instance count */ 718 OUT_BATCH(0); 719 OUT_BATCH(0); 720 ADVANCE_BATCH(); 721} 722 723 724/** 725 * \copydoc gen6_blorp_exec() 726 */ 727void 728gen7_blorp_exec(struct intel_context *intel, 729 const brw_blorp_params *params) 730{ 731 struct gl_context *ctx = &intel->ctx; 732 struct brw_context *brw = brw_context(ctx); 733 brw_blorp_prog_data *prog_data = NULL; 734 uint32_t cc_blend_state_offset = 0; 735 uint32_t cc_state_offset = 0; 736 uint32_t depthstencil_offset; 737 uint32_t wm_push_const_offset = 0; 738 uint32_t wm_bind_bo_offset = 0; 739 uint32_t sampler_offset = 0; 740 741 uint32_t prog_offset = params->get_wm_prog(brw, &prog_data); 742 gen6_blorp_emit_batch_head(brw, params); 743 gen7_allocate_push_constants(brw); 744 gen6_emit_3dstate_multisample(brw, params->num_samples); 745 gen6_emit_3dstate_sample_mask(brw, params->num_samples, 1.0, false); 746 gen6_blorp_emit_state_base_address(brw, params); 747 gen6_blorp_emit_vertices(brw, params); 748 gen7_blorp_emit_urb_config(brw, params); 749 if (params->use_wm_prog) { 750 cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params); 751 cc_state_offset = gen6_blorp_emit_cc_state(brw, params); 752 gen7_blorp_emit_blend_state_pointer(brw, params, cc_blend_state_offset); 753 gen7_blorp_emit_cc_state_pointer(brw, params, cc_state_offset); 754 } 755 depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params); 756 gen7_blorp_emit_depth_stencil_state_pointers(brw, params, 757 depthstencil_offset); 758 if (params->use_wm_prog) { 759 uint32_t wm_surf_offset_renderbuffer; 760 uint32_t wm_surf_offset_texture; 761 wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params); 762 wm_surf_offset_renderbuffer = 763 gen7_blorp_emit_surface_state(brw, params, ¶ms->dst, 764 I915_GEM_DOMAIN_RENDER, 765 I915_GEM_DOMAIN_RENDER, 766 true /* is_render_target */); 767 wm_surf_offset_texture = 768 gen7_blorp_emit_surface_state(brw, params, ¶ms->src, 769 I915_GEM_DOMAIN_SAMPLER, 0, 770 false /* is_render_target */); 771 wm_bind_bo_offset = 772 gen6_blorp_emit_binding_table(brw, params, 773 wm_surf_offset_renderbuffer, 774 wm_surf_offset_texture); 775 sampler_offset = gen7_blorp_emit_sampler_state(brw, params); 776 } 777 gen6_blorp_emit_vs_disable(brw, params); 778 gen7_blorp_emit_hs_disable(brw, params); 779 gen7_blorp_emit_te_disable(brw, params); 780 gen7_blorp_emit_ds_disable(brw, params); 781 gen6_blorp_emit_gs_disable(brw, params); 782 gen7_blorp_emit_streamout_disable(brw, params); 783 gen6_blorp_emit_clip_disable(brw, params); 784 gen7_blorp_emit_sf_config(brw, params); 785 gen7_blorp_emit_wm_config(brw, params, prog_data); 786 if (params->use_wm_prog) { 787 gen7_blorp_emit_binding_table_pointers_ps(brw, params, 788 wm_bind_bo_offset); 789 gen7_blorp_emit_sampler_state_pointers_ps(brw, params, sampler_offset); 790 gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset); 791 } 792 gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data); 793 gen7_blorp_emit_cc_viewport(brw, params); 794 795 if (params->depth.mt) 796 gen7_blorp_emit_depth_stencil_config(brw, params); 797 else 798 gen7_blorp_emit_depth_disable(brw, params); 799 gen7_blorp_emit_clear_params(brw, params); 800 gen6_blorp_emit_drawing_rectangle(brw, params); 801 gen7_blorp_emit_primitive(brw, params); 802 803 /* See comments above at first invocation of intel_flush() in 804 * gen6_blorp_emit_batch_head(). 805 */ 806 intel_flush(ctx); 807 808 /* Be safe. */ 809 brw->state.dirty.brw = ~0; 810 brw->state.dirty.cache = ~0; 811} 812