gen7_wm_surface_state.c revision 28fab4295e9631ca91c5ebdf26d1bee23011d57e
1/* 2 * Copyright © 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23#include "main/mtypes.h" 24#include "main/samplerobj.h" 25#include "program/prog_parameter.h" 26 27#include "intel_mipmap_tree.h" 28#include "intel_batchbuffer.h" 29#include "intel_tex.h" 30#include "intel_fbo.h" 31#include "intel_buffer_objects.h" 32 33#include "brw_context.h" 34#include "brw_state.h" 35#include "brw_defines.h" 36#include "brw_wm.h" 37 38void 39gen7_set_surface_tiling(struct gen7_surface_state *surf, uint32_t tiling) 40{ 41 switch (tiling) { 42 case I915_TILING_NONE: 43 surf->ss0.tiled_surface = 0; 44 surf->ss0.tile_walk = 0; 45 break; 46 case I915_TILING_X: 47 surf->ss0.tiled_surface = 1; 48 surf->ss0.tile_walk = BRW_TILEWALK_XMAJOR; 49 break; 50 case I915_TILING_Y: 51 surf->ss0.tiled_surface = 1; 52 surf->ss0.tile_walk = BRW_TILEWALK_YMAJOR; 53 break; 54 } 55} 56 57 58void 59gen7_set_surface_msaa(struct gen7_surface_state *surf, unsigned num_samples, 60 enum intel_msaa_layout layout) 61{ 62 if (num_samples > 4) 63 surf->ss4.num_multisamples = GEN7_SURFACE_MULTISAMPLECOUNT_8; 64 else if (num_samples > 1) 65 surf->ss4.num_multisamples = GEN7_SURFACE_MULTISAMPLECOUNT_4; 66 else 67 surf->ss4.num_multisamples = GEN7_SURFACE_MULTISAMPLECOUNT_1; 68 69 surf->ss4.multisampled_surface_storage_format = 70 layout == INTEL_MSAA_LAYOUT_IMS ? 71 GEN7_SURFACE_MSFMT_DEPTH_STENCIL : 72 GEN7_SURFACE_MSFMT_MSS; 73} 74 75 76void 77gen7_set_surface_mcs_info(struct brw_context *brw, 78 struct gen7_surface_state *surf, 79 uint32_t surf_offset, 80 const struct intel_mipmap_tree *mcs_mt, 81 bool is_render_target) 82{ 83 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address": 84 * 85 * "The MCS surface must be stored as Tile Y." 86 */ 87 assert(mcs_mt->region->tiling == I915_TILING_Y); 88 89 /* Compute the pitch in units of tiles. To do this we need to divide the 90 * pitch in bytes by 128, since a single Y-tile is 128 bytes wide. 91 */ 92 unsigned pitch_bytes = mcs_mt->region->pitch * mcs_mt->cpp; 93 unsigned pitch_tiles = pitch_bytes / 128; 94 95 /* The upper 20 bits of surface state DWORD 6 are the upper 20 bits of the 96 * GPU address of the MCS buffer; the lower 12 bits contain other control 97 * information. Since buffer addresses are always on 4k boundaries (and 98 * thus have their lower 12 bits zero), we can use an ordinary reloc to do 99 * the necessary address translation. 100 */ 101 assert ((mcs_mt->region->bo->offset & 0xfff) == 0); 102 surf->ss6.mcs_enabled.mcs_enable = 1; 103 surf->ss6.mcs_enabled.mcs_surface_pitch = pitch_tiles - 1; 104 surf->ss6.mcs_enabled.mcs_base_address = mcs_mt->region->bo->offset >> 12; 105 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 106 surf_offset + 107 offsetof(struct gen7_surface_state, ss6), 108 mcs_mt->region->bo, 109 surf->ss6.raw_data & 0xfff, 110 is_render_target ? I915_GEM_DOMAIN_RENDER 111 : I915_GEM_DOMAIN_SAMPLER, 112 is_render_target ? I915_GEM_DOMAIN_RENDER : 0); 113} 114 115 116void 117gen7_check_surface_setup(struct gen7_surface_state *surf, 118 bool is_render_target) 119{ 120 bool is_multisampled = 121 surf->ss4.num_multisamples != GEN7_SURFACE_MULTISAMPLECOUNT_1; 122 /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State > 123 * SURFACE_STATE > SURFACE_STATE for most messages [DevIVB]: Surface Array 124 * Spacing: 125 * 126 * If Multisampled Surface Storage Format is MSFMT_MSS and Number of 127 * Multisamples is not MULTISAMPLECOUNT_1, this field must be set to 128 * ARYSPC_LOD0. 129 */ 130 if (surf->ss4.multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS 131 && is_multisampled) 132 assert(surf->ss0.surface_array_spacing == GEN7_SURFACE_ARYSPC_LOD0); 133 134 /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State > 135 * SURFACE_STATE > SURFACE_STATE for most messages [DevIVB]: Multisampled 136 * Surface Storage Format: 137 * 138 * All multisampled render target surfaces must have this field set to 139 * MSFMT_MSS. 140 * 141 * But also: 142 * 143 * This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1. 144 */ 145 if (is_render_target && is_multisampled) { 146 assert(surf->ss4.multisampled_surface_storage_format == 147 GEN7_SURFACE_MSFMT_MSS); 148 } 149 150 /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State > 151 * SURFACE_STATE > SURFACE_STATE for most messages [DevIVB]: Multisampled 152 * Surface Storage Format: 153 * 154 * If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, Width 155 * is >= 8192 (meaning the actual surface width is >= 8193 pixels), this 156 * field must be set to MSFMT_MSS. 157 */ 158 if (surf->ss4.num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 && 159 surf->ss2.width >= 8192) { 160 assert(surf->ss4.multisampled_surface_storage_format == 161 GEN7_SURFACE_MSFMT_MSS); 162 } 163 164 /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State > 165 * SURFACE_STATE > SURFACE_STATE for most messages [DevIVB]: Multisampled 166 * Surface Storage Format: 167 * 168 * If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, 169 * ((Depth+1) * (Height+1)) is > 4,194,304, OR if the surface’s Number of 170 * Multisamples is MULTISAMPLECOUNT_4, ((Depth+1) * (Height+1)) is > 171 * 8,388,608, this field must be set to MSFMT_DEPTH_STENCIL.This field 172 * must be set to MSFMT_DEPTH_STENCIL if Surface Format is one of the 173 * following: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, or 174 * R24_UNORM_X8_TYPELESS. 175 * 176 * But also: 177 * 178 * This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1. 179 */ 180 uint32_t depth = surf->ss3.depth + 1; 181 uint32_t height = surf->ss2.height + 1; 182 if (surf->ss4.num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 && 183 depth * height > 4194304) { 184 assert(surf->ss4.multisampled_surface_storage_format == 185 GEN7_SURFACE_MSFMT_DEPTH_STENCIL); 186 } 187 if (surf->ss4.num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_4 && 188 depth * height > 8388608) { 189 assert(surf->ss4.multisampled_surface_storage_format == 190 GEN7_SURFACE_MSFMT_DEPTH_STENCIL); 191 } 192 if (is_multisampled) { 193 switch (surf->ss0.surface_format) { 194 case BRW_SURFACEFORMAT_I24X8_UNORM: 195 case BRW_SURFACEFORMAT_L24X8_UNORM: 196 case BRW_SURFACEFORMAT_A24X8_UNORM: 197 case BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS: 198 assert(surf->ss4.multisampled_surface_storage_format == 199 GEN7_SURFACE_MSFMT_DEPTH_STENCIL); 200 } 201 } 202} 203 204 205static void 206gen7_update_buffer_texture_surface(struct gl_context *ctx, 207 unsigned unit, 208 uint32_t *binding_table, 209 unsigned surf_index) 210{ 211 struct brw_context *brw = brw_context(ctx); 212 struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current; 213 struct gen7_surface_state *surf; 214 struct intel_buffer_object *intel_obj = 215 intel_buffer_object(tObj->BufferObject); 216 drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL; 217 gl_format format = tObj->_BufferObjectFormat; 218 int texel_size = _mesa_get_format_bytes(format); 219 220 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 221 sizeof(*surf), 32, &binding_table[surf_index]); 222 memset(surf, 0, sizeof(*surf)); 223 224 surf->ss0.surface_type = BRW_SURFACE_BUFFER; 225 surf->ss0.surface_format = brw_format_for_mesa_format(format); 226 227 surf->ss0.render_cache_read_write = 1; 228 229 if (surf->ss0.surface_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) { 230 _mesa_problem(NULL, "bad format %s for texture buffer\n", 231 _mesa_get_format_name(format)); 232 } 233 234 if (bo) { 235 surf->ss1.base_addr = bo->offset; /* reloc */ 236 237 /* Emit relocation to surface contents. Section 5.1.1 of the gen4 238 * bspec ("Data Cache") says that the data cache does not exist as 239 * a separate cache and is just the sampler cache. 240 */ 241 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 242 (binding_table[surf_index] + 243 offsetof(struct gen7_surface_state, ss1)), 244 bo, 0, 245 I915_GEM_DOMAIN_SAMPLER, 0); 246 247 int w = intel_obj->Base.Size / texel_size; 248 surf->ss2.width = w & 0x7f; /* bits 6:0 of size or width */ 249 surf->ss2.height = (w >> 7) & 0x1fff; /* bits 19:7 of size or width */ 250 surf->ss3.depth = (w >> 20) & 0x7f; /* bits 26:20 of size or width */ 251 surf->ss3.pitch = texel_size - 1; 252} else { 253 surf->ss1.base_addr = 0; 254 surf->ss2.width = 0; 255 surf->ss2.height = 0; 256 surf->ss3.depth = 0; 257 surf->ss3.pitch = 0; 258 } 259 260 gen7_set_surface_tiling(surf, I915_TILING_NONE); 261 262 gen7_check_surface_setup(surf, false /* is_render_target */); 263} 264 265static void 266gen7_update_texture_surface(struct gl_context *ctx, 267 unsigned unit, 268 uint32_t *binding_table, 269 unsigned surf_index) 270{ 271 struct brw_context *brw = brw_context(ctx); 272 struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current; 273 struct intel_texture_object *intelObj = intel_texture_object(tObj); 274 struct intel_mipmap_tree *mt = intelObj->mt; 275 struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel]; 276 struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit); 277 struct gen7_surface_state *surf; 278 int width, height, depth; 279 280 if (tObj->Target == GL_TEXTURE_BUFFER) { 281 gen7_update_buffer_texture_surface(ctx, unit, binding_table, surf_index); 282 return; 283 } 284 285 /* We don't support MSAA for textures. */ 286 assert(!mt->array_spacing_lod0); 287 assert(mt->num_samples <= 1); 288 289 intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth); 290 291 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 292 sizeof(*surf), 32, &binding_table[surf_index]); 293 memset(surf, 0, sizeof(*surf)); 294 295 if (mt->align_h == 4) 296 surf->ss0.vertical_alignment = 1; 297 if (mt->align_w == 8) 298 surf->ss0.horizontal_alignment = 1; 299 300 surf->ss0.surface_type = translate_tex_target(tObj->Target); 301 surf->ss0.surface_format = translate_tex_format(mt->format, 302 firstImage->InternalFormat, 303 tObj->DepthMode, 304 sampler->sRGBDecode); 305 if (tObj->Target == GL_TEXTURE_CUBE_MAP) { 306 surf->ss0.cube_pos_x = 1; 307 surf->ss0.cube_pos_y = 1; 308 surf->ss0.cube_pos_z = 1; 309 surf->ss0.cube_neg_x = 1; 310 surf->ss0.cube_neg_y = 1; 311 surf->ss0.cube_neg_z = 1; 312 } 313 314 surf->ss0.is_array = depth > 1 && tObj->Target != GL_TEXTURE_3D; 315 316 gen7_set_surface_tiling(surf, intelObj->mt->region->tiling); 317 318 /* ss0 remaining fields: 319 * - vert_line_stride (exists on gen6 but we ignore it) 320 * - vert_line_stride_ofs (exists on gen6 but we ignore it) 321 * - surface_array_spacing 322 * - render_cache_read_write (exists on gen6 but ignored here) 323 */ 324 325 surf->ss1.base_addr = 326 intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */ 327 328 surf->ss2.width = width - 1; 329 surf->ss2.height = height - 1; 330 331 surf->ss3.pitch = (intelObj->mt->region->pitch * intelObj->mt->cpp) - 1; 332 surf->ss3.depth = depth - 1; 333 334 /* ss4: ignored? */ 335 336 surf->ss5.mip_count = intelObj->_MaxLevel - tObj->BaseLevel; 337 surf->ss5.min_lod = 0; 338 339 /* ss5 remaining fields: 340 * - x_offset (N/A for textures?) 341 * - y_offset (ditto) 342 * - cache_control 343 */ 344 345 if (brw->intel.is_haswell) { 346 surf->ss7.shader_channel_select_r = HSW_SCS_RED; 347 surf->ss7.shader_channel_select_g = HSW_SCS_GREEN; 348 surf->ss7.shader_channel_select_b = HSW_SCS_BLUE; 349 surf->ss7.shader_channel_select_a = HSW_SCS_ALPHA; 350 } 351 352 /* Emit relocation to surface contents */ 353 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 354 binding_table[surf_index] + 355 offsetof(struct gen7_surface_state, ss1), 356 intelObj->mt->region->bo, intelObj->mt->offset, 357 I915_GEM_DOMAIN_SAMPLER, 0); 358 359 gen7_check_surface_setup(surf, false /* is_render_target */); 360} 361 362/** 363 * Create the constant buffer surface. Vertex/fragment shader constants will 364 * be read from this buffer with Data Port Read instructions/messages. 365 */ 366void 367gen7_create_constant_surface(struct brw_context *brw, 368 drm_intel_bo *bo, 369 uint32_t offset, 370 int width, 371 uint32_t *out_offset) 372{ 373 const GLint w = width - 1; 374 struct gen7_surface_state *surf; 375 376 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 377 sizeof(*surf), 32, out_offset); 378 memset(surf, 0, sizeof(*surf)); 379 380 surf->ss0.surface_type = BRW_SURFACE_BUFFER; 381 surf->ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT; 382 383 surf->ss0.render_cache_read_write = 1; 384 385 assert(bo); 386 surf->ss1.base_addr = bo->offset + offset; /* reloc */ 387 388 surf->ss2.width = w & 0x7f; /* bits 6:0 of size or width */ 389 surf->ss2.height = (w >> 7) & 0x1fff; /* bits 19:7 of size or width */ 390 surf->ss3.depth = (w >> 20) & 0x7f; /* bits 26:20 of size or width */ 391 surf->ss3.pitch = (16 - 1); /* stride between samples */ 392 gen7_set_surface_tiling(surf, I915_TILING_NONE); /* tiling now allowed */ 393 394 if (brw->intel.is_haswell) { 395 surf->ss7.shader_channel_select_r = HSW_SCS_RED; 396 surf->ss7.shader_channel_select_g = HSW_SCS_GREEN; 397 surf->ss7.shader_channel_select_b = HSW_SCS_BLUE; 398 surf->ss7.shader_channel_select_a = HSW_SCS_ALPHA; 399 } 400 401 /* Emit relocation to surface contents. Section 5.1.1 of the gen4 402 * bspec ("Data Cache") says that the data cache does not exist as 403 * a separate cache and is just the sampler cache. 404 */ 405 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 406 (*out_offset + 407 offsetof(struct gen7_surface_state, ss1)), 408 bo, offset, 409 I915_GEM_DOMAIN_SAMPLER, 0); 410 411 gen7_check_surface_setup(surf, false /* is_render_target */); 412} 413 414static void 415gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit) 416{ 417 /* From the Ivy bridge PRM, Vol4 Part1 p62 (Surface Type: Programming 418 * Notes): 419 * 420 * A null surface is used in instances where an actual surface is not 421 * bound. When a write message is generated to a null surface, no 422 * actual surface is written to. When a read message (including any 423 * sampling engine message) is generated to a null surface, the result 424 * is all zeros. Note that a null surface type is allowed to be used 425 * with all messages, even if it is not specificially indicated as 426 * supported. All of the remaining fields in surface state are ignored 427 * for null surfaces, with the following exceptions: Width, Height, 428 * Depth, LOD, and Render Target View Extent fields must match the 429 * depth buffer’s corresponding state for all render target surfaces, 430 * including null. 431 */ 432 struct intel_context *intel = &brw->intel; 433 struct gl_context *ctx = &intel->ctx; 434 struct gen7_surface_state *surf; 435 436 /* _NEW_BUFFERS */ 437 const struct gl_framebuffer *fb = ctx->DrawBuffer; 438 439 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 440 sizeof(*surf), 32, &brw->wm.surf_offset[unit]); 441 memset(surf, 0, sizeof(*surf)); 442 443 surf->ss0.surface_type = BRW_SURFACE_NULL; 444 surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; 445 446 surf->ss2.width = fb->Width - 1; 447 surf->ss2.height = fb->Height - 1; 448 449 /* From the Ivy bridge PRM, Vol4 Part1 p65 (Tiled Surface: Programming Notes): 450 * 451 * If Surface Type is SURFTYPE_NULL, this field must be TRUE. 452 */ 453 gen7_set_surface_tiling(surf, I915_TILING_Y); 454 455 gen7_check_surface_setup(surf, true /* is_render_target */); 456} 457 458/** 459 * Sets up a surface state structure to point at the given region. 460 * While it is only used for the front/back buffer currently, it should be 461 * usable for further buffers when doing ARB_draw_buffer support. 462 */ 463static void 464gen7_update_renderbuffer_surface(struct brw_context *brw, 465 struct gl_renderbuffer *rb, 466 unsigned int unit) 467{ 468 struct intel_context *intel = &brw->intel; 469 struct gl_context *ctx = &intel->ctx; 470 struct intel_renderbuffer *irb = intel_renderbuffer(rb); 471 struct intel_region *region = irb->mt->region; 472 struct gen7_surface_state *surf; 473 uint32_t tile_x, tile_y; 474 gl_format rb_format = intel_rb_format(irb); 475 476 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 477 sizeof(*surf), 32, &brw->wm.surf_offset[unit]); 478 memset(surf, 0, sizeof(*surf)); 479 480 /* Render targets can't use IMS layout */ 481 assert(irb->mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS); 482 483 if (irb->mt->align_h == 4) 484 surf->ss0.vertical_alignment = 1; 485 if (irb->mt->align_w == 8) 486 surf->ss0.horizontal_alignment = 1; 487 488 switch (rb_format) { 489 case MESA_FORMAT_SARGB8: 490 /* _NEW_BUFFERS 491 * 492 * Without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB surfaces to the 493 * blend/update as sRGB. 494 */ 495 if (ctx->Color.sRGBEnabled) 496 surf->ss0.surface_format = brw_format_for_mesa_format(rb_format); 497 else 498 surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; 499 break; 500 default: 501 assert(brw_render_target_supported(intel, rb)); 502 surf->ss0.surface_format = brw->render_target_format[rb_format]; 503 if (unlikely(!brw->format_supported_as_render_target[rb_format])) { 504 _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n", 505 __FUNCTION__, _mesa_get_format_name(rb_format)); 506 } 507 break; 508 } 509 510 surf->ss0.surface_type = BRW_SURFACE_2D; 511 surf->ss0.surface_array_spacing = irb->mt->array_spacing_lod0 ? 512 GEN7_SURFACE_ARYSPC_LOD0 : GEN7_SURFACE_ARYSPC_FULL; 513 514 /* reloc */ 515 surf->ss1.base_addr = intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y); 516 surf->ss1.base_addr += region->bo->offset; /* reloc */ 517 518 assert(brw->has_surface_tile_offset); 519 /* Note that the low bits of these fields are missing, so 520 * there's the possibility of getting in trouble. 521 */ 522 assert(tile_x % 4 == 0); 523 assert(tile_y % 2 == 0); 524 surf->ss5.x_offset = tile_x / 4; 525 surf->ss5.y_offset = tile_y / 2; 526 527 surf->ss2.width = rb->Width - 1; 528 surf->ss2.height = rb->Height - 1; 529 gen7_set_surface_tiling(surf, region->tiling); 530 surf->ss3.pitch = (region->pitch * region->cpp) - 1; 531 532 gen7_set_surface_msaa(surf, irb->mt->num_samples, irb->mt->msaa_layout); 533 534 if (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) { 535 gen7_set_surface_mcs_info(brw, surf, brw->wm.surf_offset[unit], 536 irb->mt->mcs_mt, true /* is_render_target */); 537 } 538 539 if (intel->is_haswell) { 540 surf->ss7.shader_channel_select_r = HSW_SCS_RED; 541 surf->ss7.shader_channel_select_g = HSW_SCS_GREEN; 542 surf->ss7.shader_channel_select_b = HSW_SCS_BLUE; 543 surf->ss7.shader_channel_select_a = HSW_SCS_ALPHA; 544 } 545 546 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 547 brw->wm.surf_offset[unit] + 548 offsetof(struct gen7_surface_state, ss1), 549 region->bo, 550 surf->ss1.base_addr - region->bo->offset, 551 I915_GEM_DOMAIN_RENDER, 552 I915_GEM_DOMAIN_RENDER); 553 554 gen7_check_surface_setup(surf, true /* is_render_target */); 555} 556 557void 558gen7_init_vtable_surface_functions(struct brw_context *brw) 559{ 560 struct intel_context *intel = &brw->intel; 561 562 intel->vtbl.update_texture_surface = gen7_update_texture_surface; 563 intel->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface; 564 intel->vtbl.update_null_renderbuffer_surface = 565 gen7_update_null_renderbuffer_surface; 566 intel->vtbl.create_constant_surface = gen7_create_constant_surface; 567} 568