intel_blit.c revision 2e5a1a254ed81b1d3efa6064f48183eefac784d0
1/************************************************************************** 2 * 3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 29#include "main/mtypes.h" 30#include "main/context.h" 31#include "main/enums.h" 32#include "main/colormac.h" 33 34#include "intel_blit.h" 35#include "intel_buffers.h" 36#include "intel_context.h" 37#include "intel_fbo.h" 38#include "intel_reg.h" 39#include "intel_regions.h" 40#include "intel_batchbuffer.h" 41#include "intel_mipmap_tree.h" 42 43#define FILE_DEBUG_FLAG DEBUG_BLIT 44 45static GLuint translate_raster_op(GLenum logicop) 46{ 47 switch(logicop) { 48 case GL_CLEAR: return 0x00; 49 case GL_AND: return 0x88; 50 case GL_AND_REVERSE: return 0x44; 51 case GL_COPY: return 0xCC; 52 case GL_AND_INVERTED: return 0x22; 53 case GL_NOOP: return 0xAA; 54 case GL_XOR: return 0x66; 55 case GL_OR: return 0xEE; 56 case GL_NOR: return 0x11; 57 case GL_EQUIV: return 0x99; 58 case GL_INVERT: return 0x55; 59 case GL_OR_REVERSE: return 0xDD; 60 case GL_COPY_INVERTED: return 0x33; 61 case GL_OR_INVERTED: return 0xBB; 62 case GL_NAND: return 0x77; 63 case GL_SET: return 0xFF; 64 default: return 0; 65 } 66} 67 68static uint32_t 69br13_for_cpp(int cpp) 70{ 71 switch (cpp) { 72 case 4: 73 return BR13_8888; 74 break; 75 case 2: 76 return BR13_565; 77 break; 78 case 1: 79 return BR13_8; 80 break; 81 default: 82 assert(0); 83 return 0; 84 } 85} 86 87/* Copy BitBlt 88 */ 89bool 90intelEmitCopyBlit(struct intel_context *intel, 91 GLuint cpp, 92 GLshort src_pitch, 93 drm_intel_bo *src_buffer, 94 GLuint src_offset, 95 uint32_t src_tiling, 96 GLshort dst_pitch, 97 drm_intel_bo *dst_buffer, 98 GLuint dst_offset, 99 uint32_t dst_tiling, 100 GLshort src_x, GLshort src_y, 101 GLshort dst_x, GLshort dst_y, 102 GLshort w, GLshort h, 103 GLenum logic_op) 104{ 105 GLuint CMD, BR13, pass = 0; 106 int dst_y2 = dst_y + h; 107 int dst_x2 = dst_x + w; 108 drm_intel_bo *aper_array[3]; 109 BATCH_LOCALS; 110 111 if (dst_tiling != I915_TILING_NONE) { 112 if (dst_offset & 4095) 113 return false; 114 if (dst_tiling == I915_TILING_Y) 115 return false; 116 } 117 if (src_tiling != I915_TILING_NONE) { 118 if (src_offset & 4095) 119 return false; 120 if (src_tiling == I915_TILING_Y) 121 return false; 122 } 123 124 /* do space check before going any further */ 125 do { 126 aper_array[0] = intel->batch.bo; 127 aper_array[1] = dst_buffer; 128 aper_array[2] = src_buffer; 129 130 if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) { 131 intel_batchbuffer_flush(intel); 132 pass++; 133 } else 134 break; 135 } while (pass < 2); 136 137 if (pass >= 2) 138 return false; 139 140 intel_batchbuffer_require_space(intel, 8 * 4, true); 141 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n", 142 __FUNCTION__, 143 src_buffer, src_pitch, src_offset, src_x, src_y, 144 dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h); 145 146 src_pitch *= cpp; 147 dst_pitch *= cpp; 148 149 /* For big formats (such as floating point), do the copy using 32bpp and 150 * multiply the coordinates. 151 */ 152 if (cpp > 4) { 153 assert(cpp % 4 == 0); 154 dst_x *= cpp / 4; 155 dst_x2 *= cpp / 4; 156 src_x *= cpp / 4; 157 cpp = 4; 158 } 159 160 BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16; 161 162 switch (cpp) { 163 case 1: 164 case 2: 165 CMD = XY_SRC_COPY_BLT_CMD; 166 break; 167 case 4: 168 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 169 break; 170 default: 171 return false; 172 } 173 174#ifndef I915 175 if (dst_tiling != I915_TILING_NONE) { 176 CMD |= XY_DST_TILED; 177 dst_pitch /= 4; 178 } 179 if (src_tiling != I915_TILING_NONE) { 180 CMD |= XY_SRC_TILED; 181 src_pitch /= 4; 182 } 183#endif 184 185 if (dst_y2 <= dst_y || dst_x2 <= dst_x) { 186 return true; 187 } 188 189 assert(dst_x < dst_x2); 190 assert(dst_y < dst_y2); 191 192 BEGIN_BATCH_BLT(8); 193 OUT_BATCH(CMD); 194 OUT_BATCH(BR13 | (uint16_t)dst_pitch); 195 OUT_BATCH((dst_y << 16) | dst_x); 196 OUT_BATCH((dst_y2 << 16) | dst_x2); 197 OUT_RELOC_FENCED(dst_buffer, 198 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 199 dst_offset); 200 OUT_BATCH((src_y << 16) | src_x); 201 OUT_BATCH((uint16_t)src_pitch); 202 OUT_RELOC_FENCED(src_buffer, 203 I915_GEM_DOMAIN_RENDER, 0, 204 src_offset); 205 ADVANCE_BATCH(); 206 207 intel_batchbuffer_emit_mi_flush(intel); 208 209 return true; 210} 211 212 213/** 214 * Use blitting to clear the renderbuffers named by 'flags'. 215 * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field 216 * since that might include software renderbuffers or renderbuffers 217 * which we're clearing with triangles. 218 * \param mask bitmask of BUFFER_BIT_* values indicating buffers to clear 219 */ 220GLbitfield 221intelClearWithBlit(struct gl_context *ctx, GLbitfield mask) 222{ 223 struct intel_context *intel = intel_context(ctx); 224 struct gl_framebuffer *fb = ctx->DrawBuffer; 225 GLuint clear_depth_value, clear_depth_mask; 226 GLint cx, cy, cw, ch; 227 GLbitfield fail_mask = 0; 228 BATCH_LOCALS; 229 230 /* 231 * Compute values for clearing the buffers. 232 */ 233 clear_depth_value = 0; 234 clear_depth_mask = 0; 235 if (mask & BUFFER_BIT_DEPTH) { 236 clear_depth_value = (GLuint) (fb->_DepthMax * ctx->Depth.Clear); 237 clear_depth_mask = XY_BLT_WRITE_RGB; 238 } 239 if (mask & BUFFER_BIT_STENCIL) { 240 clear_depth_value |= (ctx->Stencil.Clear & 0xff) << 24; 241 clear_depth_mask |= XY_BLT_WRITE_ALPHA; 242 } 243 244 cx = fb->_Xmin; 245 if (fb->Name == 0) 246 cy = ctx->DrawBuffer->Height - fb->_Ymax; 247 else 248 cy = fb->_Ymin; 249 cw = fb->_Xmax - fb->_Xmin; 250 ch = fb->_Ymax - fb->_Ymin; 251 252 if (cw == 0 || ch == 0) 253 return 0; 254 255 /* Loop over all renderbuffers */ 256 mask &= (1 << BUFFER_COUNT) - 1; 257 while (mask) { 258 GLuint buf = _mesa_ffs(mask) - 1; 259 bool is_depth_stencil = buf == BUFFER_DEPTH || buf == BUFFER_STENCIL; 260 struct intel_renderbuffer *irb; 261 int x1, y1, x2, y2; 262 uint32_t clear_val; 263 uint32_t BR13, CMD; 264 int pitch, cpp; 265 drm_intel_bo *aper_array[2]; 266 267 mask &= ~(1 << buf); 268 269 irb = intel_get_renderbuffer(fb, buf); 270 if (irb == NULL || irb->region == NULL || irb->region->bo == NULL) { 271 fail_mask |= 1 << buf; 272 continue; 273 } 274 275 /* OK, clear this renderbuffer */ 276 x1 = cx + irb->draw_x; 277 y1 = cy + irb->draw_y; 278 x2 = cx + cw + irb->draw_x; 279 y2 = cy + ch + irb->draw_y; 280 281 pitch = irb->region->pitch; 282 cpp = irb->region->cpp; 283 284 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n", 285 __FUNCTION__, 286 irb->region->bo, (pitch * cpp), 287 x1, y1, x2 - x1, y2 - y1); 288 289 BR13 = 0xf0 << 16; 290 CMD = XY_COLOR_BLT_CMD; 291 292 /* Setup the blit command */ 293 if (cpp == 4) { 294 if (is_depth_stencil) { 295 CMD |= clear_depth_mask; 296 } else { 297 /* clearing RGBA */ 298 CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 299 } 300 } 301 302 assert(irb->region->tiling != I915_TILING_Y); 303 304#ifndef I915 305 if (irb->region->tiling != I915_TILING_NONE) { 306 CMD |= XY_DST_TILED; 307 pitch /= 4; 308 } 309#endif 310 BR13 |= (pitch * cpp); 311 312 if (is_depth_stencil) { 313 clear_val = clear_depth_value; 314 } else { 315 uint8_t clear[4]; 316 GLfloat *color = ctx->Color.ClearColor.f; 317 318 _mesa_unclamped_float_rgba_to_ubyte(clear, color); 319 320 switch (irb->Base.Format) { 321 case MESA_FORMAT_ARGB8888: 322 case MESA_FORMAT_XRGB8888: 323 clear_val = PACK_COLOR_8888(clear[3], clear[0], 324 clear[1], clear[2]); 325 break; 326 case MESA_FORMAT_RGB565: 327 clear_val = PACK_COLOR_565(clear[0], clear[1], clear[2]); 328 break; 329 case MESA_FORMAT_ARGB4444: 330 clear_val = PACK_COLOR_4444(clear[3], clear[0], 331 clear[1], clear[2]); 332 break; 333 case MESA_FORMAT_ARGB1555: 334 clear_val = PACK_COLOR_1555(clear[3], clear[0], 335 clear[1], clear[2]); 336 break; 337 case MESA_FORMAT_A8: 338 clear_val = PACK_COLOR_8888(clear[3], clear[3], 339 clear[3], clear[3]); 340 break; 341 default: 342 fail_mask |= 1 << buf; 343 continue; 344 } 345 } 346 347 BR13 |= br13_for_cpp(cpp); 348 349 assert(x1 < x2); 350 assert(y1 < y2); 351 352 /* do space check before going any further */ 353 aper_array[0] = intel->batch.bo; 354 aper_array[1] = irb->region->bo; 355 356 if (drm_intel_bufmgr_check_aperture_space(aper_array, 357 ARRAY_SIZE(aper_array)) != 0) { 358 intel_batchbuffer_flush(intel); 359 } 360 361 BEGIN_BATCH_BLT(6); 362 OUT_BATCH(CMD); 363 OUT_BATCH(BR13); 364 OUT_BATCH((y1 << 16) | x1); 365 OUT_BATCH((y2 << 16) | x2); 366 OUT_RELOC_FENCED(irb->region->bo, 367 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 368 0); 369 OUT_BATCH(clear_val); 370 ADVANCE_BATCH(); 371 372 if (intel->always_flush_cache) 373 intel_batchbuffer_emit_mi_flush(intel); 374 375 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) 376 mask &= ~(BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL); 377 } 378 379 return fail_mask; 380} 381 382bool 383intelEmitImmediateColorExpandBlit(struct intel_context *intel, 384 GLuint cpp, 385 GLubyte *src_bits, GLuint src_size, 386 GLuint fg_color, 387 GLshort dst_pitch, 388 drm_intel_bo *dst_buffer, 389 GLuint dst_offset, 390 uint32_t dst_tiling, 391 GLshort x, GLshort y, 392 GLshort w, GLshort h, 393 GLenum logic_op) 394{ 395 int dwords = ALIGN(src_size, 8) / 4; 396 uint32_t opcode, br13, blit_cmd; 397 398 if (dst_tiling != I915_TILING_NONE) { 399 if (dst_offset & 4095) 400 return false; 401 if (dst_tiling == I915_TILING_Y) 402 return false; 403 } 404 405 assert( logic_op - GL_CLEAR >= 0 ); 406 assert( logic_op - GL_CLEAR < 0x10 ); 407 assert(dst_pitch > 0); 408 409 if (w < 0 || h < 0) 410 return true; 411 412 dst_pitch *= cpp; 413 414 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n", 415 __FUNCTION__, 416 dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords); 417 418 intel_batchbuffer_require_space(intel, 419 (8 * 4) + 420 (3 * 4) + 421 dwords * 4, true); 422 423 opcode = XY_SETUP_BLT_CMD; 424 if (cpp == 4) 425 opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 426#ifndef I915 427 if (dst_tiling != I915_TILING_NONE) { 428 opcode |= XY_DST_TILED; 429 dst_pitch /= 4; 430 } 431#endif 432 433 br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29); 434 br13 |= br13_for_cpp(cpp); 435 436 blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */ 437 if (dst_tiling != I915_TILING_NONE) 438 blit_cmd |= XY_DST_TILED; 439 440 BEGIN_BATCH_BLT(8 + 3); 441 OUT_BATCH(opcode); 442 OUT_BATCH(br13); 443 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */ 444 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */ 445 OUT_RELOC_FENCED(dst_buffer, 446 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 447 dst_offset); 448 OUT_BATCH(0); /* bg */ 449 OUT_BATCH(fg_color); /* fg */ 450 OUT_BATCH(0); /* pattern base addr */ 451 452 OUT_BATCH(blit_cmd | ((3 - 2) + dwords)); 453 OUT_BATCH((y << 16) | x); 454 OUT_BATCH(((y + h) << 16) | (x + w)); 455 ADVANCE_BATCH(); 456 457 intel_batchbuffer_data(intel, src_bits, dwords * 4, true); 458 459 intel_batchbuffer_emit_mi_flush(intel); 460 461 return true; 462} 463 464/* We don't have a memmove-type blit like some other hardware, so we'll do a 465 * rectangular blit covering a large space, then emit 1-scanline blit at the 466 * end to cover the last if we need. 467 */ 468void 469intel_emit_linear_blit(struct intel_context *intel, 470 drm_intel_bo *dst_bo, 471 unsigned int dst_offset, 472 drm_intel_bo *src_bo, 473 unsigned int src_offset, 474 unsigned int size) 475{ 476 GLuint pitch, height; 477 bool ok; 478 479 /* The pitch given to the GPU must be DWORD aligned, and 480 * we want width to match pitch. Max width is (1 << 15 - 1), 481 * rounding that down to the nearest DWORD is 1 << 15 - 4 482 */ 483 pitch = MIN2(size, (1 << 15) - 4); 484 height = size / pitch; 485 ok = intelEmitCopyBlit(intel, 1, 486 pitch, src_bo, src_offset, I915_TILING_NONE, 487 pitch, dst_bo, dst_offset, I915_TILING_NONE, 488 0, 0, /* src x/y */ 489 0, 0, /* dst x/y */ 490 pitch, height, /* w, h */ 491 GL_COPY); 492 assert(ok); 493 494 src_offset += pitch * height; 495 dst_offset += pitch * height; 496 size -= pitch * height; 497 assert (size < (1 << 15)); 498 assert ((size & 3) == 0); /* Pitch must be DWORD aligned */ 499 if (size != 0) { 500 ok = intelEmitCopyBlit(intel, 1, 501 size, src_bo, src_offset, I915_TILING_NONE, 502 size, dst_bo, dst_offset, I915_TILING_NONE, 503 0, 0, /* src x/y */ 504 0, 0, /* dst x/y */ 505 size, 1, /* w, h */ 506 GL_COPY); 507 assert(ok); 508 } 509} 510 511/** 512 * Used to initialize the alpha value of an ARGB8888 teximage after 513 * loading it from an XRGB8888 source. 514 * 515 * This is very common with glCopyTexImage2D(). 516 */ 517void 518intel_set_teximage_alpha_to_one(struct gl_context *ctx, 519 struct intel_texture_image *intel_image) 520{ 521 struct intel_context *intel = intel_context(ctx); 522 unsigned int image_x, image_y; 523 uint32_t x1, y1, x2, y2; 524 uint32_t BR13, CMD; 525 int pitch, cpp; 526 drm_intel_bo *aper_array[2]; 527 struct intel_region *region = intel_image->mt->region; 528 int width, height, depth; 529 BATCH_LOCALS; 530 531 intel_miptree_get_dimensions_for_image(&intel_image->base.Base, 532 &width, &height, &depth); 533 assert(depth == 1); 534 535 assert(intel_image->base.Base.TexFormat == MESA_FORMAT_ARGB8888); 536 537 /* get dest x/y in destination texture */ 538 intel_miptree_get_image_offset(intel_image->mt, 539 intel_image->base.Base.Level, 540 intel_image->base.Base.Face, 541 0, 542 &image_x, &image_y); 543 544 x1 = image_x; 545 y1 = image_y; 546 x2 = image_x + width; 547 y2 = image_y + height; 548 549 pitch = region->pitch; 550 cpp = region->cpp; 551 552 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n", 553 __FUNCTION__, 554 intel_image->mt->region->bo, (pitch * cpp), 555 x1, y1, x2 - x1, y2 - y1); 556 557 BR13 = br13_for_cpp(cpp) | 0xf0 << 16; 558 CMD = XY_COLOR_BLT_CMD; 559 CMD |= XY_BLT_WRITE_ALPHA; 560 561 assert(region->tiling != I915_TILING_Y); 562 563#ifndef I915 564 if (region->tiling != I915_TILING_NONE) { 565 CMD |= XY_DST_TILED; 566 pitch /= 4; 567 } 568#endif 569 BR13 |= (pitch * cpp); 570 571 /* do space check before going any further */ 572 aper_array[0] = intel->batch.bo; 573 aper_array[1] = region->bo; 574 575 if (drm_intel_bufmgr_check_aperture_space(aper_array, 576 ARRAY_SIZE(aper_array)) != 0) { 577 intel_batchbuffer_flush(intel); 578 } 579 580 BEGIN_BATCH_BLT(6); 581 OUT_BATCH(CMD); 582 OUT_BATCH(BR13); 583 OUT_BATCH((y1 << 16) | x1); 584 OUT_BATCH((y2 << 16) | x2); 585 OUT_RELOC_FENCED(region->bo, 586 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 587 0); 588 OUT_BATCH(0xffffffff); /* white, but only alpha gets written */ 589 ADVANCE_BATCH(); 590 591 intel_batchbuffer_emit_mi_flush(intel); 592} 593