intel_blit.c revision 6a49473ab5797b1e6ce021e396902f9cb77674ef
1/************************************************************************** 2 * 3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 29#include <stdio.h> 30#include <errno.h> 31 32#include "main/mtypes.h" 33#include "main/context.h" 34#include "main/enums.h" 35#include "main/texformat.h" 36#include "main/colormac.h" 37 38#include "intel_blit.h" 39#include "intel_buffers.h" 40#include "intel_context.h" 41#include "intel_fbo.h" 42#include "intel_reg.h" 43#include "intel_regions.h" 44#include "intel_batchbuffer.h" 45#include "intel_chipset.h" 46 47#define FILE_DEBUG_FLAG DEBUG_BLIT 48 49/** 50 * Copy the back color buffer to the front color buffer. 51 * Used for SwapBuffers(). 52 */ 53void 54intelCopyBuffer(const __DRIdrawablePrivate * dPriv, 55 const drm_clip_rect_t * rect) 56{ 57 58 struct intel_context *intel; 59 const intelScreenPrivate *intelScreen; 60 61 DBG("%s\n", __FUNCTION__); 62 63 assert(dPriv); 64 65 intel = intelScreenContext(dPriv->driScreenPriv->private); 66 if (!intel) 67 return; 68 69 intelScreen = intel->intelScreen; 70 71 /* The LOCK_HARDWARE is required for the cliprects. Buffer offsets 72 * should work regardless. 73 */ 74 LOCK_HARDWARE(intel); 75 76 if (dPriv && dPriv->numClipRects) { 77 struct intel_framebuffer *intel_fb = dPriv->driverPrivate; 78 struct intel_region *src, *dst; 79 int nbox = dPriv->numClipRects; 80 drm_clip_rect_t *pbox = dPriv->pClipRects; 81 int cpp; 82 int src_pitch, dst_pitch; 83 unsigned short src_x, src_y; 84 int BR13, CMD; 85 int i; 86 dri_bo *aper_array[3]; 87 88 src = intel_get_rb_region(&intel_fb->Base, BUFFER_BACK_LEFT); 89 dst = intel_get_rb_region(&intel_fb->Base, BUFFER_FRONT_LEFT); 90 91 src_pitch = src->pitch * src->cpp; 92 dst_pitch = dst->pitch * dst->cpp; 93 94 cpp = src->cpp; 95 96 ASSERT(intel_fb); 97 ASSERT(intel_fb->Base.Name == 0); /* Not a user-created FBO */ 98 ASSERT(src); 99 ASSERT(dst); 100 ASSERT(src->cpp == dst->cpp); 101 102 if (cpp == 2) { 103 BR13 = (0xCC << 16) | BR13_565; 104 CMD = XY_SRC_COPY_BLT_CMD; 105 } 106 else { 107 BR13 = (0xCC << 16) | BR13_8888; 108 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 109 } 110 111#ifndef I915 112 if (src->tiling != I915_TILING_NONE) { 113 CMD |= XY_SRC_TILED; 114 src_pitch /= 4; 115 } 116 if (dst->tiling != I915_TILING_NONE) { 117 CMD |= XY_DST_TILED; 118 dst_pitch /= 4; 119 } 120#endif 121 /* do space/cliprects check before going any further */ 122 intel_batchbuffer_require_space(intel->batch, 8 * 4, 123 REFERENCES_CLIPRECTS); 124 again: 125 aper_array[0] = intel->batch->buf; 126 aper_array[1] = dst->buffer; 127 aper_array[2] = src->buffer; 128 129 if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) { 130 intel_batchbuffer_flush(intel->batch); 131 goto again; 132 } 133 134 for (i = 0; i < nbox; i++, pbox++) { 135 drm_clip_rect_t box = *pbox; 136 137 if (rect) { 138 if (!intel_intersect_cliprects(&box, &box, rect)) 139 continue; 140 } 141 142 if (box.x1 >= box.x2 || 143 box.y1 >= box.y2) 144 continue; 145 146 assert(box.x1 < box.x2); 147 assert(box.y1 < box.y2); 148 src_x = box.x1 - dPriv->x + dPriv->backX; 149 src_y = box.y1 - dPriv->y + dPriv->backY; 150 151 BEGIN_BATCH(8, REFERENCES_CLIPRECTS); 152 OUT_BATCH(CMD); 153 OUT_BATCH(BR13 | dst_pitch); 154 OUT_BATCH((box.y1 << 16) | box.x1); 155 OUT_BATCH((box.y2 << 16) | box.x2); 156 157 OUT_RELOC(dst->buffer, 158 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 159 0); 160 OUT_BATCH((src_y << 16) | src_x); 161 OUT_BATCH(src_pitch); 162 OUT_RELOC(src->buffer, 163 I915_GEM_DOMAIN_RENDER, 0, 164 0); 165 ADVANCE_BATCH(); 166 } 167 168 /* Flush the rendering and the batch so that the results all land on the 169 * screen in a timely fashion. 170 */ 171 intel_batchbuffer_emit_mi_flush(intel->batch); 172 intel_batchbuffer_flush(intel->batch); 173 } 174 175 UNLOCK_HARDWARE(intel); 176} 177 178static GLuint translate_raster_op(GLenum logicop) 179{ 180 switch(logicop) { 181 case GL_CLEAR: return 0x00; 182 case GL_AND: return 0x88; 183 case GL_AND_REVERSE: return 0x44; 184 case GL_COPY: return 0xCC; 185 case GL_AND_INVERTED: return 0x22; 186 case GL_NOOP: return 0xAA; 187 case GL_XOR: return 0x66; 188 case GL_OR: return 0xEE; 189 case GL_NOR: return 0x11; 190 case GL_EQUIV: return 0x99; 191 case GL_INVERT: return 0x55; 192 case GL_OR_REVERSE: return 0xDD; 193 case GL_COPY_INVERTED: return 0x33; 194 case GL_OR_INVERTED: return 0xBB; 195 case GL_NAND: return 0x77; 196 case GL_SET: return 0xFF; 197 default: return 0; 198 } 199} 200 201 202/* Copy BitBlt 203 */ 204void 205intelEmitCopyBlit(struct intel_context *intel, 206 GLuint cpp, 207 GLshort src_pitch, 208 dri_bo *src_buffer, 209 GLuint src_offset, 210 uint32_t src_tiling, 211 GLshort dst_pitch, 212 dri_bo *dst_buffer, 213 GLuint dst_offset, 214 uint32_t dst_tiling, 215 GLshort src_x, GLshort src_y, 216 GLshort dst_x, GLshort dst_y, 217 GLshort w, GLshort h, 218 GLenum logic_op) 219{ 220 GLuint CMD, BR13, pass = 0; 221 int dst_y2 = dst_y + h; 222 int dst_x2 = dst_x + w; 223 dri_bo *aper_array[3]; 224 BATCH_LOCALS; 225 226 /* do space/cliprects check before going any further */ 227 do { 228 aper_array[0] = intel->batch->buf; 229 aper_array[1] = dst_buffer; 230 aper_array[2] = src_buffer; 231 232 if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) { 233 intel_batchbuffer_flush(intel->batch); 234 pass++; 235 } else 236 break; 237 } while (pass < 2); 238 239 if (pass >= 2) { 240 GLboolean locked = GL_FALSE; 241 if (!intel->locked) { 242 LOCK_HARDWARE(intel); 243 locked = GL_TRUE; 244 } 245 246 dri_bo_map(dst_buffer, GL_TRUE); 247 dri_bo_map(src_buffer, GL_FALSE); 248 _mesa_copy_rect((GLubyte *)dst_buffer->virtual + dst_offset, 249 cpp, 250 dst_pitch, 251 dst_x, dst_y, 252 w, h, 253 (GLubyte *)src_buffer->virtual + src_offset, 254 src_pitch, 255 src_x, src_y); 256 257 dri_bo_unmap(src_buffer); 258 dri_bo_unmap(dst_buffer); 259 260 if (locked) 261 UNLOCK_HARDWARE(intel); 262 263 return; 264 } 265 266 intel_batchbuffer_require_space(intel->batch, 8 * 4, NO_LOOP_CLIPRECTS); 267 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n", 268 __FUNCTION__, 269 src_buffer, src_pitch, src_offset, src_x, src_y, 270 dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h); 271 272 src_pitch *= cpp; 273 dst_pitch *= cpp; 274 275 BR13 = translate_raster_op(logic_op) << 16; 276 277 switch (cpp) { 278 case 1: 279 CMD = XY_SRC_COPY_BLT_CMD; 280 break; 281 case 2: 282 BR13 |= BR13_565; 283 CMD = XY_SRC_COPY_BLT_CMD; 284 break; 285 case 4: 286 BR13 |= BR13_8888; 287 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 288 break; 289 default: 290 return; 291 } 292 293#ifndef I915 294 if (dst_tiling != I915_TILING_NONE) { 295 CMD |= XY_DST_TILED; 296 dst_pitch /= 4; 297 } 298 if (src_tiling != I915_TILING_NONE) { 299 CMD |= XY_SRC_TILED; 300 src_pitch /= 4; 301 } 302#endif 303 304 if (dst_y2 <= dst_y || dst_x2 <= dst_x) { 305 return; 306 } 307 308 assert(dst_x < dst_x2); 309 assert(dst_y < dst_y2); 310 311 BEGIN_BATCH(8, NO_LOOP_CLIPRECTS); 312 OUT_BATCH(CMD); 313 OUT_BATCH(BR13 | (uint16_t)dst_pitch); 314 OUT_BATCH((dst_y << 16) | dst_x); 315 OUT_BATCH((dst_y2 << 16) | dst_x2); 316 OUT_RELOC(dst_buffer, 317 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 318 dst_offset); 319 OUT_BATCH((src_y << 16) | src_x); 320 OUT_BATCH((uint16_t)src_pitch); 321 OUT_RELOC(src_buffer, 322 I915_GEM_DOMAIN_RENDER, 0, 323 src_offset); 324 ADVANCE_BATCH(); 325 326 intel_batchbuffer_emit_mi_flush(intel->batch); 327} 328 329 330/** 331 * Use blitting to clear the renderbuffers named by 'flags'. 332 * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field 333 * since that might include software renderbuffers or renderbuffers 334 * which we're clearing with triangles. 335 * \param mask bitmask of BUFFER_BIT_* values indicating buffers to clear 336 */ 337void 338intelClearWithBlit(GLcontext *ctx, GLbitfield mask) 339{ 340 struct intel_context *intel = intel_context(ctx); 341 struct gl_framebuffer *fb = ctx->DrawBuffer; 342 GLuint clear_depth; 343 GLbitfield skipBuffers = 0; 344 unsigned int num_cliprects; 345 struct drm_clip_rect *cliprects; 346 int x_off, y_off; 347 BATCH_LOCALS; 348 349 /* 350 * Compute values for clearing the buffers. 351 */ 352 clear_depth = 0; 353 if (mask & BUFFER_BIT_DEPTH) { 354 clear_depth = (GLuint) (fb->_DepthMax * ctx->Depth.Clear); 355 } 356 if (mask & BUFFER_BIT_STENCIL) { 357 clear_depth |= (ctx->Stencil.Clear & 0xff) << 24; 358 } 359 360 /* If clearing both depth and stencil, skip BUFFER_BIT_STENCIL in 361 * the loop below. 362 */ 363 if ((mask & BUFFER_BIT_DEPTH) && (mask & BUFFER_BIT_STENCIL)) { 364 skipBuffers = BUFFER_BIT_STENCIL; 365 } 366 367 /* XXX Move this flush/lock into the following conditional? */ 368 intelFlush(&intel->ctx); 369 LOCK_HARDWARE(intel); 370 371 intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off); 372 if (num_cliprects) { 373 GLint cx, cy, cw, ch; 374 drm_clip_rect_t clear; 375 int i; 376 377 /* Get clear bounds after locking */ 378 cx = fb->_Xmin; 379 cy = fb->_Ymin; 380 cw = fb->_Xmax - cx; 381 ch = fb->_Ymax - cy; 382 383 if (fb->Name == 0) { 384 /* clearing a window */ 385 386 /* flip top to bottom */ 387 clear.x1 = cx + x_off; 388 clear.y1 = intel->driDrawable->y + intel->driDrawable->h - cy - ch; 389 clear.x2 = clear.x1 + cw; 390 clear.y2 = clear.y1 + ch; 391 } 392 else { 393 /* clearing FBO */ 394 assert(num_cliprects == 1); 395 assert(cliprects == &intel->fboRect); 396 clear.x1 = cx; 397 clear.y1 = cy; 398 clear.x2 = clear.x1 + cw; 399 clear.y2 = clear.y1 + ch; 400 /* no change to mask */ 401 } 402 403 for (i = 0; i < num_cliprects; i++) { 404 const drm_clip_rect_t *box = &cliprects[i]; 405 drm_clip_rect_t b; 406 GLuint buf; 407 GLuint clearMask = mask; /* use copy, since we modify it below */ 408 GLboolean all = (cw == fb->Width && ch == fb->Height); 409 410 if (!all) { 411 intel_intersect_cliprects(&b, &clear, box); 412 } 413 else { 414 b = *box; 415 } 416 417 if (b.x1 >= b.x2 || b.y1 >= b.y2) 418 continue; 419 420 if (0) 421 _mesa_printf("clear %d,%d..%d,%d, mask %x\n", 422 b.x1, b.y1, b.x2, b.y2, mask); 423 424 /* Loop over all renderbuffers */ 425 for (buf = 0; buf < BUFFER_COUNT && clearMask; buf++) { 426 const GLbitfield bufBit = 1 << buf; 427 if ((clearMask & bufBit) && !(bufBit & skipBuffers)) { 428 /* OK, clear this renderbuffer */ 429 struct intel_renderbuffer *irb = intel_get_renderbuffer(fb, buf); 430 dri_bo *write_buffer = 431 intel_region_buffer(intel, irb->region, 432 all ? INTEL_WRITE_FULL : 433 INTEL_WRITE_PART); 434 435 GLuint clearVal; 436 GLint pitch, cpp; 437 GLuint BR13, CMD; 438 439 pitch = irb->region->pitch; 440 cpp = irb->region->cpp; 441 442 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n", 443 __FUNCTION__, 444 irb->region->buffer, (pitch * cpp), 445 irb->region->draw_offset, 446 b.x1, b.y1, b.x2 - b.x1, b.y2 - b.y1); 447 448 BR13 = 0xf0 << 16; 449 CMD = XY_COLOR_BLT_CMD; 450 451 /* Setup the blit command */ 452 if (cpp == 4) { 453 BR13 |= BR13_8888; 454 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) { 455 if (clearMask & BUFFER_BIT_DEPTH) 456 CMD |= XY_BLT_WRITE_RGB; 457 if (clearMask & BUFFER_BIT_STENCIL) 458 CMD |= XY_BLT_WRITE_ALPHA; 459 } 460 else { 461 /* clearing RGBA */ 462 CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 463 } 464 } 465 else { 466 ASSERT(cpp == 2); 467 BR13 |= BR13_565; 468 } 469 470#ifndef I915 471 if (irb->region->tiling != I915_TILING_NONE) { 472 CMD |= XY_DST_TILED; 473 pitch /= 4; 474 } 475#endif 476 BR13 |= (pitch * cpp); 477 478 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) { 479 clearVal = clear_depth; 480 } 481 else { 482 uint8_t clear[4]; 483 GLclampf *color = ctx->Color.ClearColor; 484 485 CLAMPED_FLOAT_TO_UBYTE(clear[0], color[0]); 486 CLAMPED_FLOAT_TO_UBYTE(clear[1], color[1]); 487 CLAMPED_FLOAT_TO_UBYTE(clear[2], color[2]); 488 CLAMPED_FLOAT_TO_UBYTE(clear[3], color[3]); 489 490 switch (irb->texformat->MesaFormat) { 491 case MESA_FORMAT_ARGB8888: 492 clearVal = intel->ClearColor8888; 493 break; 494 case MESA_FORMAT_RGB565: 495 clearVal = intel->ClearColor565; 496 break; 497 case MESA_FORMAT_ARGB4444: 498 clearVal = PACK_COLOR_4444(clear[3], clear[0], 499 clear[1], clear[2]); 500 break; 501 case MESA_FORMAT_ARGB1555: 502 clearVal = PACK_COLOR_1555(clear[3], clear[0], 503 clear[1], clear[2]); 504 break; 505 default: 506 _mesa_problem(ctx, "Unexpected renderbuffer format: %d\n", 507 irb->texformat->MesaFormat); 508 clearVal = 0; 509 } 510 } 511 512 /* 513 _mesa_debug(ctx, "hardware blit clear buf %d rb id %d\n", 514 buf, irb->Base.Name); 515 */ 516 517 assert(b.x1 < b.x2); 518 assert(b.y1 < b.y2); 519 520 BEGIN_BATCH(6, REFERENCES_CLIPRECTS); 521 OUT_BATCH(CMD); 522 OUT_BATCH(BR13); 523 OUT_BATCH((b.y1 << 16) | b.x1); 524 OUT_BATCH((b.y2 << 16) | b.x2); 525 OUT_RELOC(write_buffer, 526 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 527 irb->region->draw_offset); 528 OUT_BATCH(clearVal); 529 ADVANCE_BATCH(); 530 clearMask &= ~bufBit; /* turn off bit, for faster loop exit */ 531 } 532 } 533 } 534 } 535 536 UNLOCK_HARDWARE(intel); 537} 538 539void 540intelEmitImmediateColorExpandBlit(struct intel_context *intel, 541 GLuint cpp, 542 GLubyte *src_bits, GLuint src_size, 543 GLuint fg_color, 544 GLshort dst_pitch, 545 dri_bo *dst_buffer, 546 GLuint dst_offset, 547 uint32_t dst_tiling, 548 GLshort x, GLshort y, 549 GLshort w, GLshort h, 550 GLenum logic_op) 551{ 552 int dwords = ALIGN(src_size, 8) / 4; 553 uint32_t opcode, br13, blit_cmd; 554 555 assert( logic_op - GL_CLEAR >= 0 ); 556 assert( logic_op - GL_CLEAR < 0x10 ); 557 558 if (w < 0 || h < 0) 559 return; 560 561 dst_pitch *= cpp; 562 563 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n", 564 __FUNCTION__, 565 dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords); 566 567 intel_batchbuffer_require_space( intel->batch, 568 (8 * 4) + 569 (3 * 4) + 570 dwords * 4, 571 REFERENCES_CLIPRECTS ); 572 573 opcode = XY_SETUP_BLT_CMD; 574 if (cpp == 4) 575 opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 576#ifndef I915 577 if (dst_tiling != I915_TILING_NONE) { 578 opcode |= XY_DST_TILED; 579 dst_pitch /= 4; 580 } 581#endif 582 583 br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29); 584 if (cpp == 2) 585 br13 |= BR13_565; 586 else 587 br13 |= BR13_8888; 588 589 blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */ 590 if (dst_tiling != I915_TILING_NONE) 591 blit_cmd |= XY_DST_TILED; 592 593 BEGIN_BATCH(8 + 3, REFERENCES_CLIPRECTS); 594 OUT_BATCH(opcode); 595 OUT_BATCH(br13); 596 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */ 597 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */ 598 OUT_RELOC(dst_buffer, 599 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 600 dst_offset); 601 OUT_BATCH(0); /* bg */ 602 OUT_BATCH(fg_color); /* fg */ 603 OUT_BATCH(0); /* pattern base addr */ 604 605 OUT_BATCH(blit_cmd | ((3 - 2) + dwords)); 606 OUT_BATCH((y << 16) | x); 607 OUT_BATCH(((y + h) << 16) | (x + w)); 608 ADVANCE_BATCH(); 609 610 intel_batchbuffer_data( intel->batch, 611 src_bits, 612 dwords * 4, 613 REFERENCES_CLIPRECTS ); 614 615 intel_batchbuffer_emit_mi_flush(intel->batch); 616} 617