intel_blit.c revision 7bae1c3d85344b7229e0124d1f54376392682430
1/************************************************************************** 2 * 3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 29#include "main/mtypes.h" 30#include "main/context.h" 31#include "main/enums.h" 32#include "main/colormac.h" 33 34#include "intel_blit.h" 35#include "intel_buffers.h" 36#include "intel_context.h" 37#include "intel_fbo.h" 38#include "intel_reg.h" 39#include "intel_regions.h" 40#include "intel_batchbuffer.h" 41#include "intel_mipmap_tree.h" 42 43#define FILE_DEBUG_FLAG DEBUG_BLIT 44 45static GLuint translate_raster_op(GLenum logicop) 46{ 47 switch(logicop) { 48 case GL_CLEAR: return 0x00; 49 case GL_AND: return 0x88; 50 case GL_AND_REVERSE: return 0x44; 51 case GL_COPY: return 0xCC; 52 case GL_AND_INVERTED: return 0x22; 53 case GL_NOOP: return 0xAA; 54 case GL_XOR: return 0x66; 55 case GL_OR: return 0xEE; 56 case GL_NOR: return 0x11; 57 case GL_EQUIV: return 0x99; 58 case GL_INVERT: return 0x55; 59 case GL_OR_REVERSE: return 0xDD; 60 case GL_COPY_INVERTED: return 0x33; 61 case GL_OR_INVERTED: return 0xBB; 62 case GL_NAND: return 0x77; 63 case GL_SET: return 0xFF; 64 default: return 0; 65 } 66} 67 68static uint32_t 69br13_for_cpp(int cpp) 70{ 71 switch (cpp) { 72 case 4: 73 return BR13_8888; 74 break; 75 case 2: 76 return BR13_565; 77 break; 78 case 1: 79 return BR13_8; 80 break; 81 default: 82 assert(0); 83 return 0; 84 } 85} 86 87/* Copy BitBlt 88 */ 89GLboolean 90intelEmitCopyBlit(struct intel_context *intel, 91 GLuint cpp, 92 GLshort src_pitch, 93 drm_intel_bo *src_buffer, 94 GLuint src_offset, 95 uint32_t src_tiling, 96 GLshort dst_pitch, 97 drm_intel_bo *dst_buffer, 98 GLuint dst_offset, 99 uint32_t dst_tiling, 100 GLshort src_x, GLshort src_y, 101 GLshort dst_x, GLshort dst_y, 102 GLshort w, GLshort h, 103 GLenum logic_op) 104{ 105 GLuint CMD, BR13, pass = 0; 106 int dst_y2 = dst_y + h; 107 int dst_x2 = dst_x + w; 108 drm_intel_bo *aper_array[3]; 109 BATCH_LOCALS; 110 111 if (dst_tiling != I915_TILING_NONE) { 112 if (dst_offset & 4095) 113 return GL_FALSE; 114 if (dst_tiling == I915_TILING_Y) 115 return GL_FALSE; 116 } 117 if (src_tiling != I915_TILING_NONE) { 118 if (src_offset & 4095) 119 return GL_FALSE; 120 if (src_tiling == I915_TILING_Y) 121 return GL_FALSE; 122 } 123 124 /* do space check before going any further */ 125 do { 126 aper_array[0] = intel->batch.bo; 127 aper_array[1] = dst_buffer; 128 aper_array[2] = src_buffer; 129 130 if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) { 131 intel_batchbuffer_flush(intel); 132 pass++; 133 } else 134 break; 135 } while (pass < 2); 136 137 if (pass >= 2) 138 return GL_FALSE; 139 140 intel_batchbuffer_require_space(intel, 8 * 4, true); 141 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n", 142 __FUNCTION__, 143 src_buffer, src_pitch, src_offset, src_x, src_y, 144 dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h); 145 146 src_pitch *= cpp; 147 dst_pitch *= cpp; 148 149 BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16; 150 151 switch (cpp) { 152 case 1: 153 case 2: 154 CMD = XY_SRC_COPY_BLT_CMD; 155 break; 156 case 4: 157 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 158 break; 159 default: 160 return GL_FALSE; 161 } 162 163#ifndef I915 164 if (dst_tiling != I915_TILING_NONE) { 165 CMD |= XY_DST_TILED; 166 dst_pitch /= 4; 167 } 168 if (src_tiling != I915_TILING_NONE) { 169 CMD |= XY_SRC_TILED; 170 src_pitch /= 4; 171 } 172#endif 173 174 if (dst_y2 <= dst_y || dst_x2 <= dst_x) { 175 return GL_TRUE; 176 } 177 178 assert(dst_x < dst_x2); 179 assert(dst_y < dst_y2); 180 181 BEGIN_BATCH_BLT(8); 182 OUT_BATCH(CMD); 183 OUT_BATCH(BR13 | (uint16_t)dst_pitch); 184 OUT_BATCH((dst_y << 16) | dst_x); 185 OUT_BATCH((dst_y2 << 16) | dst_x2); 186 OUT_RELOC_FENCED(dst_buffer, 187 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 188 dst_offset); 189 OUT_BATCH((src_y << 16) | src_x); 190 OUT_BATCH((uint16_t)src_pitch); 191 OUT_RELOC_FENCED(src_buffer, 192 I915_GEM_DOMAIN_RENDER, 0, 193 src_offset); 194 ADVANCE_BATCH(); 195 196 intel_batchbuffer_emit_mi_flush(intel); 197 198 return GL_TRUE; 199} 200 201 202/** 203 * Use blitting to clear the renderbuffers named by 'flags'. 204 * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field 205 * since that might include software renderbuffers or renderbuffers 206 * which we're clearing with triangles. 207 * \param mask bitmask of BUFFER_BIT_* values indicating buffers to clear 208 */ 209GLbitfield 210intelClearWithBlit(struct gl_context *ctx, GLbitfield mask) 211{ 212 struct intel_context *intel = intel_context(ctx); 213 struct gl_framebuffer *fb = ctx->DrawBuffer; 214 GLuint clear_depth; 215 GLboolean all; 216 GLint cx, cy, cw, ch; 217 GLbitfield fail_mask = 0; 218 BATCH_LOCALS; 219 220 /* 221 * Compute values for clearing the buffers. 222 */ 223 clear_depth = 0; 224 if (mask & BUFFER_BIT_DEPTH) { 225 clear_depth = (GLuint) (fb->_DepthMax * ctx->Depth.Clear); 226 } 227 if (mask & BUFFER_BIT_STENCIL) { 228 clear_depth |= (ctx->Stencil.Clear & 0xff) << 24; 229 } 230 231 cx = fb->_Xmin; 232 if (fb->Name == 0) 233 cy = ctx->DrawBuffer->Height - fb->_Ymax; 234 else 235 cy = fb->_Ymin; 236 cw = fb->_Xmax - fb->_Xmin; 237 ch = fb->_Ymax - fb->_Ymin; 238 239 if (cw == 0 || ch == 0) 240 return 0; 241 242 all = (cw == fb->Width && ch == fb->Height); 243 244 /* Loop over all renderbuffers */ 245 mask &= (1 << BUFFER_COUNT) - 1; 246 while (mask) { 247 GLuint buf = _mesa_ffs(mask) - 1; 248 struct intel_renderbuffer *irb; 249 drm_intel_bo *write_buffer; 250 int x1, y1, x2, y2; 251 uint32_t clear_val; 252 uint32_t BR13, CMD; 253 int pitch, cpp; 254 drm_intel_bo *aper_array[2]; 255 256 mask &= ~(1 << buf); 257 258 irb = intel_get_renderbuffer(fb, buf); 259 if (irb == NULL || irb->region == NULL || irb->region->buffer == NULL) { 260 fail_mask |= 1 << buf; 261 continue; 262 } 263 264 /* OK, clear this renderbuffer */ 265 write_buffer = intel_region_buffer(intel, irb->region, 266 all ? INTEL_WRITE_FULL : 267 INTEL_WRITE_PART); 268 x1 = cx + irb->region->draw_x; 269 y1 = cy + irb->region->draw_y; 270 x2 = cx + cw + irb->region->draw_x; 271 y2 = cy + ch + irb->region->draw_y; 272 273 pitch = irb->region->pitch; 274 cpp = irb->region->cpp; 275 276 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n", 277 __FUNCTION__, 278 irb->region->buffer, (pitch * cpp), 279 x1, y1, x2 - x1, y2 - y1); 280 281 BR13 = br13_for_cpp(cpp) | 0xf0 << 16; 282 CMD = XY_COLOR_BLT_CMD; 283 284 /* Setup the blit command */ 285 if (cpp == 4) { 286 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) { 287 if (mask & BUFFER_BIT_DEPTH) 288 CMD |= XY_BLT_WRITE_RGB; 289 if (mask & BUFFER_BIT_STENCIL) 290 CMD |= XY_BLT_WRITE_ALPHA; 291 } else { 292 /* clearing RGBA */ 293 CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 294 } 295 } 296 297 assert(irb->region->tiling != I915_TILING_Y); 298 299#ifndef I915 300 if (irb->region->tiling != I915_TILING_NONE) { 301 CMD |= XY_DST_TILED; 302 pitch /= 4; 303 } 304#endif 305 BR13 |= (pitch * cpp); 306 307 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) { 308 clear_val = clear_depth; 309 } else { 310 uint8_t clear[4]; 311 GLclampf *color = ctx->Color.ClearColor; 312 313 CLAMPED_FLOAT_TO_UBYTE(clear[0], color[0]); 314 CLAMPED_FLOAT_TO_UBYTE(clear[1], color[1]); 315 CLAMPED_FLOAT_TO_UBYTE(clear[2], color[2]); 316 CLAMPED_FLOAT_TO_UBYTE(clear[3], color[3]); 317 318 switch (irb->Base.Format) { 319 case MESA_FORMAT_ARGB8888: 320 case MESA_FORMAT_XRGB8888: 321 clear_val = PACK_COLOR_8888(clear[3], clear[0], 322 clear[1], clear[2]); 323 break; 324 case MESA_FORMAT_RGB565: 325 clear_val = PACK_COLOR_565(clear[0], clear[1], clear[2]); 326 break; 327 case MESA_FORMAT_ARGB4444: 328 clear_val = PACK_COLOR_4444(clear[3], clear[0], 329 clear[1], clear[2]); 330 break; 331 case MESA_FORMAT_ARGB1555: 332 clear_val = PACK_COLOR_1555(clear[3], clear[0], 333 clear[1], clear[2]); 334 break; 335 case MESA_FORMAT_A8: 336 clear_val = PACK_COLOR_8888(clear[3], clear[3], 337 clear[3], clear[3]); 338 break; 339 default: 340 fail_mask |= 1 << buf; 341 continue; 342 } 343 } 344 345 assert(x1 < x2); 346 assert(y1 < y2); 347 348 /* do space check before going any further */ 349 aper_array[0] = intel->batch.bo; 350 aper_array[1] = write_buffer; 351 352 if (drm_intel_bufmgr_check_aperture_space(aper_array, 353 ARRAY_SIZE(aper_array)) != 0) { 354 intel_batchbuffer_flush(intel); 355 } 356 357 BEGIN_BATCH_BLT(6); 358 OUT_BATCH(CMD); 359 OUT_BATCH(BR13); 360 OUT_BATCH((y1 << 16) | x1); 361 OUT_BATCH((y2 << 16) | x2); 362 OUT_RELOC_FENCED(write_buffer, 363 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 364 0); 365 OUT_BATCH(clear_val); 366 ADVANCE_BATCH(); 367 368 if (intel->always_flush_cache) 369 intel_batchbuffer_emit_mi_flush(intel); 370 371 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) 372 mask &= ~(BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL); 373 } 374 375 return fail_mask; 376} 377 378GLboolean 379intelEmitImmediateColorExpandBlit(struct intel_context *intel, 380 GLuint cpp, 381 GLubyte *src_bits, GLuint src_size, 382 GLuint fg_color, 383 GLshort dst_pitch, 384 drm_intel_bo *dst_buffer, 385 GLuint dst_offset, 386 uint32_t dst_tiling, 387 GLshort x, GLshort y, 388 GLshort w, GLshort h, 389 GLenum logic_op) 390{ 391 int dwords = ALIGN(src_size, 8) / 4; 392 uint32_t opcode, br13, blit_cmd; 393 394 if (dst_tiling != I915_TILING_NONE) { 395 if (dst_offset & 4095) 396 return GL_FALSE; 397 if (dst_tiling == I915_TILING_Y) 398 return GL_FALSE; 399 } 400 401 assert( logic_op - GL_CLEAR >= 0 ); 402 assert( logic_op - GL_CLEAR < 0x10 ); 403 assert(dst_pitch > 0); 404 405 if (w < 0 || h < 0) 406 return GL_TRUE; 407 408 dst_pitch *= cpp; 409 410 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n", 411 __FUNCTION__, 412 dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords); 413 414 intel_batchbuffer_require_space(intel, 415 (8 * 4) + 416 (3 * 4) + 417 dwords * 4, true); 418 419 opcode = XY_SETUP_BLT_CMD; 420 if (cpp == 4) 421 opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 422#ifndef I915 423 if (dst_tiling != I915_TILING_NONE) { 424 opcode |= XY_DST_TILED; 425 dst_pitch /= 4; 426 } 427#endif 428 429 br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29); 430 br13 |= br13_for_cpp(cpp); 431 432 blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */ 433 if (dst_tiling != I915_TILING_NONE) 434 blit_cmd |= XY_DST_TILED; 435 436 BEGIN_BATCH_BLT(8 + 3); 437 OUT_BATCH(opcode); 438 OUT_BATCH(br13); 439 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */ 440 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */ 441 OUT_RELOC_FENCED(dst_buffer, 442 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 443 dst_offset); 444 OUT_BATCH(0); /* bg */ 445 OUT_BATCH(fg_color); /* fg */ 446 OUT_BATCH(0); /* pattern base addr */ 447 448 OUT_BATCH(blit_cmd | ((3 - 2) + dwords)); 449 OUT_BATCH((y << 16) | x); 450 OUT_BATCH(((y + h) << 16) | (x + w)); 451 ADVANCE_BATCH(); 452 453 intel_batchbuffer_data(intel, src_bits, dwords * 4, true); 454 455 intel_batchbuffer_emit_mi_flush(intel); 456 457 return GL_TRUE; 458} 459 460/* We don't have a memmove-type blit like some other hardware, so we'll do a 461 * rectangular blit covering a large space, then emit 1-scanline blit at the 462 * end to cover the last if we need. 463 */ 464void 465intel_emit_linear_blit(struct intel_context *intel, 466 drm_intel_bo *dst_bo, 467 unsigned int dst_offset, 468 drm_intel_bo *src_bo, 469 unsigned int src_offset, 470 unsigned int size) 471{ 472 GLuint pitch, height; 473 GLboolean ok; 474 475 /* The pitch given to the GPU must be DWORD aligned, and 476 * we want width to match pitch. Max width is (1 << 15 - 1), 477 * rounding that down to the nearest DWORD is 1 << 15 - 4 478 */ 479 pitch = MIN2(size, (1 << 15) - 4); 480 height = size / pitch; 481 ok = intelEmitCopyBlit(intel, 1, 482 pitch, src_bo, src_offset, I915_TILING_NONE, 483 pitch, dst_bo, dst_offset, I915_TILING_NONE, 484 0, 0, /* src x/y */ 485 0, 0, /* dst x/y */ 486 pitch, height, /* w, h */ 487 GL_COPY); 488 assert(ok); 489 490 src_offset += pitch * height; 491 dst_offset += pitch * height; 492 size -= pitch * height; 493 assert (size < (1 << 15)); 494 assert ((size & 3) == 0); /* Pitch must be DWORD aligned */ 495 if (size != 0) { 496 ok = intelEmitCopyBlit(intel, 1, 497 size, src_bo, src_offset, I915_TILING_NONE, 498 size, dst_bo, dst_offset, I915_TILING_NONE, 499 0, 0, /* src x/y */ 500 0, 0, /* dst x/y */ 501 size, 1, /* w, h */ 502 GL_COPY); 503 assert(ok); 504 } 505} 506 507/** 508 * Used to initialize the alpha value of an ARGB8888 teximage after 509 * loading it from an XRGB8888 source. 510 * 511 * This is very common with glCopyTexImage2D(). 512 */ 513void 514intel_set_teximage_alpha_to_one(struct gl_context *ctx, 515 struct intel_texture_image *intel_image) 516{ 517 struct intel_context *intel = intel_context(ctx); 518 unsigned int image_x, image_y; 519 uint32_t x1, y1, x2, y2; 520 uint32_t BR13, CMD; 521 int pitch, cpp; 522 drm_intel_bo *aper_array[2]; 523 struct intel_region *region = intel_image->mt->region; 524 BATCH_LOCALS; 525 526 assert(intel_image->base.TexFormat == MESA_FORMAT_ARGB8888); 527 528 /* get dest x/y in destination texture */ 529 intel_miptree_get_image_offset(intel_image->mt, 530 intel_image->level, 531 intel_image->face, 532 0, 533 &image_x, &image_y); 534 535 x1 = image_x; 536 y1 = image_y; 537 x2 = image_x + intel_image->base.Width; 538 y2 = image_y + intel_image->base.Height; 539 540 pitch = region->pitch; 541 cpp = region->cpp; 542 543 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n", 544 __FUNCTION__, 545 intel_image->mt->region->buffer, (pitch * cpp), 546 x1, y1, x2 - x1, y2 - y1); 547 548 BR13 = br13_for_cpp(cpp) | 0xf0 << 16; 549 CMD = XY_COLOR_BLT_CMD; 550 CMD |= XY_BLT_WRITE_ALPHA; 551 552 assert(region->tiling != I915_TILING_Y); 553 554#ifndef I915 555 if (region->tiling != I915_TILING_NONE) { 556 CMD |= XY_DST_TILED; 557 pitch /= 4; 558 } 559#endif 560 BR13 |= (pitch * cpp); 561 562 /* do space check before going any further */ 563 aper_array[0] = intel->batch.bo; 564 aper_array[1] = region->buffer; 565 566 if (drm_intel_bufmgr_check_aperture_space(aper_array, 567 ARRAY_SIZE(aper_array)) != 0) { 568 intel_batchbuffer_flush(intel); 569 } 570 571 BEGIN_BATCH_BLT(6); 572 OUT_BATCH(CMD); 573 OUT_BATCH(BR13); 574 OUT_BATCH((y1 << 16) | x1); 575 OUT_BATCH((y2 << 16) | x2); 576 OUT_RELOC_FENCED(region->buffer, 577 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 578 0); 579 OUT_BATCH(0xffffffff); /* white, but only alpha gets written */ 580 ADVANCE_BATCH(); 581 582 intel_batchbuffer_emit_mi_flush(intel); 583} 584