intel_blit.c revision b17aab5753a6d14c9e757bedb186963b2dae8823
1/************************************************************************** 2 * 3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 29#include "main/mtypes.h" 30#include "main/context.h" 31#include "main/enums.h" 32#include "main/colormac.h" 33 34#include "intel_blit.h" 35#include "intel_buffers.h" 36#include "intel_context.h" 37#include "intel_fbo.h" 38#include "intel_reg.h" 39#include "intel_regions.h" 40#include "intel_batchbuffer.h" 41#include "intel_mipmap_tree.h" 42 43#define FILE_DEBUG_FLAG DEBUG_BLIT 44 45static GLuint translate_raster_op(GLenum logicop) 46{ 47 switch(logicop) { 48 case GL_CLEAR: return 0x00; 49 case GL_AND: return 0x88; 50 case GL_AND_REVERSE: return 0x44; 51 case GL_COPY: return 0xCC; 52 case GL_AND_INVERTED: return 0x22; 53 case GL_NOOP: return 0xAA; 54 case GL_XOR: return 0x66; 55 case GL_OR: return 0xEE; 56 case GL_NOR: return 0x11; 57 case GL_EQUIV: return 0x99; 58 case GL_INVERT: return 0x55; 59 case GL_OR_REVERSE: return 0xDD; 60 case GL_COPY_INVERTED: return 0x33; 61 case GL_OR_INVERTED: return 0xBB; 62 case GL_NAND: return 0x77; 63 case GL_SET: return 0xFF; 64 default: return 0; 65 } 66} 67 68static uint32_t 69br13_for_cpp(int cpp) 70{ 71 switch (cpp) { 72 case 4: 73 return BR13_8888; 74 break; 75 case 2: 76 return BR13_565; 77 break; 78 case 1: 79 return BR13_8; 80 break; 81 default: 82 assert(0); 83 return 0; 84 } 85} 86 87/* Copy BitBlt 88 */ 89GLboolean 90intelEmitCopyBlit(struct intel_context *intel, 91 GLuint cpp, 92 GLshort src_pitch, 93 drm_intel_bo *src_buffer, 94 GLuint src_offset, 95 uint32_t src_tiling, 96 GLshort dst_pitch, 97 drm_intel_bo *dst_buffer, 98 GLuint dst_offset, 99 uint32_t dst_tiling, 100 GLshort src_x, GLshort src_y, 101 GLshort dst_x, GLshort dst_y, 102 GLshort w, GLshort h, 103 GLenum logic_op) 104{ 105 GLuint CMD, BR13, pass = 0; 106 int dst_y2 = dst_y + h; 107 int dst_x2 = dst_x + w; 108 drm_intel_bo *aper_array[3]; 109 BATCH_LOCALS; 110 111 if (dst_tiling != I915_TILING_NONE) { 112 if (dst_offset & 4095) 113 return GL_FALSE; 114 if (dst_tiling == I915_TILING_Y) 115 return GL_FALSE; 116 } 117 if (src_tiling != I915_TILING_NONE) { 118 if (src_offset & 4095) 119 return GL_FALSE; 120 if (src_tiling == I915_TILING_Y) 121 return GL_FALSE; 122 } 123 124 /* do space check before going any further */ 125 do { 126 aper_array[0] = intel->batch.bo; 127 aper_array[1] = dst_buffer; 128 aper_array[2] = src_buffer; 129 130 if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) { 131 intel_batchbuffer_flush(intel); 132 pass++; 133 } else 134 break; 135 } while (pass < 2); 136 137 if (pass >= 2) 138 return GL_FALSE; 139 140 intel_batchbuffer_require_space(intel, 8 * 4, true); 141 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n", 142 __FUNCTION__, 143 src_buffer, src_pitch, src_offset, src_x, src_y, 144 dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h); 145 146 src_pitch *= cpp; 147 dst_pitch *= cpp; 148 149 /* For big formats (such as floating point), do the copy using 32bpp and 150 * multiply the coordinates. 151 */ 152 if (cpp > 4) { 153 assert(cpp % 4 == 0); 154 dst_x *= cpp / 4; 155 dst_x2 *= cpp / 4; 156 src_x *= cpp / 4; 157 cpp = 4; 158 } 159 160 BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16; 161 162 switch (cpp) { 163 case 1: 164 case 2: 165 CMD = XY_SRC_COPY_BLT_CMD; 166 break; 167 case 4: 168 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 169 break; 170 default: 171 return GL_FALSE; 172 } 173 174#ifndef I915 175 if (dst_tiling != I915_TILING_NONE) { 176 CMD |= XY_DST_TILED; 177 dst_pitch /= 4; 178 } 179 if (src_tiling != I915_TILING_NONE) { 180 CMD |= XY_SRC_TILED; 181 src_pitch /= 4; 182 } 183#endif 184 185 if (dst_y2 <= dst_y || dst_x2 <= dst_x) { 186 return GL_TRUE; 187 } 188 189 assert(dst_x < dst_x2); 190 assert(dst_y < dst_y2); 191 192 BEGIN_BATCH_BLT(8); 193 OUT_BATCH(CMD); 194 OUT_BATCH(BR13 | (uint16_t)dst_pitch); 195 OUT_BATCH((dst_y << 16) | dst_x); 196 OUT_BATCH((dst_y2 << 16) | dst_x2); 197 OUT_RELOC_FENCED(dst_buffer, 198 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 199 dst_offset); 200 OUT_BATCH((src_y << 16) | src_x); 201 OUT_BATCH((uint16_t)src_pitch); 202 OUT_RELOC_FENCED(src_buffer, 203 I915_GEM_DOMAIN_RENDER, 0, 204 src_offset); 205 ADVANCE_BATCH(); 206 207 intel_batchbuffer_emit_mi_flush(intel); 208 209 return GL_TRUE; 210} 211 212 213/** 214 * Use blitting to clear the renderbuffers named by 'flags'. 215 * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field 216 * since that might include software renderbuffers or renderbuffers 217 * which we're clearing with triangles. 218 * \param mask bitmask of BUFFER_BIT_* values indicating buffers to clear 219 */ 220GLbitfield 221intelClearWithBlit(struct gl_context *ctx, GLbitfield mask) 222{ 223 struct intel_context *intel = intel_context(ctx); 224 struct gl_framebuffer *fb = ctx->DrawBuffer; 225 GLuint clear_depth_value, clear_depth_mask; 226 GLboolean all; 227 GLint cx, cy, cw, ch; 228 GLbitfield fail_mask = 0; 229 BATCH_LOCALS; 230 231 /* 232 * Compute values for clearing the buffers. 233 */ 234 clear_depth_value = 0; 235 clear_depth_mask = 0; 236 if (mask & BUFFER_BIT_DEPTH) { 237 clear_depth_value = (GLuint) (fb->_DepthMax * ctx->Depth.Clear); 238 clear_depth_mask = XY_BLT_WRITE_RGB; 239 } 240 if (mask & BUFFER_BIT_STENCIL) { 241 clear_depth_value |= (ctx->Stencil.Clear & 0xff) << 24; 242 clear_depth_mask |= XY_BLT_WRITE_ALPHA; 243 } 244 245 cx = fb->_Xmin; 246 if (fb->Name == 0) 247 cy = ctx->DrawBuffer->Height - fb->_Ymax; 248 else 249 cy = fb->_Ymin; 250 cw = fb->_Xmax - fb->_Xmin; 251 ch = fb->_Ymax - fb->_Ymin; 252 253 if (cw == 0 || ch == 0) 254 return 0; 255 256 all = (cw == fb->Width && ch == fb->Height); 257 258 /* Loop over all renderbuffers */ 259 mask &= (1 << BUFFER_COUNT) - 1; 260 while (mask) { 261 GLuint buf = _mesa_ffs(mask) - 1; 262 GLboolean is_depth_stencil = buf == BUFFER_DEPTH || buf == BUFFER_STENCIL; 263 struct intel_renderbuffer *irb; 264 drm_intel_bo *write_buffer; 265 int x1, y1, x2, y2; 266 uint32_t clear_val; 267 uint32_t BR13, CMD; 268 int pitch, cpp; 269 drm_intel_bo *aper_array[2]; 270 271 mask &= ~(1 << buf); 272 273 irb = intel_get_renderbuffer(fb, buf); 274 if (irb == NULL || irb->region == NULL || irb->region->buffer == NULL) { 275 fail_mask |= 1 << buf; 276 continue; 277 } 278 279 /* OK, clear this renderbuffer */ 280 write_buffer = intel_region_buffer(intel, irb->region, 281 all ? INTEL_WRITE_FULL : 282 INTEL_WRITE_PART); 283 x1 = cx + irb->draw_x; 284 y1 = cy + irb->draw_y; 285 x2 = cx + cw + irb->draw_x; 286 y2 = cy + ch + irb->draw_y; 287 288 pitch = irb->region->pitch; 289 cpp = irb->region->cpp; 290 291 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n", 292 __FUNCTION__, 293 irb->region->buffer, (pitch * cpp), 294 x1, y1, x2 - x1, y2 - y1); 295 296 BR13 = 0xf0 << 16; 297 CMD = XY_COLOR_BLT_CMD; 298 299 /* Setup the blit command */ 300 if (cpp == 4) { 301 if (is_depth_stencil) { 302 CMD |= clear_depth_mask; 303 } else { 304 /* clearing RGBA */ 305 CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 306 } 307 } 308 309 assert(irb->region->tiling != I915_TILING_Y); 310 311#ifndef I915 312 if (irb->region->tiling != I915_TILING_NONE) { 313 CMD |= XY_DST_TILED; 314 pitch /= 4; 315 } 316#endif 317 BR13 |= (pitch * cpp); 318 319 if (is_depth_stencil) { 320 clear_val = clear_depth_value; 321 } else { 322 uint8_t clear[4]; 323 GLclampf *color = ctx->Color.ClearColor; 324 325 CLAMPED_FLOAT_TO_UBYTE(clear[0], color[0]); 326 CLAMPED_FLOAT_TO_UBYTE(clear[1], color[1]); 327 CLAMPED_FLOAT_TO_UBYTE(clear[2], color[2]); 328 CLAMPED_FLOAT_TO_UBYTE(clear[3], color[3]); 329 330 switch (irb->Base.Format) { 331 case MESA_FORMAT_ARGB8888: 332 case MESA_FORMAT_XRGB8888: 333 clear_val = PACK_COLOR_8888(clear[3], clear[0], 334 clear[1], clear[2]); 335 break; 336 case MESA_FORMAT_RGB565: 337 clear_val = PACK_COLOR_565(clear[0], clear[1], clear[2]); 338 break; 339 case MESA_FORMAT_ARGB4444: 340 clear_val = PACK_COLOR_4444(clear[3], clear[0], 341 clear[1], clear[2]); 342 break; 343 case MESA_FORMAT_ARGB1555: 344 clear_val = PACK_COLOR_1555(clear[3], clear[0], 345 clear[1], clear[2]); 346 break; 347 case MESA_FORMAT_A8: 348 clear_val = PACK_COLOR_8888(clear[3], clear[3], 349 clear[3], clear[3]); 350 break; 351 default: 352 fail_mask |= 1 << buf; 353 continue; 354 } 355 } 356 357 BR13 |= br13_for_cpp(cpp); 358 359 assert(x1 < x2); 360 assert(y1 < y2); 361 362 /* do space check before going any further */ 363 aper_array[0] = intel->batch.bo; 364 aper_array[1] = write_buffer; 365 366 if (drm_intel_bufmgr_check_aperture_space(aper_array, 367 ARRAY_SIZE(aper_array)) != 0) { 368 intel_batchbuffer_flush(intel); 369 } 370 371 BEGIN_BATCH_BLT(6); 372 OUT_BATCH(CMD); 373 OUT_BATCH(BR13); 374 OUT_BATCH((y1 << 16) | x1); 375 OUT_BATCH((y2 << 16) | x2); 376 OUT_RELOC_FENCED(write_buffer, 377 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 378 0); 379 OUT_BATCH(clear_val); 380 ADVANCE_BATCH(); 381 382 if (intel->always_flush_cache) 383 intel_batchbuffer_emit_mi_flush(intel); 384 385 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) 386 mask &= ~(BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL); 387 } 388 389 return fail_mask; 390} 391 392GLboolean 393intelEmitImmediateColorExpandBlit(struct intel_context *intel, 394 GLuint cpp, 395 GLubyte *src_bits, GLuint src_size, 396 GLuint fg_color, 397 GLshort dst_pitch, 398 drm_intel_bo *dst_buffer, 399 GLuint dst_offset, 400 uint32_t dst_tiling, 401 GLshort x, GLshort y, 402 GLshort w, GLshort h, 403 GLenum logic_op) 404{ 405 int dwords = ALIGN(src_size, 8) / 4; 406 uint32_t opcode, br13, blit_cmd; 407 408 if (dst_tiling != I915_TILING_NONE) { 409 if (dst_offset & 4095) 410 return GL_FALSE; 411 if (dst_tiling == I915_TILING_Y) 412 return GL_FALSE; 413 } 414 415 assert( logic_op - GL_CLEAR >= 0 ); 416 assert( logic_op - GL_CLEAR < 0x10 ); 417 assert(dst_pitch > 0); 418 419 if (w < 0 || h < 0) 420 return GL_TRUE; 421 422 dst_pitch *= cpp; 423 424 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n", 425 __FUNCTION__, 426 dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords); 427 428 intel_batchbuffer_require_space(intel, 429 (8 * 4) + 430 (3 * 4) + 431 dwords * 4, true); 432 433 opcode = XY_SETUP_BLT_CMD; 434 if (cpp == 4) 435 opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 436#ifndef I915 437 if (dst_tiling != I915_TILING_NONE) { 438 opcode |= XY_DST_TILED; 439 dst_pitch /= 4; 440 } 441#endif 442 443 br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29); 444 br13 |= br13_for_cpp(cpp); 445 446 blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */ 447 if (dst_tiling != I915_TILING_NONE) 448 blit_cmd |= XY_DST_TILED; 449 450 BEGIN_BATCH_BLT(8 + 3); 451 OUT_BATCH(opcode); 452 OUT_BATCH(br13); 453 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */ 454 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */ 455 OUT_RELOC_FENCED(dst_buffer, 456 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 457 dst_offset); 458 OUT_BATCH(0); /* bg */ 459 OUT_BATCH(fg_color); /* fg */ 460 OUT_BATCH(0); /* pattern base addr */ 461 462 OUT_BATCH(blit_cmd | ((3 - 2) + dwords)); 463 OUT_BATCH((y << 16) | x); 464 OUT_BATCH(((y + h) << 16) | (x + w)); 465 ADVANCE_BATCH(); 466 467 intel_batchbuffer_data(intel, src_bits, dwords * 4, true); 468 469 intel_batchbuffer_emit_mi_flush(intel); 470 471 return GL_TRUE; 472} 473 474/* We don't have a memmove-type blit like some other hardware, so we'll do a 475 * rectangular blit covering a large space, then emit 1-scanline blit at the 476 * end to cover the last if we need. 477 */ 478void 479intel_emit_linear_blit(struct intel_context *intel, 480 drm_intel_bo *dst_bo, 481 unsigned int dst_offset, 482 drm_intel_bo *src_bo, 483 unsigned int src_offset, 484 unsigned int size) 485{ 486 GLuint pitch, height; 487 GLboolean ok; 488 489 /* The pitch given to the GPU must be DWORD aligned, and 490 * we want width to match pitch. Max width is (1 << 15 - 1), 491 * rounding that down to the nearest DWORD is 1 << 15 - 4 492 */ 493 pitch = MIN2(size, (1 << 15) - 4); 494 height = size / pitch; 495 ok = intelEmitCopyBlit(intel, 1, 496 pitch, src_bo, src_offset, I915_TILING_NONE, 497 pitch, dst_bo, dst_offset, I915_TILING_NONE, 498 0, 0, /* src x/y */ 499 0, 0, /* dst x/y */ 500 pitch, height, /* w, h */ 501 GL_COPY); 502 assert(ok); 503 504 src_offset += pitch * height; 505 dst_offset += pitch * height; 506 size -= pitch * height; 507 assert (size < (1 << 15)); 508 assert ((size & 3) == 0); /* Pitch must be DWORD aligned */ 509 if (size != 0) { 510 ok = intelEmitCopyBlit(intel, 1, 511 size, src_bo, src_offset, I915_TILING_NONE, 512 size, dst_bo, dst_offset, I915_TILING_NONE, 513 0, 0, /* src x/y */ 514 0, 0, /* dst x/y */ 515 size, 1, /* w, h */ 516 GL_COPY); 517 assert(ok); 518 } 519} 520 521/** 522 * Used to initialize the alpha value of an ARGB8888 teximage after 523 * loading it from an XRGB8888 source. 524 * 525 * This is very common with glCopyTexImage2D(). 526 */ 527void 528intel_set_teximage_alpha_to_one(struct gl_context *ctx, 529 struct intel_texture_image *intel_image) 530{ 531 struct intel_context *intel = intel_context(ctx); 532 unsigned int image_x, image_y; 533 uint32_t x1, y1, x2, y2; 534 uint32_t BR13, CMD; 535 int pitch, cpp; 536 drm_intel_bo *aper_array[2]; 537 struct intel_region *region = intel_image->mt->region; 538 BATCH_LOCALS; 539 540 assert(intel_image->base.TexFormat == MESA_FORMAT_ARGB8888); 541 542 /* get dest x/y in destination texture */ 543 intel_miptree_get_image_offset(intel_image->mt, 544 intel_image->level, 545 intel_image->face, 546 0, 547 &image_x, &image_y); 548 549 x1 = image_x; 550 y1 = image_y; 551 x2 = image_x + intel_image->base.Width; 552 y2 = image_y + intel_image->base.Height; 553 554 pitch = region->pitch; 555 cpp = region->cpp; 556 557 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n", 558 __FUNCTION__, 559 intel_image->mt->region->buffer, (pitch * cpp), 560 x1, y1, x2 - x1, y2 - y1); 561 562 BR13 = br13_for_cpp(cpp) | 0xf0 << 16; 563 CMD = XY_COLOR_BLT_CMD; 564 CMD |= XY_BLT_WRITE_ALPHA; 565 566 assert(region->tiling != I915_TILING_Y); 567 568#ifndef I915 569 if (region->tiling != I915_TILING_NONE) { 570 CMD |= XY_DST_TILED; 571 pitch /= 4; 572 } 573#endif 574 BR13 |= (pitch * cpp); 575 576 /* do space check before going any further */ 577 aper_array[0] = intel->batch.bo; 578 aper_array[1] = region->buffer; 579 580 if (drm_intel_bufmgr_check_aperture_space(aper_array, 581 ARRAY_SIZE(aper_array)) != 0) { 582 intel_batchbuffer_flush(intel); 583 } 584 585 BEGIN_BATCH_BLT(6); 586 OUT_BATCH(CMD); 587 OUT_BATCH(BR13); 588 OUT_BATCH((y1 << 16) | x1); 589 OUT_BATCH((y2 << 16) | x2); 590 OUT_RELOC_FENCED(region->buffer, 591 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 592 0); 593 OUT_BATCH(0xffffffff); /* white, but only alpha gets written */ 594 ADVANCE_BATCH(); 595 596 intel_batchbuffer_emit_mi_flush(intel); 597} 598